-- ******************************************************************** -- -- Boundary Scan Description Language (BSDL) for Zarlink MT93L00av IC -- File name : mt9300av.bsd -- DEVICE : Zarlink MT93L00av Multi-Channel Voice Echo Canceller -- BSDL revision : STD_1149_1_1994 -- Date created: Dec 22, 1998 -- Last Updated: Nov 20, 2001 -- Documentation: MT93L00av Advance Information Data Sheet -- Packages: 208-pin LBGA -- -- ******************************************************************** -- IMPORTANT NOTICE -- -- -- ZARLINK and MT93L00 are trademarks of ZARLINK Semiconductor. ZARLINK -- products, marketed under trademarks, are protected under numerous US -- and foreign patents and pending applications, maskwork rights, and -- copyrights. -- -- ZARLINK reserves the right to make changes to any products and -- services at any time without notice. ZARLINK assumes no -- responsibility or liability arising out of the application or use of -- any information, product, or service described herein except as -- expressly agreed to in writing by ZARLINK Corporation. ZARLINK -- customers are advised to obtain the latest version of device -- specifications before relying on any published information and before -- placing orders for products or services. -- ******************************************************************** -- Modification History: -- Initial release: Dec 22, 1998 -- ................................................................. -- 1.9.2000 VSN Systems / JTAG Technologies BV (JD) -- Changed disable value from 0 to 1 for the following nets: -- D[0..7], Rout, Sout, Dtab and IRQb -- ................................................................. -- Removed TAP_SCAN_RESET from Scan port identification Nov 20, 2001 -- ******************************************************************** entity MT93L00av is generic (PHYSICAL_PIN_MAP:string:="LBGA_208"); port ( RESETb : in bit; MCLK : in bit; Fsel : in bit; -- st-bus port C4ib : in bit; F0ib : in bit; Rin : in bit; Sin : in bit; Rout : out bit; Sout : out bit; ODE : in bit; -- internal connections IC0 : in bit_vector(0 to 13); IC0_14 : linkage bit; -- This is the MSBit of -- the IC0 vector, and has been renamed IC0_14 because this is -- a linkage bit, rather than an in bit. Not in BS chain. -- microport DSb : in bit; CSb : in bit; R_Wb : in bit; A : in bit_vector(0 to 10); D : inout bit_vector(0 to 7); DTAb : out bit; IRQb : out bit; -- TAP Controller TCK : in bit; TMS : in bit; TDI : in bit; TRSTb : in bit; TDO : out bit; -- Supplies and NC VDD1 : linkage bit_vector(1 to 42); -- not in BS chain VDD2 : linkage bit_vector(1 to 8); -- not in BS chain GND : linkage bit_vector(1 to 84); -- not in BS chain NC : linkage bit_vector(1 to 18); -- not in BS chain PLLVDD : linkage bit; -- not in BS chain PLLGND : linkage bit -- not in BS chain ); --end of ports -- BSDL description conforms to 1994 standard use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of MT93L00av: entity is "STD_1149_1_1993"; attribute PIN_MAP of MT93L00av: entity is PHYSICAL_PIN_MAP; constant LBGA_208: PIN_MAP_STRING:= "IRQb:R9,"& "DSb:R11,"& "CSb:R13,"& "R_Wb:R5,"& "DTAb:R7,"& "ODE:B13,"& "Sout:A8,"& "Rout:B9,"& "Sin:B11,"& "Rin:B7,"& "F0ib:B5,"& "C4ib:A4,"& "MCLK:G2,"& "Fsel:H2,"& "RESETb:R3,"& "D:( T2, T4, T6, T8, T9, T11, T13, T15),"& "A:( P16, N16, M16, L16, K16, J16, H16, G16, F16, E16, D16),"& "IC0:( E15, F15, A12, A10, A6, A2, B1, B3, C1,"& "C2, D2, E2, J2, K2),"& "IC0_14:R1,"& -- TAP controller pins "TMS:M2,"& "TDI:M1,"& "TDO:N1,"& "TCK:P1,"& "TRSTb:N2,"& -- Pins not scanned by boundary-scan "GND:( A1, A3, A7, A11, A13, A15, A16, B2, B6, B8, B12, B14, B15, B16, C3, C5,"& "C7, C9, C11, C12, C13, C14, C16, D4, D8, D10, D12, D13, E3, E4, E14, F13,"& "G3, G4, G7, G8, G9, G10, H7, H8, H9, H10, H13, H14, J7, J8, J9, J10,"& "K7, K8, K9, K10, K13, K14, L3, L4, M13, M14, M15, N3, N4, N5, N7, N9,"& "N11, N13, P2, P3, P5, P7, P9, P11, P13, P14, R2, R14, R15, R16, T1,"& "T3, T7, T10, T14, T16),"& "VDD1:( A5, A9, B4, B10, C4, C8, C10, D3, D5, D7, D9, D11, D14, E13, F3, F4, F14,"& "H3, H4, J13, J14, L13, L14, M3, M4, N6, N8, N10, N14, N15, P4, P6, P8,"& "P10, P15, R4, R6, R8, R10, R12, T5, T12),"& "VDD2:( C6, D6, J3, J4, N12, P12, G13, G14),"& "PLLGND:K3,"& "PLLVDD:K4,"& "NC:( A14, C15, D1, D15, E1, F1, G1, G15, H1, H15, J1, J15, K1, K15, L1, L15, F2, L2)"; -- Scan port identification attribute TAP_SCAN_IN of TDI: signal is true; attribute TAP_SCAN_MODE of TMS: signal is true; attribute TAP_SCAN_OUT of TDO: signal is true; attribute TAP_SCAN_CLOCK of TCK: signal is (10.00e6, BOTH); -- TAP Description attribute INSTRUCTION_LENGTH of MT93L00av: entity is 3; attribute INSTRUCTION_OPCODE of MT93L00av: entity is "BYPASS (111),"& "IDCODE (001),"& "EXTEST (000),"& "SAMPLE (010, 011, 100, 101, 110)"; attribute INSTRUCTION_CAPTURE of MT93L00av: entity is "001"; -- ID code attribute IDCODE_REGISTER of MT93L00av: entity is "0000" & -- 4-bit version (0) "1001001100000000" & -- 16-bit part number 9300 "00010100101" & -- 11-bit manufacturer (Mitel) "1"; -- mandatory LSB attribute BOUNDARY_LENGTH of MT93L00av: entity is 60; -- THE BOUNDARY SCAN CHAIN -- The first cell (i.e., numbered 0) is closest to TDO attribute BOUNDARY_REGISTER of MT93L00av: entity is -- num cell port function safe [ccell disval rslt] ----------------------------------------------------------------- "59 (BC_4, RESETb, input, 0), "& "58 (BC_4, MCLK, clock, X), "& "57 (BC_4, Fsel, input, X), "& "56 (BC_4, IC0(9), input, 0), "& "55 (BC_4, IC0(10), input, 0), "& "54 (BC_4, IC0(11), input, 0), "& "53 (BC_4, C4ib, clock, X), "& "52 (BC_4, F0ib, input, X), "& "51 (BC_4, Rin, input, X), "& "50 (BC_4, Sin, input, X), "& "49 (BC_1, Rout, output3, X, 47, 1, Z), "& "48 (BC_1, Sout, output3, X, 47, 1, Z), "& "47 (BC_1, *, control, X), "& "46 (BC_4, ODE, input, X), "& "45 (BC_4, IC0(3), input, X), "& "44 (BC_4, IC0(4), input, X), "& "43 (BC_4, IC0(5), input, X), "& "42 (BC_4, IC0(6), input, X), "& "41 (BC_4, IC0(7), input, X), "& "40 (BC_4, IC0(8), input, X), "& "39 (BC_4, IC0(2), input, X), "& "38 (BC_4, IC0(12), input, X), "& "37 (BC_4, IC0(13), input, X), "& "36 (BC_4, DSb, input, X), "& "35 (BC_4, CSb, input, X), "& "34 (BC_4, R_Wb, input, X), "& "33 (BC_1, DTAb, output3, X, 32, 1, Weak1), "& "32 (BC_1, *, control, X), "& "31 (BC_4, A(0), input, X), "& "30 (BC_4, A(1), input, X), "& "29 (BC_4, A(2), input, X), "& "28 (BC_4, A(3), input, X), "& "27 (BC_4, A(4), input, X), "& "26 (BC_4, IC0(0), input, X), "& "25 (BC_4, IC0(1), input, X), "& "24 (BC_4, A(5), input, X), "& "23 (BC_4, A(6), input, X), "& "22 (BC_4, A(7), input, X), "& "21 (BC_4, A(8), input, X), "& "20 (BC_4, A(9), input, X), "& "19 (BC_4, A(10), input, X), "& "18 (BC_4, D(0), input, X), "& "17 (BC_1, D(0), output3, X, 2, 1, Z), "& "16 (BC_4, D(1), input, X), "& "15 (BC_1, D(1), output3, X, 2, 1, Z), "& "14 (BC_4, D(2), input, X), "& "13 (BC_1, D(2), output3, X, 2, 1, Z), "& "12 (BC_4, D(3), input, X), "& "11 (BC_1, D(3), output3, X, 2, 1, Z), "& "10 (BC_4, D(4), input, X), "& "9 (BC_1, D(4), output3, X, 2, 1, Z), "& "8 (BC_4, D(5), input, X), "& "7 (BC_1, D(5), output3, X, 2, 1, Z), "& "6 (BC_4, D(6), input, X), "& "5 (BC_1, D(6), output3, X, 2, 1, Z), "& "4 (BC_4, D(7), input, X), "& "3 (BC_1, D(7), output3, X, 2, 1, Z), "& "2 (BC_1, *, control, X), "& "1 (BC_1, IRQb, output3, X, 0, 1, Weak1), "& "0 (BC_1, *, control, X) "; end MT93L00av;