------------------------------------------------------------------------------- -- SA-1100.bsdl -- The BSDL Description for SA-1100 IEEE 1149.1 Circuits ------------------------------------------------------------------------------- -- Revision History -- Rev who Date Description -- 00 YunChii 04-AUG-1997 Taken the bsdl code from DC1035 -- StrongARM SA-110 -- 01 J. Belkin Cleaned up file. -- 02 Richard Reis Added 3 missing scan cells between -- cells 11 & 12. -- 03 J. Belkin 18-AUG-1997 Corrected for inverted control cells, -- transposed UCDP/UCPN pinning, -- changed PWREN BSR bit to "internal" -- 04 Validated by Corelis (562)926-6727, 08-APR-1999, BC7 cell type replaced. -- 05 J. Cooper 20-APR-1999 Adapted for 256 Mini-Ball Grid Array Package. ------------------------------------------------------------------------------- entity SA1100 is -- (ref B.8) generic (PHYSICAL_PIN_MAP: string:= "MBGA_256"); -- (ref B.8.2) port( -- (ref B.8.3) RXDC :inout bit; TXDC :inout bit; D :inout bit_vector (31 downto 0); GP :inout bit_vector (27 downto 0); LBIAS :inout bit; LPCLK :inout bit; LDD :inout bit_vector (7 downto 0); LLCLK :inout bit; LFCLK :inout bit; POE :buffer bit; PWE :buffer bit; PIOR :buffer bit; PIOW :buffer bit; PSKTSEL :buffer bit; IOIS16 :in bit; PWAIT :in bit; PREG :buffer bit; PCE2 :buffer bit; PCE1 :buffer bit; WE :out bit; OE :out bit; RAS :out bit_vector (3 downto 0); CAS :out bit_vector (3 downto 0); CS :out bit_vector (3 downto 0); A :out bit_vector (25 downto 0); UDCP :inout bit; UDCN :inout bit; RXD1 :inout bit; TXD1 :inout bit; RXD2 :inout bit; TXD2 :inout bit; RXD3 :inout bit; TXD3 :inout bit; TXTAL :linkage bit; TEXTAL :linkage bit; PEXTAL :linkage bit; PXTAL :linkage bit; RESET :in bit; RESETO :buffer bit; ROMSEL :in bit; TCKBYP :linkage bit; TESTCLK :linkage bit; TMS :in bit; TCK :in bit; TDI :in bit; TDO :out bit; TRST :in bit; BATTF :in bit; VDDFA :in bit; PWREN :linkage bit; SFRMC :inout bit; SCLKC :inout bit; VDDR :linkage bit; VDDX :linkage bit_vector (48 downto 0); VSSX :linkage bit_vector (36 downto 0); VDD :linkage bit_vector (8 downto 0); VSS :linkage bit_vector (8 downto 0) ) ; use STD_1149_1_1994.all ; -- (ref B.8.4) -- changed to 1990 for Teradyne Victory compiler -- "COMPILERSENSITIVE" -- use STD_1149_1_1990.all ; -- "COMPILERSENSITIVE" attribute COMPONENT_CONFORMANCE of SA1100: entity is "STD_1149_1_1993"; -- (ref B.8.6) attribute PIN_MAP of SA1100 : entity is PHYSICAL_PIN_MAP ; -- (ref B.8.7) constant MBGA_256 : PIN_MAP_STRING := "BATTF: A4, " & "PWREN: A3, " & "SCLKC: A2, " & "D: ( P2, M1, L1, K2, J3, H4, F2, E3, P3, M2, " & " L2, K3, H2, G3, F3, F4, N2, M3, L3, K4, " & " H3, G2, E1, D1, N3, M4, K1, J1, G1, F1, " & " E2, D2), " & "GP: ( R1, T1, R2, P4, T2, R3, T3, R4, T4, P5, " & " R5, T5, N6, P6, R6, R7, T6, P7, T7, N8, " & " P8, R8, P9, T9, N10, R10, P10, T10), " & "LBIAS: R11, " & "LPCLK: P11, " & "LDD: ( T13, R13, T12, P13, P12, R12, T11, N12), " & "LLCLK: R14, " & "LFCLK: T14, " & "POE: R15, " & "PWE: T15, " & "PIOR: P14, " & "PIOW: P15, " & "PSKTSEL: P16, " & "IOIS16: N15, " & "PWAIT: N16, " & "PREG: N14, " & "PCE2: M13, " & "PCE1: M15, " & "WE: M14, " & "OE: M16, " & "RAS: ( L15, L14, L16, K13), " & "CAS: ( K15, K14, K16, J15), " & "CS: ( H14, H13, H16, H15), " & "A: ( G14, G16, G15, F15, F14, F13, F16, E15, E14, E16, " & " D14, D15, C16, B16, C14, B14, B15, A16, A15, A14, " & " B13, C13, A13, B12, C12, D12), " & "UDCN: A12, " & "UDCP: C11, " & "RXD1: B11, " & "TXD1: A11, " & "RXD2: B10, " & "TXD2: D10, " & "RXD3: C10, " & "TXD3: A10, " & "RESET: B7, " & "RESETO: C7, " & "ROMSEL: D6, " & "TXTAL: B9, " & "RXDC: B1, " & "TXDC: C2, " & "TEXTAL: C9, " & "PEXTAL: A8, " & "PXTAL: B8, " & "TCKBYP: A6, " & "TESTCLK: B6, " & "TMS: C6, " & "TCK: C5, " & "TDI: A5, " & "TDO: B5, " & "TRST: B4, " & "VDDFA: C4, " & "SFRMC: B3, " & "VDDR: D7, " & "VDDX: ( J13, K5, D13, K12, E4, D5, D9, K10, D11, K11, " & " L4, L5, L12, L13, M5, E6, E7, L10, E8, L11, " & " E9, E10, E11, M6, M7, M8, M9, M10, M11, N7, " & " N9, N11, E12, E13, F5, F12, G4, G5, G12, G13, " & " H5, H12, J4, J5, J12, M12, N4, N5, N13), " & "VSSX: ( A1, B2, C3, D4, E5, F6, F7, F8, F9, F10, " & " F11, G6, G7, G8, G9, G10, G11, H6, H7, H8, " & " H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, " & " K7, K8, K9, L6, L7, L8, L9), " & "VDD: ( C1, H1, N1, T8, R16, J14, C15, C8, A7), " & "VSS: ( D3, J2, P1, R9, T16, J16, D16, A9, D8) "; attribute TAP_SCAN_CLOCK of TCK : signal is (16.60e6, LOW); -- (Ref B.8.9) attribute TAP_SCAN_IN of TDI : signal is TRUE; attribute TAP_SCAN_OUT of TDO : signal is TRUE; attribute TAP_SCAN_MODE of TMS : signal is TRUE; attribute TAP_SCAN_RESET of TRST : signal is TRUE; attribute INSTRUCTION_LENGTH of SA1100 : entity is 5 ; -- (Ref B.8.11) attribute INSTRUCTION_OPCODE of SA1100 : entity is "EXTEST (00000)," & "SAMPLE (00001)," & "CLAMP (00100)," & "HIGHZ (00101)," & "IDCODE (00110)," & "BYPASS (11111)" ; attribute INSTRUCTION_CAPTURE of SA1100 : entity is "00001" ; -- attribute INSTRUCTION_PRIVATE of SA1100 : entity is "Private"; -- "COMPILERSENSITIVE" Comment out -- if unsupported by the compile -- ID Register Description attribute IDCODE_REGISTER of SA1100: entity is "X001" & -- Version "0001000010000100" & -- Part Number "00000110101" & -- Manufacturer "1"; -- Mandatory LSB attribute REGISTER_ACCESS of SA1100 : entity is -- (ref B.8.13) "BOUNDARY (EXTEST, SAMPLE)," & -- Redundant. Added for completeness "BYPASS (BYPASS, HIGHZ, CLAMP)"; -- ditto -- "DIE_ID[32] (DIE_ID)"; attribute BOUNDARY_LENGTH of SA1100 : entity is 279 ; -- (ref B.8.14) attribute BOUNDARY_REGISTER of SA1100 : entity is ------------------------------------------------------------------------------ -- scan cell cntr disable disable -- cell type port function safe cell value state ------------------------------------------------------------------------------ "278 (BC_4, BATTF, INPUT, x), " & "277 (BC_4, VDDFA, INPUT, x), " & "276 (BC_4, *, internal,x), " & "275 (BC_2, *, control, 0), " & "274 (BC_1, SFRMC, OUTPUT3, x, 275, 0, Z ), " & "273 (BC_4, SFRMC, INPUT, x), " & "272 (BC_2, *, control, 0), " & "271 (BC_1, SCLKC, OUTPUT3, x, 272, 0, Z ), " & "270 (BC_4, SCLKC, INPUT, x), " & "269 (BC_2, *, control, 0), " & "268 (BC_1, RXDC, OUTPUT3, x, 269, 0, Z ), " & "267 (BC_4, RXDC, INPUT, x), " & "266 (BC_2, *, control, 0), " & "265 (BC_1, TXDC, OUTPUT3, x, 266, 0, Z ), " & "264 (BC_4, TXDC, INPUT, x), " & "263 (BC_1, D(0), OUTPUT3, x, 199, 1, Z ), " & "262 (BC_4, D(0), INPUT, x), " & "261 (BC_1, D(8), OUTPUT3, x, 199, 1, Z ), " & "260 (BC_4, D(8), INPUT, x), " & "259 (BC_1, D(16), OUTPUT3, x, 199, 1, Z ), " & "258 (BC_4, D(16), INPUT, x), " & "257 (BC_1, D(24), OUTPUT3, x, 199, 1, Z ), " & "256 (BC_4, D(24), INPUT, x), " & "255 (BC_1, D(1), OUTPUT3, x, 199, 1, Z ), " & "254 (BC_4, D(1), INPUT, x), " & "253 (BC_1, D(9), OUTPUT3, x, 199, 1, Z ), " & "252 (BC_4, D(9), INPUT, x), " & "251 (BC_1, D(17), OUTPUT3, x, 199, 1, Z ), " & "250 (BC_4, D(17), INPUT, x), " & "249 (BC_1, D(25), OUTPUT3, x, 199, 1, Z ), " & "248 (BC_4, D(25), INPUT, x), " & "247 (BC_1, D(2), OUTPUT3, x, 199, 1, Z ), " & "246 (BC_4, D(2), INPUT, x), " & "245 (BC_1, D(10), OUTPUT3, x, 199, 1, Z ), " & "244 (BC_4, D(10), INPUT, x), " & "243 (BC_1, D(18), OUTPUT3, x, 199, 1, Z ), " & "242 (BC_4, D(18), INPUT, x), " & "241 (BC_1, D(26), OUTPUT3, x, 199, 1, Z ), " & "240 (BC_4, D(26), INPUT, x), " & "239 (BC_1, D(3), OUTPUT3, x, 199, 1, Z ), " & "238 (BC_4, D(3), INPUT, x), " & "237 (BC_1, D(11), OUTPUT3, x, 199, 1, Z ), " & "236 (BC_4, D(11), INPUT, x), " & "235 (BC_1, D(19), OUTPUT3, x, 199, 1, Z ), " & "234 (BC_4, D(19), INPUT, x), " & "233 (BC_1, D(27), OUTPUT3, x, 199, 1, Z ), " & "232 (BC_4, D(27), INPUT, x), " & "231 (BC_1, D(4), OUTPUT3, x, 199, 1, Z ), " & "230 (BC_4, D(4), INPUT, x), " & "229 (BC_1, D(12), OUTPUT3, x, 199, 1, Z ), " & "228 (BC_4, D(12), INPUT, x), " & "227 (BC_1, D(20), OUTPUT3, x, 199, 1, Z ), " & "226 (BC_4, D(20), INPUT, x), " & "225 (BC_1, D(28), OUTPUT3, x, 199, 1, Z ), " & "224 (BC_4, D(28), INPUT, x), " & "223 (BC_1, D(5), OUTPUT3, x, 199, 1, Z ), " & "222 (BC_4, D(5), INPUT, x), " & "221 (BC_1, D(13), OUTPUT3, x, 199, 1, Z ), " & "220 (BC_4, D(13), INPUT, x), " & "219 (BC_1, D(21), OUTPUT3, x, 199, 1, Z ), " & "218 (BC_4, D(21), INPUT, x), " & "217 (BC_1, D(29), OUTPUT3, x, 199, 1, Z ), " & "216 (BC_4, D(29), INPUT, x), " & "215 (BC_1, D(6), OUTPUT3, x, 199, 1, Z ), " & "214 (BC_4, D(6), INPUT, x), " & "213 (BC_1, D(14), OUTPUT3, x, 199, 1, Z ), " & "212 (BC_4, D(14), INPUT, x), " & "211 (BC_1, D(22), OUTPUT3, x, 199, 1, Z ), " & "210 (BC_4, D(22), INPUT, x), " & "209 (BC_1, D(30), OUTPUT3, x, 199, 1, Z ), " & "208 (BC_4, D(30), INPUT, x), " & "207 (BC_1, D(7), OUTPUT3, x, 199, 1, Z ), " & "206 (BC_4, D(7), INPUT, x), " & "205 (BC_1, D(15), OUTPUT3, x, 199, 1, Z ), " & "204 (BC_4, D(15), INPUT, x), " & "203 (BC_1, D(23), OUTPUT3, x, 199, 1, Z ), " & "202 (BC_4, D(23), INPUT, x), " & "201 (BC_1, D(31), OUTPUT3, x, 199, 1, Z ), " & "200 (BC_4, D(31), INPUT, x), " & "199 (BC_2, *, control, 1), " & "198 (BC_2, *, control, 0), " & "197 (BC_1, GP(27), OUTPUT3, x, 198, 0, Z ), " & "196 (BC_4, GP(27), INPUT, x), " & "195 (BC_2, *, control, 0), " & "194 (BC_1, GP(26), OUTPUT3, x, 195, 0, Z ), " & "193 (BC_4, GP(26), INPUT, x), " & "192 (BC_2, *, control, 0), " & "191 (BC_1, GP(25), OUTPUT3, x, 192, 0, Z ), " & "190 (BC_4, GP(25), INPUT, x), " & "189 (BC_2, *, control, 0), " & "188 (BC_1, GP(24), OUTPUT3, x, 189, 0, Z ), " & "187 (BC_4, GP(24), INPUT, x), " & "186 (BC_2, *, control, 0), " & "185 (BC_1, GP(23), OUTPUT3, x, 186, 0, Z ), " & "184 (BC_4, GP(23), INPUT, x), " & "183 (BC_2, *, control, 0), " & "182 (BC_1, GP(22), OUTPUT3, x, 183, 0, Z ), " & "181 (BC_4, GP(22), INPUT, x), " & "180 (BC_2, *, control, 0), " & "179 (BC_1, GP(21), OUTPUT3, x, 180, 0, Z ), " & "178 (BC_4, GP(21), INPUT, x), " & "177 (BC_2, *, control, 0), " & "176 (BC_1, GP(20), OUTPUT3, x, 177, 0, Z ), " & "175 (BC_4, GP(20), INPUT, x), " & "174 (BC_2, *, control, 0), " & "173 (BC_1, GP(19), OUTPUT3, x, 174, 0, Z ), " & "172 (BC_4, GP(19), INPUT, x), " & "171 (BC_2, *, control, 0), " & "170 (BC_1, GP(18), OUTPUT3, x, 171, 0, Z ), " & "169 (BC_4, GP(18), INPUT, x), " & "168 (BC_2, *, control, 0), " & "167 (BC_1, GP(17), OUTPUT3, x, 168, 0, Z ), " & "166 (BC_4, GP(17), INPUT, x), " & "165 (BC_2, *, control, 0), " & "164 (BC_1, GP(16), OUTPUT3, x, 165, 0, Z ), " & "163 (BC_4, GP(16), INPUT, x), " & "162 (BC_2, *, control, 0), " & "161 (BC_1, GP(15), OUTPUT3, x, 162, 0, Z ), " & "160 (BC_4, GP(15), INPUT, x), " & "159 (BC_2, *, control, 0), " & "158 (BC_1, GP(14), OUTPUT3, x, 159, 0, Z ), " & "157 (BC_4, GP(14), INPUT, x), " & "156 (BC_2, *, control, 0), " & "155 (BC_1, GP(13), OUTPUT3, x, 156, 0, Z ), " & "154 (BC_4, GP(13), INPUT, x), " & "153 (BC_2, *, control, 0), " & "152 (BC_1, GP(12), OUTPUT3, x, 153, 0, Z ), " & "151 (BC_4, GP(12), INPUT, x), " & "150 (BC_2, *, control, 0), " & "149 (BC_1, GP(11), OUTPUT3, x, 150, 0, Z ), " & "148 (BC_4, GP(11), INPUT, x), " & "147 (BC_2, *, control, 0), " & "146 (BC_1, GP(10), OUTPUT3, x, 147, 0, Z ), " & "145 (BC_4, GP(10), INPUT, x), " & "144 (BC_2, *, control, 0), " & "143 (BC_1, GP(9), OUTPUT3, x, 144, 0, Z ), " & "142 (BC_4, GP(9), INPUT, x), " & "141 (BC_2, *, control, 0), " & "140 (BC_1, GP(8), OUTPUT3, x, 141, 0, Z ), " & "139 (BC_4, GP(8), INPUT, x), " & "138 (BC_2, *, control, 0), " & "137 (BC_1, GP(7), OUTPUT3, x, 138, 0, Z ), " & "136 (BC_4, GP(7), INPUT, x), " & "135 (BC_2, *, control, 0), " & "134 (BC_1, GP(6), OUTPUT3, x, 135, 0, Z ), " & "133 (BC_4, GP(6), INPUT, x), " & "132 (BC_2, *, control, 0), " & "131 (BC_1, GP(5), OUTPUT3, x, 132, 0, Z ), " & "130 (BC_4, GP(5), INPUT, x), " & "129 (BC_2, *, control, 0), " & "128 (BC_1, GP(4), OUTPUT3, x, 129, 0, Z ), " & "127 (BC_4, GP(4), INPUT, x), " & "126 (BC_2, *, control, 0), " & "125 (BC_1, GP(3), OUTPUT3, x, 126, 0, Z ), " & "124 (BC_4, GP(3), INPUT, x), " & "123 (BC_2, *, control, 0), " & "122 (BC_1, GP(2), OUTPUT3, x, 123, 0, Z ), " & "121 (BC_4, GP(2), INPUT, x), " & "120 (BC_2, *, control, 0), " & "119 (BC_1, GP(1), OUTPUT3, x, 120, 0, Z ), " & "118 (BC_4, GP(1), INPUT, x), " & "117 (BC_2, *, control, 0), " & "116 (BC_1, GP(0), OUTPUT3, x, 117, 0, Z ), " & "115 (BC_4, GP(0), INPUT, x), " & "114 (BC_2, *, control, 0), " & "113 (BC_1, LBIAS, OUTPUT3, x, 114, 0, Z ), " & "112 (BC_4, LBIAS, INPUT, x), " & "111 (BC_1, *, control, 0), " & "110 (BC_1, LPCLK, OUTPUT3, x, 111, 0, Z ), " & "109 (BC_4, LPCLK, INPUT, x), " & "108 (BC_1, *, control, 0), " & "107 (BC_1, LDD(0), OUTPUT3, x, 108, 0, Z ), " & "106 (BC_4, LDD(0), INPUT, x), " & "105 (BC_1, *, control, 0), " & "104 (BC_1, LDD(1), OUTPUT3, x, 105, 0, Z ), " & "103 (BC_4, LDD(1), INPUT, x), " & "102 (BC_1, *, control, 0), " & "101 (BC_1, LDD(2), OUTPUT3, x, 102, 0, Z ), " & "100 (BC_4, LDD(2), INPUT, x), " & "99 (BC_1, *, control, 0), " & "98 (BC_1, LDD(3), OUTPUT3, x, 99, 0, Z ), " & "97 (BC_4, LDD(3), INPUT, x), " & "96 (BC_1, *, control, 0), " & "95 (BC_1, LDD(4), OUTPUT3, x, 96, 0, Z ), " & "94 (BC_4, LDD(4), INPUT, x), " & "93 (BC_1, *, control, 0), " & "92 (BC_1, LDD(5), OUTPUT3, x, 93, 0, Z ), " & "91 (BC_4, LDD(5), INPUT, x), " & "90 (BC_1, *, control, 0), " & "89 (BC_1, LDD(6), OUTPUT3, x, 90, 0, Z ), " & "88 (BC_4, LDD(6), INPUT, x), " & "87 (BC_1, *, control, 0), " & "86 (BC_1, LDD(7), OUTPUT3, x, 87, 0, Z ), " & "85 (BC_4, LDD(7), INPUT, x), " & "84 (BC_1, *, control, 0), " & "83 (BC_1, LLCLK, OUTPUT3, x, 84, 0, Z ), " & "82 (BC_4, LLCLK, INPUT, x), " & "81 (BC_1, *, control, 0), " & "80 (BC_1, LFCLK, OUTPUT3, x, 81, 0, Z ), " & "79 (BC_4, LFCLK, INPUT, x), " & "78 (BC_1, POE, OUTPUT2, x), " & "77 (BC_1, PWE, OUTPUT2, x), " & "76 (BC_1, PIOR, OUTPUT2, x), " & "75 (BC_1, PIOW, OUTPUT2, x), " & "74 (BC_1, PSKTSEL, OUTPUT2, x), " & "73 (BC_4, IOIS16, INPUT, x), " & "72 (BC_4, PWAIT, INPUT, x), " & "71 (BC_1, PREG, OUTPUT2, x), " & "70 (BC_1, PCE2, OUTPUT2, x), " & "69 (BC_1, PCE1, OUTPUT2, x), " & "68 (BC_1, *, control, 1), " & "67 (BC_1, WE, OUTPUT3, x, 68, 1, Z ), " & "66 (BC_1, OE, OUTPUT3, x, 68, 1, Z ), " & "65 (BC_1, RAS(3), OUTPUT3, x, 68, 1, Z ), " & "64 (BC_1, RAS(2), OUTPUT3, x, 68, 1, Z ), " & "63 (BC_1, RAS(1), OUTPUT3, x, 68, 1, Z ), " & "62 (BC_1, RAS(0), OUTPUT3, x, 68, 1, Z ), " & "61 (BC_1, CAS(3), OUTPUT3, x, 68, 1, Z ), " & "60 (BC_1, CAS(2), OUTPUT3, x, 68, 1, Z ), " & "59 (BC_1, CAS(1), OUTPUT3, x, 68, 1, Z ), " & "58 (BC_1, CAS(0), OUTPUT3, x, 68, 1, Z ), " & "57 (BC_1, CS(3), OUTPUT3, x, 68, 1, Z ), " & "56 (BC_1, CS(2), OUTPUT3, x, 68, 1, Z ), " & "55 (BC_1, CS(1), OUTPUT3, x, 68, 1, Z ), " & "54 (BC_1, CS(0), OUTPUT3, x, 68, 1, Z ), " & "53 (BC_1, A(25), OUTPUT3, x, 68, 1, Z ), " & "52 (BC_1, A(24), OUTPUT3, x, 68, 1, Z ), " & "51 (BC_1, A(23), OUTPUT3, x, 68, 1, Z ), " & "50 (BC_1, A(22), OUTPUT3, x, 68, 1, Z ), " & "49 (BC_1, A(21), OUTPUT3, x, 68, 1, Z ), " & "48 (BC_1, A(20), OUTPUT3, x, 68, 1, Z ), " & "47 (BC_1, A(19), OUTPUT3, x, 68, 1, Z ), " & "46 (BC_1, A(18), OUTPUT3, x, 68, 1, Z ), " & "45 (BC_1, A(17), OUTPUT3, x, 68, 1, Z ), " & "44 (BC_1, A(16), OUTPUT3, x, 68, 1, Z ), " & "43 (BC_1, A(15), OUTPUT3, x, 68, 1, Z ), " & "42 (BC_1, A(14), OUTPUT3, x, 68, 1, Z ), " & "41 (BC_1, A(13), OUTPUT3, x, 68, 1, Z ), " & "40 (BC_1, A(12), OUTPUT3, x, 68, 1, Z ), " & "39 (BC_1, A(11), OUTPUT3, x, 68, 1, Z ), " & "38 (BC_1, A(10), OUTPUT3, x, 68, 1, Z ), " & "37 (BC_1, A(9), OUTPUT3, x, 68, 1, Z ), " & "36 (BC_1, A(8), OUTPUT3, x, 68, 1, Z ), " & "35 (BC_1, A(7), OUTPUT3, x, 68, 1, Z ), " & "34 (BC_1, A(6), OUTPUT3, x, 68, 1, Z ), " & "33 (BC_1, A(5), OUTPUT3, x, 68, 1, Z ), " & "32 (BC_1, A(4), OUTPUT3, x, 68, 1, Z ), " & "31 (BC_1, A(3), OUTPUT3, x, 68, 1, Z ), " & "30 (BC_1, A(2), OUTPUT3, x, 68, 1, Z ), " & "29 (BC_1, A(1), OUTPUT3, x, 68, 1, Z ), " & "28 (BC_1, A(0), OUTPUT3, x, 68, 1, Z ), " & "27 (BC_2, *, control, 1), " & "26 (BC_1, UDCN, OUTPUT3, x, 27, 1, Z ), " & "25 (BC_4, UDCN, INPUT, x), " & "24 (BC_4, *, INTERNAL,x), " & "23 (BC_2, *, control, 1), " & "22 (BC_1, UDCP, OUTPUT3, x, 23, 1, Z ), " & "21 (BC_4, UDCP, INPUT, x), " & "20 (BC_2, *, control, 0), " & "19 (BC_1, RXD1, OUTPUT3, x, 20, 0, Z ), " & "18 (BC_4, RXD1, INPUT, x), " & "17 (BC_2, *, control, 0), " & "16 (BC_1, TXD1, OUTPUT3, x, 17, 0, Z ), " & "15 (BC_4, TXD1, INPUT, x), " & "14 (BC_2, *, control, 0), " & "13 (BC_1, RXD2, OUTPUT3, x, 14, 0, Z ), " & "12 (BC_4, RXD2, INPUT, x), " & "11 (BC_2, *, control, 0), " & "10 (BC_1, TXD2, OUTPUT3, x, 11, 0, Z ), " & "9 (BC_4, TXD2, INPUT, x), " & "8 (BC_2, *, control, 0), " & "7 (BC_1, RXD3, OUTPUT3, x, 8, 0, Z ), " & "6 (BC_4, RXD3, INPUT, x), " & "5 (BC_2, *, control, 0), " & "4 (BC_1, TXD3, OUTPUT3, x, 5, 0, Z ), " & "3 (BC_4, TXD3, INPUT, x), " & "2 (BC_4, RESET, INPUT, x), " & "1 (BC_1, RESETO, OUTPUT2, x), " & "0 (BC_4, ROMSEL, INPUT, x) "; ------------------------------------------------------------------------------ -- scan cell port function safe cntrl disable disable -- cell type cell value state ------------------------------------------------------------------------------ attribute DESIGN_WARNING of SA1100: entity is -- (ref B.8.18) " 1.IEEE 1149.1 circuits on SA1100 are designed " & " primarily to support testing in off-line module " & " manufacturing environment. The SAMPLE/PRELOAD " & " instruction support is designed primarily for " & " supporting interconnection verification test and not " & " for at-speed samples of pin data. " & " 2.Ensure to drive BATTF and VDDF to login level 0 else the chip " & " will sleep! "; end SA1100;