-- Copyright Intel Corporation 1993 --**************************************************************************** -- Intel Corporation makes no warranty for the use of its products -- and assumes no responsibility for any errors which may appear in -- this document nor does it make a commitment to update the information -- contained herein. --**************************************************************************** -- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1990 -- compliant devices. This language is under consideration by the IEEE for -- formal inclusion within a supplement to the 1149.1-1990 standard. The -- generation of the supplement entails an extensive IEEE review and a formal -- acceptance balloting procedure which may change the resultant form of the -- language. Be aware that this process may extend well into 1993, and at -- this time the IEEE does not endorse or hold an opinion on the language. --**************************************************************************** -- -- Intel486(TM) DX2 CPU BSDL description -- C-stepping (aA Stepping SL-enhanced) -- PGA Package verified electrically -- NOTE: PQFP and SQFP have *NOT* been verified electrically! -- --------------------------------------------------------- -- Rev: 2.0 12 Aug 1993 entity Intel486_DX2_C_TM is generic(PHYSICAL_PIN_MAP : string := "PGA_17x17"); port (A20M : in bit; ABUS2 : out bit; ABUS3 : out bit; ABUS : inout bit_vector (4 to 31); -- Address bus (words) ADS : out bit; AHOLD : in bit; BE : out bit_vector(0 to 3); BLAST : out bit; BOFF : in bit; BRDY : in bit; -- BRDYC : in bit; -- chipset version only BREQ : out bit; BS8 : in bit; BS16 : in bit; CLK : in bit; DBUS : inout bit_vector(0 to 31); -- Data bus DC : out bit; DP : inout bit_vector(0 to 3); EADS : in bit; FERR : out bit; FLUSH : in bit; HLDA : out bit; HOLD : in bit; IGNNE : in bit; INTR : in bit; KEN : in bit; LOCK : out bit; MIO : out bit; NC : linkage bit_vector(1 to 7); -- No Connects base NCP : linkage bit_vector(1 to 33); -- No Connects PQFP NCS : linkage bit; -- No Connects SQFP NMI : in bit; PCD : out bit; PCHK : out bit; PLOCK : out bit; PWT : out bit; RDY : in bit; SMI : in bit; -- new SMIACT : out bit; -- new SRESET : in bit; -- new STPCLK : in bit; -- new RESET : in bit; TCK, TMS, TDI : in bit; -- Scan Port inputs TDO : out bit; -- Scan Port output UP : in bit; VCC : linkage bit_vector(1 to 24); -- VCC PGA&PQFP VCCS : linkage bit_vector(1 to 30); -- VCC SQFP VSS : linkage bit_vector(1 to 24); -- VSS PQFP VSSG : linkage bit_vector(1 to 4); -- VSS PGA VSSS : linkage bit_vector(1 to 14); -- VSS SQFP WR : out bit); use STD_1149_1_1990.all; attribute PIN_MAP of Intel486_DX2_C_TM : entity is PHYSICAL_PIN_MAP; constant PGA_17x17 : PIN_MAP_STRING := -- Define Pin Out of PGA "A20M : D15, " & "ABUS2 : Q14, " & "ABUS3 : R15, " & "ABUS : (S16, Q12, S15, Q13, R13, Q11, S13, R12," & " S7, Q10, S5, R7, Q9, Q3, R5, Q4, Q8, Q5," & " Q7, S3, Q6, R2, S2, S1, R1, P2, P3, Q1)," & "ADS : S17, " & "AHOLD : A17, " & "BE : (K15, J16, J15, F17), " & "BLAST : R16, " & "BOFF : D17, " & "BRDY : H15, " & -- "BRDYC : S4, " & -- chipset version only "NCS : S4, " & "BREQ : Q15, " & "BS8 : D16, " & "BS16 : C17, " & "CLK : C3, " & "DBUS : (P1, N2, N1, H2, M3, J2, L2, L3, F2, D1, E3, " & " C1, G3, D2, K3, F3, J3, D3, C2, B1, A1, B2, " & " A2, A4, A6, B6, C7, C6, C8, A8, C9, B8)," & "DC : M15, " & "DP : (N3, F1, H3, A5), " & "EADS : B17, " & "FERR : C14, " & "FLUSH : C15, " & "HLDA : P15, " & "HOLD : E15, " & "IGNNE : A15, " & "INTR : A16, " & "KEN : F15, " & "LOCK : N15, " & "MIO : N16, " & "NC : (R17, C13, B12, B13, A10, A12, A13)," & "NMI : B15, " & "PCD : J17, " & "PCHK : Q17, " & "PLOCK : Q16, " & "PWT : L15, " & "SMI : B10, " & "SMIACT : C12, " & "SRESET : C10, " & "STPCLK : G15, " & "RDY : F16, " & "RESET : C16, " & "TCK : A3, " & "TDI : A14, " & "TDO : B16, " & "TMS : B14, " & "UP : C11, " & "VCC : (R8, R9, R10, R11, R14, P16, M2, M16, L16, K2, K16, " & " J1, H16, G2, G16, E2, E16, C4, C5, B7, B9, B11, " & " R3, R6)," & "VSS : (S6, S8, S9, S10, S11, S12, S14, R4, Q2, P17, M1, " & " M17, L1, L17, K1, K17, H1, H17, G1, G17, E1, E17, " & " B3, B4)," & "VSSG : (B5, A7, A9, A11), " & "WR : N17 "; constant PQFP_196 : PIN_MAP_STRING := -- Define Pin Out of Plastic Quad FP "A20M : 104, " & "ABUS2 : 146, " & "ABUS3 : 150, " & "ABUS : (152, 154, 158, 159, 161, 163, 165, 172," & " 174, 176, 178, 180, 181, 183, 189, 191, 193, 2," & " 3, 4, 5, 7, 8, 9, 10, 12, 13, 14)," & "ADS : 145, " & "AHOLD : 129, " & "BE : (117, 116, 115, 113), " & "BLAST : 144, " & "BOFF : 137, " & "BRDY : 138, " & "BREQ : 118, " & "BS8 : 135, " & "BS16 : 136, " & "CLK : 123, " & "DBUS : (17, 18, 20, 23, 25, 26, 27, 29, 31, 32, 35, " & " 37, 38, 39, 41, 42, 44, 45, 46, 47, 48, 51, " & " 53, 55, 59, 61, 63, 65, 67, 69, 71, 74)," & "DC : 110, " & "DP : (16, 30, 43, 57), " & "EADS : 105, " & "FERR : 81, " & "FLUSH : 102, " & "HLDA : 122, " & "HOLD : 130, " & "IGNNE : 77, " & "INTR : 101, " & "KEN : 132, " & "LOCK : 142, " & "MIO : 111, " & "NC : (15, 34, 52, 56, 60, 64, 68), " & "NCP : (72, 73, 76, 78, 79, " & " 82, 83, 87, 88, 89, 90, 91, 97, 124, 127, 134, " & " 140, 149, 151, 153, 155, 157, 160, 162, 166, 169, " & " 171, 173, 186, 188, 190, 192, 195)," & "NMI : 100, " & "PCD : 106, " & "PCHK : 139, " & "PLOCK : 143, " & "PWT : 108, " & "SMI : 85, " & "SMIACT : 92, " & "SRESET : 94, " & "STPCLK : 75, " & "RDY : 133, " & "RESET : 103, " & "TCK : 128, " & "TDI : 185, " & "TDO : 80, " & "TMS : 187, " & "UP : 156, " & "VCC : ( 6, 19, 24, 28, 36, 49, 54, 62, 70, 84, 93, " & " 98, 107, 112, 119, 125, 131, 147, 164, 170, 175, 179, " & " 184, 196)," & "VSS : ( 1, 11, 21, 22, 33, 40, 50, 58, 66, 86, 95, 96, 99, " & " 109, 114, 121, 126, 141, 148, 167, 168, 177, 182, 194), " & "WR : 120 "; constant SQFP_208 : PIN_MAP_STRING := -- Define Pin Out of SQFP package "A20M : 47, " & "ABUS2 : 202, " & "ABUS3 : 197, " & "ABUS : (196, 195, 193, 192, 190, 187, 186, 182," & " 180, 178, 177, 174, 173, 171, 166, 165, 164, 161," & " 160, 159, 158, 154, 153, 152, 151, 149, 148, 147)," & "ADS : 203, " & "AHOLD : 17, " & "BE : (31, 32, 33, 34), " & "BLAST : 204, " & "BOFF : 6, " & "BRDY : 5, " & "BREQ : 30, " & "BS8 : 8, " & "BS16 : 7, " & "CLK : 24, " & "DBUS : (144, 143, 142, 141, 140, 130, 129, 126, 124, 123, 119, " & " 118, 117, 116, 113, 112, 108, 103, 101, 100, 99, 93, " & " 92, 91, 87, 85, 84, 83, 79, 78, 75, 74)," & "DC : 39, " & "DP : (145, 125, 109, 90), " & "EADS : 46, " & "FERR : 66, " & "FLUSH : 49, " & "HLDA : 26, " & "HOLD : 16, " & "IGNNE : 72, " & "INTR : 50, " & "KEN : 13, " & "LOCK : 207, " & "MIO : 37, " & "NC : (11, 63, 64, 67, 70, 71, 96)," & "NCS : 127," & "NMI : 51, " & "PCD : 41, " & "PCHK : 4, " & "PLOCK : 206, " & "PWT : 40, " & "SMI : 65, " & "SMIACT : 59, " & "SRESET : 58, " & "STPCLK : 73, " & "RDY : 12, " & "RESET : 48, " & "TCK : 18, " & "TDI : 168, " & "TDO : 68, " & "TMS : 167, " & "UP : 194, " & "VCC : ( 2, 3, 9, 14, 19, 20, 22, 23, 25, 29, 35, " & " 38, 42, 44, 45, 54, 56, 60, 62, 69, 77, 80, 82, 86), " & "VCCS : (89, 95, 98, 102, 106, 111, 114, 121, 128, 131, 133, " & " 134, 136, 137, 139,150, 155, 162, 163, 169, 172, 176, " & " 179, 183, 185, 188, 191, 198, 200, 205)," & "VSS : (1, 10, 15, 21, 28, 36, 43, 52, 53, 55, 57, 61, 76, " & " 81, 88, 94, 97, 104, 105, 107, 110, 115, 120, 122), " & "VSSS : (132, 135, 138, 146, 156, 157, 170, 175, 181, 184, 189, 199, " & " 201, 208), " & "WR : 27 "; attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Clock of TCK : signal is (25.0e6, BOTH); attribute Instruction_Length of Intel486_DX2_C_TM: entity is 4; attribute Instruction_Opcode of Intel486_DX2_C_TM: entity is "BYPASS (1111)," & "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "RUNBIST (1000)," & "PRIVATE (0011,0100,0101,0110,0111,1001,1010,1011,1100,1101,1110)"; attribute Instruction_Capture of Intel486_DX2_C_TM: entity is "0001"; -- there is no Instruction_Disable attribute for Intel486_DX2_C_TM attribute Instruction_Private of Intel486_DX2_C_TM: entity is "private"; attribute Instruction_Usage of Intel486_DX2_C_TM: entity is "RUNBIST (registers BIST; " & "result 0;" & "clock CLK in Run_Test_Idle;"& "length 1200000)"; attribute Idcode_Register of Intel486_DX2_C_TM: entity is "0001" & -- version "0" & -- 0=5v 1=3v part "000001010000101" & -- DX2-S production part ID "00000001001" & -- manufacturers identity =Intel "1"; -- required by the standard -- attribute Register_Access of Intel486_DX2_C_TM: entity is "BIST[1] (RUNBIST)" ; --{*******************************************************************} --{ The first cell is closest to TDO } --{*******************************************************************} attribute Boundary_Length of Intel486_DX2_C_TM: entity is 109; attribute Boundary_Cells of Intel486_DX2_C_TM: entity is "BC_2, BC_1, BC_6"; attribute Boundary_Register of Intel486_DX2_C_TM: entity is "0 (BC_2, ABUS2, output3, X, 107, 1, Z)," & "1 (BC_2, ABUS3, output3, X, 107, 1, Z)," & "2 (BC_6, ABUS(4), bidir, X, 107, 1, Z)," & "3 (BC_6, ABUS(5), bidir, X, 107, 1, Z)," & "4 (BC_1, UP , input, X)," & "5 (BC_6, ABUS(6), bidir, X, 107, 1, Z)," & "6 (BC_6, ABUS(7), bidir, X, 107, 1, Z)," & "7 (BC_6, ABUS(8), bidir, X, 107, 1, Z)," & "8 (BC_6, ABUS(9), bidir, X, 107, 1, Z)," & "9 (BC_6, ABUS(10), bidir, X, 107, 1, Z)," & "10 (BC_6, ABUS(11), bidir, X, 107, 1, Z)," & "11 (BC_6, ABUS(12), bidir, X, 107, 1, Z)," & "12 (BC_6, ABUS(13), bidir, X, 107, 1, Z)," & "13 (BC_6, ABUS(14), bidir, X, 107, 1, Z)," & "14 (BC_6, ABUS(15), bidir, X, 107, 1, Z)," & "15 (BC_6, ABUS(16), bidir, X, 107, 1, Z)," & "16 (BC_6, ABUS(17), bidir, X, 107, 1, Z)," & "17 (BC_6, ABUS(18), bidir, X, 107, 1, Z)," & "18 (BC_6, ABUS(19), bidir, X, 107, 1, Z)," & "19 (BC_6, ABUS(20), bidir, X, 107, 1, Z)," & "20 (BC_6, ABUS(21), bidir, X, 107, 1, Z)," & "21 (BC_6, ABUS(22), bidir, X, 107, 1, Z)," & "22 (BC_6, ABUS(23), bidir, X, 107, 1, Z)," & "23 (BC_6, ABUS(24), bidir, X, 107, 1, Z)," & "24 (BC_6, ABUS(25), bidir, X, 107, 1, Z)," & "25 (BC_6, ABUS(26), bidir, X, 107, 1, Z)," & "26 (BC_6, ABUS(27), bidir, X, 107, 1, Z)," & "27 (BC_6, ABUS(28), bidir, X, 107, 1, Z)," & "28 (BC_6, ABUS(29), bidir, X, 107, 1, Z)," & "29 (BC_6, ABUS(30), bidir, X, 107, 1, Z)," & "30 (BC_6, ABUS(31), bidir, X, 107, 1, Z)," & "31 (BC_6, DP(0), bidir, X, 108, 1, Z)," & "32 (BC_6, DBUS(0), bidir, X, 108, 1, Z)," & "33 (BC_6, DBUS(1), bidir, X, 108, 1, Z)," & "34 (BC_6, DBUS(2), bidir, X, 108, 1, Z)," & "35 (BC_6, DBUS(3), bidir, X, 108, 1, Z)," & "36 (BC_6, DBUS(4), bidir, X, 108, 1, Z)," & "37 (BC_6, DBUS(5), bidir, X, 108, 1, Z)," & "38 (BC_6, DBUS(6), bidir, X, 108, 1, Z)," & "39 (BC_6, DBUS(7), bidir, X, 108, 1, Z)," & "40 (BC_6, DP(1), bidir, X, 108, 1, Z)," & "41 (BC_6, DBUS(8), bidir, X, 108, 1, Z)," & "42 (BC_6, DBUS(9), bidir, X, 108, 1, Z)," & "43 (BC_6, DBUS(10), bidir, X, 108, 1, Z)," & "44 (BC_6, DBUS(11), bidir, X, 108, 1, Z)," & "45 (BC_6, DBUS(12), bidir, X, 108, 1, Z)," & "46 (BC_6, DBUS(13), bidir, X, 108, 1, Z)," & "47 (BC_6, DBUS(14), bidir, X, 108, 1, Z)," & "48 (BC_6, DBUS(15), bidir, X, 108, 1, Z)," & "49 (BC_6, DP(2), bidir, X, 108, 1, Z)," & "50 (BC_6, DBUS(16), bidir, X, 108, 1, Z)," & "51 (BC_6, DBUS(17), bidir, X, 108, 1, Z)," & "52 (BC_6, DBUS(18), bidir, X, 108, 1, Z)," & "53 (BC_6, DBUS(19), bidir, X, 108, 1, Z)," & "54 (BC_6, DBUS(20), bidir, X, 108, 1, Z)," & "55 (BC_6, DBUS(21), bidir, X, 108, 1, Z)," & "56 (BC_6, DBUS(22), bidir, X, 108, 1, Z)," & "57 (BC_6, DBUS(23), bidir, X, 108, 1, Z)," & "58 (BC_6, DP(3), bidir, X, 108, 1, Z)," & "59 (BC_6, DBUS(24), bidir, X, 108, 1, Z)," & "60 (BC_6, DBUS(25), bidir, X, 108, 1, Z)," & "61 (BC_6, DBUS(26), bidir, X, 108, 1, Z)," & "62 (BC_6, DBUS(27), bidir, X, 108, 1, Z)," & "63 (BC_6, DBUS(28), bidir, X, 108, 1, Z)," & "64 (BC_6, DBUS(29), bidir, X, 108, 1, Z)," & "65 (BC_6, DBUS(30), bidir, X, 108, 1, Z)," & "66 (BC_6, DBUS(31), bidir, X, 108, 1, Z)," & "67 (BC_1, STPCLK, input, X)," & "68 (BC_1, IGNNE, input, X)," & "69 (BC_2, FERR, output3, X, 105, 1, Z)," & "70 (BC_1, SMI , input, X)," & "71 (BC_2, SMIACT , output3, X, 105, 1, Z)," & "72 (BC_1, SRESET , input, X)," & "73 (BC_1, NMI, input, X)," & "74 (BC_1, INTR, input, X)," & "75 (BC_1, FLUSH, input, X)," & "76 (BC_1, RESET, input, X)," & "77 (BC_1, A20M, input, X)," & "78 (BC_1, EADS, input, X)," & "79 (BC_2, PCD, output3, X, 106, 1, Z)," & "80 (BC_2, PWT, output3, X, 106, 1, Z)," & "81 (BC_2, DC, output3, X, 106, 1, Z)," & "82 (BC_2, MIO, output3, X, 106, 1, Z)," & "83 (BC_2, BE(3), output3, X, 106, 1, Z)," & "84 (BC_2, BE(2), output3, X, 106, 1, Z)," & "85 (BC_2, BE(1), output3, X, 106, 1, Z)," & "86 (BC_2, BE(0), output3, X, 106, 1, Z)," & "87 (BC_2, BREQ, output3, X, 105, 1, Z)," & "88 (BC_2, WR, output3, X, 106, 1, Z)," & "89 (BC_2, HLDA, output3, X, 105, 1, Z)," & "90 (BC_1, CLK, input, X)," & -- "91 (BC_1, BRDYC , input, X)," & -- chipset only "91 (BC_1, * , internal, 1)," & "92 (BC_1, AHOLD, input, X)," & "93 (BC_1, HOLD, input, X)," & "94 (BC_1, KEN, input, X)," & "95 (BC_1, RDY, input, X)," & "96 (BC_1, BS8, input, X)," & "97 (BC_1, BS16, input, X)," & "98 (BC_1, BOFF, input, X)," & "99 (BC_1, BRDY, input, X)," & "100 (BC_2, PCHK, output3, X, 105, 1, Z)," & "101 (BC_2, LOCK, output3, X, 106, 1, Z)," & "102 (BC_2, PLOCK, output3, X, 106, 1, Z)," & "103 (BC_2, BLAST, output3, X, 106, 1, Z)," & "104 (BC_2, ADS, output3, X, 106, 1, Z)," & "105 (BC_2, *, control, 1)," & -- DISMISC "106 (BC_2, *, control, 1)," & -- DISBUS "107 (BC_2, *, control, 1)," & -- DISABUS "108 (BC_2, *, control, 1)"; -- DISWR end Intel486_DX2_C_TM;