-- Boundary Scan Description Language (BSDL) for ZARLINK MT90220 IC -- File name : MT90220.bsd -- DEVICE : ZARLINK MT90220 Octal IMA/UNI PHY Device -- BSDL revision : STD_1149_1_1990 -- Date created : 97/Nov/12 -- Last updated : 99/Oct/2 SM Corrected errors on lines 250 & 325 -- Documentation : MT90220 Data Sheet and Programmers' Manual. -- Packages : 208-pin MQFP -- -- IMPORTANT NOTICE -- -- ZARLINK and MT90220 are trademarks of ZARLINK Semiconductor. ZARLINK products -- marketed under trademarks are protected under numerous US and foreign -- patents and pending applications, maskwork rights, and copyrights. -- -- ZARLINK reserves the right to make changes to any products and services -- at any time without notice. ZARLINK assumes no responsibility or -- liability arising out of the application or use of any information, -- product, or service described herein except as expressly agreed to -- in writing by ZARLINK Semiconductor. ZARLINK customers are advised to obtain -- the latest version of device specifications before relying on any -- published information and before placing orders for products or services. entity mt90220 is generic (PHYSICAL_PIN_MAP : string := "LSI_PACKAGE"); port ( TRST : in bit ; TDO : out bit ; up_irq : out bit ; up_a_0 : in bit ; up_a_1 : in bit ; up_a_2 : in bit ; up_a_3 : in bit ; up_a_4 : in bit ; up_a_5 : in bit ; up_a_6 : in bit ; up_a_7 : in bit ; up_a_8 : in bit ; up_a_9 : in bit ; up_a_10 : in bit ; reset : in bit ; up_d_0 : inout bit ; up_d_1 : inout bit ; up_d_2 : inout bit ; up_d_3 : inout bit ; up_d_4 : inout bit ; up_d_5 : inout bit ; up_d_6 : inout bit ; up_d_7 : inout bit ; up_rw : in bit ; up_oe : in bit ; up_cs : in bit ; TxAddr_0 : in bit ; TxAddr_1 : in bit ; TxAddr_2 : in bit ; TxAddr_3 : in bit ; TxAddr_4 : in bit ; TxClk : in bit ; TxEnb : in bit ; TxData_0 : in bit ; TxData_1 : in bit ; TxData_2 : in bit ; TxData_3 : in bit ; TxData_4 : in bit ; TxData_5 : in bit ; TxData_6 : in bit ; TxData_7 : in bit ; TxSOC : in bit ; TxClav : out bit ; RxEnb : in bit ; RxClk : in bit ; RxAddr_0 : in bit ; RxAddr_1 : in bit ; RxAddr_2 : in bit ; RxAddr_3 : in bit ; RxAddr_4 : in bit ; RxData_0 : out bit ; RxData_1 : out bit ; RxData_2 : out bit ; RxData_3 : out bit ; RxData_4 : out bit ; RxData_5 : out bit ; RxData_6 : out bit ; RxData_7 : out bit ; RxClav : out bit ; RxSOC : out bit ; sr_cs_0 : buffer bit ; sr_cs_1 : buffer bit ; sr_d_0 : inout bit ; sr_d_1 : inout bit ; sr_d_2 : inout bit ; sr_d_3 : inout bit ; sr_d_4 : inout bit ; sr_d_5 : inout bit ; sr_d_6 : inout bit ; sr_d_7 : inout bit ; sr_we : buffer bit ; sr_a_0 : buffer bit ; sr_a_1 : buffer bit ; sr_a_2 : buffer bit ; sr_a_3 : buffer bit ; sr_a_4 : buffer bit ; sr_a_5 : buffer bit ; sr_a_6 : buffer bit ; sr_a_7 : buffer bit ; sr_a_8 : buffer bit ; sr_a_9 : buffer bit ; sr_a_10 : buffer bit ; sr_a_11 : buffer bit ; sr_a_12 : buffer bit ; sr_a_13 : buffer bit ; sr_a_14 : buffer bit ; sr_a_15 : buffer bit ; sr_a_16 : buffer bit ; sr_a_17 : buffer bit ; sr_a_18 : buffer bit ; REFCK_0 : in bit ; REFCK_1 : in bit ; REFCK_2 : in bit ; REFCK_3 : in bit ; PLLREF_0 : linkage bit ; -- not in chain PLLREF_1 : buffer bit ; Test3 : linkage bit ; -- not in chain Test4 : linkage bit ; -- not in chain DSTi_0 : in bit ; RXSYNCi_0 : in bit ; RXCKi_0 : in bit ; RXCKi_1 : in bit ; DSTi_1 : in bit ; RXSYNCi_1 : in bit ; DSTi_2 : in bit ; RXSYNCi_2 : in bit ; RXCKi_2 : in bit ; RXCKi_3 : in bit ; DSTi_3 : in bit ; RXSYNCi_3 : in bit ; DSTi_4 : in bit ; RXSYNCi_4 : in bit ; RXCKi_4 : in bit ; RXCKi_5 : in bit ; DSTi_5 : in bit ; RXSYNCi_5 : in bit ; RXSYNCi_6 : in bit ; DSTi_6 : in bit ; RXCKi_6 : in bit ; RXCKi_7 : in bit ; DSTi_7 : in bit ; RXSYNCi_7 : in bit ; DSTo_0 : out bit ; TXSYNCio_0 : inout bit ; TXCKio_0 : inout bit ; TXCKio_1 : inout bit ; DSTo_1 : out bit ; TXSYNCio_1 : inout bit ; DSTo_2 : out bit ; TXSYNCio_2 : inout bit ; TXCKio_2 : inout bit ; TXCKio_3 : inout bit ; DSTo_3 : out bit ; TXSYNCio_3 : inout bit ; DSTo_4 : out bit ; TXSYNCio_4 : inout bit ; TXCKio_4 : inout bit ; TXCKio_5 : inout bit ; DSTo_5 : out bit ; TXSYNCio_5 : inout bit ; DSTo_6 : out bit ; TXSYNCio_6 : inout bit ; TXCKio_6 : inout bit ; TXCKio_7 : inout bit ; DSTo_7 : out bit ; TXSYNCio_7 : inout bit ; Test1 : in bit ; Test2 : in bit ; vdd : linkage bit_vector (0 to 24); Clk : in bit ; vss : linkage bit_vector (0 to 30); TCK : in bit ; TMS : in bit ; TDI : in bit ) ; use STD_1149_1_1990.all; attribute PIN_MAP of mt90220 : entity is PHYSICAL_PIN_MAP ; constant LSI_PACKAGE : PIN_MAP_STRING := "TDI : 70, TMS : 71, TCK : 72, " & "Test1 : 76, Test2 : 77, TXSYNCio_7 : 80, " & "DSTo_7 : 81, TXCKio_7 : 83, TXCKio_6 : 85, " & "TXSYNCio_6 : 87, DSTo_6 : 88, TXSYNCio_5 : 89, " & "DSTo_5 : 90, TXCKio_5 : 92, TXCKio_4 : 94, " & "TXSYNCio_4 : 96, DSTo_4 : 97, TXSYNCio_3 : 98, " & "DSTo_3 : 99, TXCKio_3 : 101, TXCKio_2 : 103, " & "TXSYNCio_2 : 106, DSTo_2 : 107, TXSYNCio_1 : 108, " & "DSTo_1 : 109, TXCKio_1 : 111, TXCKio_0 : 113, " & "TXSYNCio_0 : 115, DSTo_0 : 116, RXSYNCi_7 : 117, " & "DSTi_7 : 118, RXCKi_7 : 120, RXCKi_6 : 122, " & "DSTi_6 : 124, RXSYNCi_6 : 125, RXSYNCi_5 : 126, " & "DSTi_5 : 127, RXCKi_5 : 129, RXCKi_4 : 131, " & "RXSYNCi_4 : 133, DSTi_4 : 134, RXSYNCi_3 : 135, " & "DSTi_3 : 136, RXCKi_3 : 138, RXCKi_2 : 140, " & "RXSYNCi_2 : 142, DSTi_2 : 143, RXSYNCi_1 : 144, " & "DSTi_1 : 145, RXCKi_1 : 146, RXCKi_0 : 148, " & "RXSYNCi_0 : 150, DSTi_0 : 151, PLLREF_1 : 154, " & "REFCK_3 : 158, REFCK_2 : 159, REFCK_1 : 160, " & "REFCK_0 : 161, sr_a_18 : 162, sr_a_17 : 163, " & "sr_a_16 : 164, sr_a_15 : 165, sr_a_14 : 166, " & "sr_a_13 : 169, sr_a_12 : 170, sr_a_11 : 171, " & "sr_a_10 : 172, sr_a_9 : 175, sr_a_8 : 176, " & "sr_a_7 : 177, sr_a_6 : 178, sr_a_5 : 179, " & "sr_a_4 : 182, sr_a_3 : 183, sr_a_2 : 184, " & "sr_a_1 : 185, sr_a_0 : 186, sr_we : 187, " & "sr_d_7 : 188, sr_d_6 : 189, sr_d_5 : 190, " & "sr_d_4 : 191, sr_d_3 : 192, sr_d_2 : 195, " & "sr_d_1 : 196, sr_d_0 : 197, sr_cs_1 : 198, " & "sr_cs_0 : 199, RxSOC : 202, RxClav : 203, " & "RxData_7 : 205, RxData_6 : 206, RxData_5 : 207, " & "RxData_4 : 2, RxData_3 : 3, RxData_2 : 4, " & "RxData_1 : 5, RxData_0 : 6, RxAddr_4 : 9, " & "RxAddr_3 : 10, RxAddr_2 : 11, RxAddr_1 : 12, " & "RxAddr_0 : 13, RxClk : 15, RxEnb : 17, " & "TxClav : 20, TxSOC : 21, TxData_7 : 22, " & "TxData_6 : 23, TxData_5 : 24, TxData_4 : 25, " & "TxData_3 : 26, TxData_2 : 27, TxData_1 : 28, " & "TxData_0 : 29, TxEnb : 30, TxClk : 32, " & "TxAddr_4 : 34, TxAddr_3 : 35, TxAddr_2 : 36, " & "TxAddr_1 : 37, TxAddr_0 : 38, up_cs : 39, " & "up_oe : 40, up_rw : 41, up_d_7 : 44, " & "up_d_6 : 45, up_d_5 : 46, up_d_4 : 47, " & "up_d_3 : 48, up_d_2 : 49, up_d_1 : 50, " & "up_d_0 : 51, reset : 54, up_a_10 : 55, " & "up_a_9 : 56, up_a_8 : 57, up_a_7 : 58, " & "up_a_6 : 59, up_a_5 : 60, up_a_4 : 61, " & "up_a_3 : 62, up_a_2 : 63, up_a_1 : 64, " & "up_a_0 : 65, up_irq : 67, TDO : 68, " & "TRST : 69, Clk : 74, " & -- Pins not scanned by boundary-scan " PLLREF_0 : 155, Test4 : 152, Test3 : 153, " & "vss : ( 1, 8, 16, 19, 33, 42, 52, 53, 73, " & "79, 84, 91, 95, 100, 104, 105, 112, 119, 123, " & "132, 137, 141, 147, 156, 157, 168, 174, 181, 194, " & "200, 208 ), " & "vdd : ( 7, 14, 18, 31, 43, 66, 75, 78, 82, " & "86, 93, 102, 110, 114, 121, 128, 130, 139, 149, " & "167, 173, 180, 193, 201, 204 )" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_RESET of TRST : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is ( 1.200000e+07, BOTH ); attribute INSTRUCTION_LENGTH of mt90220 : entity is 2; attribute INSTRUCTION_OPCODE of mt90220 : entity is "IDCODE (10)," & "SAMPLE (01)," & "BYPASS (11)," & "EXTEST (00)" ; attribute INSTRUCTION_CAPTURE of mt90220 : entity is "01"; attribute IDCODE_REGISTER of mt90220 : entity is -- hex 1 0220 14B "0001" & -- 4-bit version (version 1) "0000001000100000" & -- 16-bit part number (hex 0220) "00010100101" & -- 11-bit manufacturer (Zarlink) "1" ; -- mandatory LSB attribute REGISTER_ACCESS of mt90220 : entity is "IDCODE (IDCODE)," & "BOUNDARY (SAMPLE, EXTEST)," & "BYPASS (BYPASS)" ; attribute BOUNDARY_CELLS of mt90220 : entity is "BC_2, BC_4, BC_1"; attribute BOUNDARY_LENGTH of mt90220 : entity is 206; attribute BOUNDARY_REGISTER of mt90220 : entity is -- num cell port function safe [ccell disval rslt] "0 ( BC_1, *, controlr, 1 ) ," & "1 ( BC_1, *, controlr, 1 ) ," & "2 ( BC_1, *, controlr, 1 ) ," & "3 ( BC_1, *, controlr, 1 ) ," & "4 ( BC_1, *, controlr, 1 ) ," & "5 ( BC_1, *, controlr, 1 ) ," & "6 ( BC_1, *, controlr, 1 ) ," & "7 ( BC_1, *, controlr, 1 ) ," & "8 ( BC_1, *, controlr, 1 ) ," & "9 ( BC_1, *, controlr, 1 ) ," & "10 ( BC_1, *, controlr, 1 ) ," & "11 ( BC_1, *, controlr, 1 ) ," & "12 ( BC_1, *, controlr, 1 ) ," & "13 ( BC_1, *, controlr, 1 ) ," & "14 ( BC_1, *, controlr, 1 ) ," & "15 ( BC_1, *, controlr, 1 ) ," & "16 ( BC_1, *, controlr, 1 ) ," & "17 ( BC_1, *, controlr, 1 ) ," & "18 ( BC_1, *, controlr, 1 ) ," & "19 ( BC_1, *, controlr, 1 ) ," & "20 ( BC_1, *, controlr, 1 ) ," & "21 ( BC_1, *, controlr, 1 ) ," & "22 ( BC_1, *, controlr, 1 ) ," & "23 ( BC_1, *, controlr, 1 ) ," & "24 ( BC_1, *, controlr, 1 ) ," & "25 ( BC_1, *, controlr, 1 ) ," & "26 ( BC_1, *, controlr, 1 ) ," & "27 ( BC_1, *, controlr, 1 ) ," & "28 ( BC_1, *, controlr, 1 ) ," & "29 ( BC_1, *, controlr, 1 ) ," & "30 ( BC_1, up_irq, output2, 1 , 30, 1, weak1)," & "31 ( BC_4, up_a_0, clock, X ) ," & "32 ( BC_4, up_a_1, clock, X ) ," & "33 ( BC_4, up_a_2, clock, X ) ," & "34 ( BC_4, up_a_3, clock, X ) ," & "35 ( BC_4, up_a_4, clock, X ) ," & "36 ( BC_4, up_a_5, clock, X ) ," & "37 ( BC_4, up_a_6, clock, X ) ," & "38 ( BC_4, up_a_7, clock, X ) ," & "39 ( BC_4, up_a_8, clock, X ) ," & "40 ( BC_4, up_a_9, clock, X ) ," & "41 ( BC_4, up_a_10, clock, X ) ," & "42 ( BC_4, reset, clock, 1 ) ," & "43 ( BC_1, up_d_0, output3, X , 28, 1, Z)," & "44 ( BC_2, up_d_0, input, X ) ," & "45 ( BC_1, up_d_1, output3, X , 28, 1, Z)," & "46 ( BC_2, up_d_1, input, X ) ," & "47 ( BC_1, up_d_2, output3, X , 28, 1, Z)," & "48 ( BC_2, up_d_2, input, X ) ," & "49 ( BC_1, up_d_3, output3, X , 28, 1, Z)," & "50 ( BC_2, up_d_3, input, X ) ," & "51 ( BC_1, up_d_4, output3, X , 28, 1, Z)," & "52 ( BC_2, up_d_4, input, X ) ," & "53 ( BC_1, up_d_5, output3, X , 28, 1, Z)," & "54 ( BC_2, up_d_5, input, X ) ," & "55 ( BC_1, up_d_6, output3, X , 28, 1, Z)," & "56 ( BC_2, up_d_6, input, X ) ," & "57 ( BC_1, up_d_7, output3, X , 28, 1, Z)," & "58 ( BC_2, up_d_7, input, X ) ," & "59 ( BC_4, up_rw, clock, X ) ," & "60 ( BC_4, up_oe, clock, X ) ," & "61 ( BC_4, up_cs, clock, X ) ," & "62 ( BC_4, TxAddr_0, clock, X ) ," & "63 ( BC_4, TxAddr_1, clock, X ) ," & "64 ( BC_4, TxAddr_2, clock, X ) ," & "65 ( BC_4, TxAddr_3, clock, X ) ," & "66 ( BC_4, TxAddr_4, clock, X ) ," & "67 ( BC_4, TxClk, clock, X ) ," & "68 ( BC_4, TxEnb, clock, X ) ," & "69 ( BC_4, TxData_0, clock, X ) ," & "70 ( BC_4, TxData_1, clock, X ) ," & "71 ( BC_4, TxData_2, clock, X ) ," & "72 ( BC_4, TxData_3, clock, X ) ," & "73 ( BC_4, TxData_4, clock, X ) ," & "74 ( BC_4, TxData_5, clock, X ) ," & "75 ( BC_4, TxData_6, clock, X ) ," & "76 ( BC_4, TxData_7, clock, X ) ," & "77 ( BC_4, TxSOC, clock, X ) ," & "78 ( BC_1, TxClav, output3, X , 29, 1, Z)," & "79 ( BC_4, RxEnb, clock, X ) ," & "80 ( BC_4, RxClk, clock, X ) ," & "81 ( BC_4, RxAddr_0, clock, X ) ," & "82 ( BC_4, RxAddr_1, clock, X ) ," & "83 ( BC_4, RxAddr_2, clock, X ) ," & "84 ( BC_4, RxAddr_3, clock, X ) ," & "85 ( BC_4, RxAddr_4, clock, X ) ," & "86 ( BC_1, RxData_0, output3, X , 1, 1, Z)," & "87 ( BC_1, RxData_1, output3, X , 1, 1, Z)," & "88 ( BC_1, RxData_2, output3, X , 1, 1, Z)," & "89 ( BC_1, RxData_3, output3, X , 1, 1, Z)," & "90 ( BC_1, RxData_4, output3, X , 1, 1, Z)," & "91 ( BC_1, RxData_5, output3, X , 1, 1, Z)," & "92 ( BC_1, RxData_6, output3, X , 1, 1, Z)," & "93 ( BC_1, RxData_7, output3, X , 1, 1, Z)," & "94 ( BC_1, RxClav, output3, X , 0, 1, Z)," & "95 ( BC_1, RxSOC, output3, X , 2, 1, Z)," & "96 ( BC_1, sr_cs_0, output2, X ) ," & "97 ( BC_1, sr_cs_1, output2, X ) ," & "98 ( BC_1, sr_d_0, output3, X , 27, 1, Z)," & "99 ( BC_2, sr_d_0, input, X ) ," & "100 ( BC_1, sr_d_1, output3, X , 27, 1, Z)," & "101 ( BC_2, sr_d_1, input, X ) ," & "102 ( BC_1, sr_d_2, output3, X , 27, 1, Z)," & "103 ( BC_2, sr_d_2, input, X ) ," & "104 ( BC_1, sr_d_3, output3, X , 27, 1, Z)," & "105 ( BC_2, sr_d_3, input, X ) ," & "106 ( BC_1, sr_d_4, output3, X , 27, 1, Z)," & "107 ( BC_2, sr_d_4, input, X ) ," & "108 ( BC_1, sr_d_5, output3, X , 27, 1, Z)," & "109 ( BC_2, sr_d_5, input, X ) ," & "110 ( BC_1, sr_d_6, output3, X , 27, 1, Z)," & "111 ( BC_2, sr_d_6, input, X ) ," & "112 ( BC_1, sr_d_7, output3, X , 27, 1, Z)," & "113 ( BC_2, sr_d_7, input, X ) ," & "114 ( BC_1, sr_we, output2, X ) ," & "115 ( BC_1, sr_a_0, output2, X ) ," & "116 ( BC_1, sr_a_1, output2, X ) ," & "117 ( BC_1, sr_a_2, output2, X ) ," & "118 ( BC_1, sr_a_3, output2, X ) ," & "119 ( BC_1, sr_a_4, output2, X ) ," & "120 ( BC_1, sr_a_5, output2, X ) ," & "121 ( BC_1, sr_a_6, output2, X ) ," & "122 ( BC_1, sr_a_7, output2, X ) ," & "123 ( BC_1, sr_a_8, output2, X ) ," & "124 ( BC_1, sr_a_9, output2, X ) ," & "125 ( BC_1, sr_a_10, output2, X ) ," & "126 ( BC_1, sr_a_11, output2, X ) ," & "127 ( BC_1, sr_a_12, output2, X ) ," & "128 ( BC_1, sr_a_13, output2, X ) ," & "129 ( BC_1, sr_a_14, output2, X ) ," & "130 ( BC_1, sr_a_15, output2, X ) ," & "131 ( BC_1, sr_a_16, output2, X ) ," & "132 ( BC_1, sr_a_17, output2, X ) ," & "133 ( BC_1, sr_a_18, output2, X ) ," & "134 ( BC_4, REFCK_0, clock, X ) ," & "135 ( BC_4, REFCK_1, clock, X ) ," & "136 ( BC_4, REFCK_2, clock, X ) ," & "137 ( BC_4, REFCK_3, clock, X ) ," & "138 ( BC_1, PLLREF_1, output2, X ) ," & "139 ( BC_4, DSTi_0, clock, X ) ," & "140 ( BC_4, RXSYNCi_0, clock, X ) ," & "141 ( BC_4, RXCKi_0, clock, X ) ," & "142 ( BC_4, RXCKi_1, clock, X ) ," & "143 ( BC_4, DSTi_1, clock, X ) ," & "144 ( BC_4, RXSYNCi_1, clock, X ) ," & "145 ( BC_4, DSTi_2, clock, X ) ," & "146 ( BC_4, RXSYNCi_2, clock, X ) ," & "147 ( BC_4, RXCKi_2, clock, X ) ," & "148 ( BC_4, RXCKi_3, clock, X ) ," & "149 ( BC_4, DSTi_3, clock, X ) ," & "150 ( BC_4, RXSYNCi_3, clock, X ) ," & "151 ( BC_4, DSTi_4, clock, X ) ," & "152 ( BC_4, RXSYNCi_4, clock, X ) ," & "153 ( BC_4, RXCKi_4, clock, X ) ," & "154 ( BC_4, RXCKi_5, clock, X ) ," & "155 ( BC_4, DSTi_5, clock, X ) ," & "156 ( BC_4, RXSYNCi_5, clock, X ) ," & "157 ( BC_4, RXSYNCi_6, clock, X ) ," & "158 ( BC_4, DSTi_6, clock, X ) ," & "159 ( BC_4, RXCKi_6, clock, X ) ," & "160 ( BC_4, RXCKi_7, clock, X ) ," & "161 ( BC_4, DSTi_7, clock, X ) ," & "162 ( BC_4, RXSYNCi_7, clock, X ) ," & "163 ( BC_1, DSTo_0, output3, X , 10, 1, Z)," & "164 ( BC_1, TXSYNCio_0, output3, X , 18, 1, Z)," & "165 ( BC_2, TXSYNCio_0, input, X ) ," & "166 ( BC_1, TXCKio_0, output3, X , 26, 1, Z)," & "167 ( BC_2, TXCKio_0, input, X ) ," & "168 ( BC_1, TXCKio_1, output3, X , 25, 1, Z)," & "169 ( BC_2, TXCKio_1, input, X ) ," & "170 ( BC_1, DSTo_1, output3, X , 9, 1, Z)," & "171 ( BC_1, TXSYNCio_1, output3, X , 17, 1, Z)," & "172 ( BC_2, TXSYNCio_1, input, X ) ," & "173 ( BC_1, DSTo_2, output3, X , 8, 1, Z)," & "174 ( BC_1, TXSYNCio_2, output3, X , 16, 1, Z)," & "175 ( BC_2, TXSYNCio_2, input, X ) ," & "176 ( BC_1, TXCKio_2, output3, X , 24, 1, Z)," & "177 ( BC_2, TXCKio_2, input, X ) ," & "178 ( BC_1, TXCKio_3, output3, X , 23, 1, Z)," & "179 ( BC_2, TXCKio_3, input, X ) ," & "180 ( BC_1, DSTo_3, output3, X , 7, 1, Z)," & "181 ( BC_1, TXSYNCio_3, output3, X , 15, 1, Z)," & "182 ( BC_2, TXSYNCio_3, input, X ) ," & "183 ( BC_1, DSTo_4, output3, X , 6, 1, Z)," & "184 ( BC_1, TXSYNCio_4, output3, X , 14, 1, Z)," & "185 ( BC_2, TXSYNCio_4, input, X ) ," & "186 ( BC_1, TXCKio_4, output3, X , 22, 1, Z)," & "187 ( BC_2, TXCKio_4, input, X ) ," & "188 ( BC_1, TXCKio_5, output3, X , 21, 1, Z)," & "189 ( BC_2, TXCKio_5, input, X ) ," & "190 ( BC_1, DSTo_5, output3, X , 5, 1, Z)," & "191 ( BC_1, TXSYNCio_5, output3, X , 13, 1, Z)," & "192 ( BC_2, TXSYNCio_5, input, X ) ," & "193 ( BC_1, DSTo_6, output3, X , 4, 1, Z)," & "194 ( BC_1, TXSYNCio_6, output3, X , 12, 1, Z)," & "195 ( BC_2, TXSYNCio_6, input, X ) ," & "196 ( BC_1, TXCKio_6, output3, X , 20, 1, Z)," & "197 ( BC_2, TXCKio_6, input, X ) ," & "198 ( BC_1, TXCKio_7, output3, X , 19, 1, Z)," & "199 ( BC_2, TXCKio_7, input, X ) ," & "200 ( BC_1, DSTo_7, output3, X , 3, 1, Z)," & "201 ( BC_1, TXSYNCio_7, output3, X , 11, 1, Z)," & "202 ( BC_2, TXSYNCio_7, input, X ) ," & "203 ( BC_4, Test2, clock, X ) ," & "204 ( BC_4, Test1, clock, X ) ," & "205 ( BC_4, Clk, clock, X ) "; end mt90220;