----------------------------------------------------------------------- -- Boundary Scan Description Language (IEEE P1149.1b) -- -- -- -- Device : LH75410 -- File Version : 1.1 -- File Name : LH75410_BSDL.txt -- File created : June 2, 2003 -- Package type : LQFP ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- IMPORTANT NOTICE -- -- This information is provided on an AS IS basis and without warranty. -- IN NO EVENT SHALL NXP BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL -- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF -- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR -- CUSTOMERS OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES -- WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES -- OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE. -- -- -- NXP does not represent or warrant that the information furnished -- hereunder is free of infringement of any third party patents, -- copyrights, trade secrets, or other intellectual property rights. -- NXP does not represent or warrant that the information is free of -- defect, or that it meets any particular standard, requirements or -- need of the user of the information or their customers. -- -- -- NXP reserves the right to change the information in this file -- without notice. ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- $Id: LH75410_BSDL.txt.rca 1.1 Wed Sep 14 08:07:36 2005 wwhite $ ----------------------------------------------------------------------- -- Test pins don't have boundary scans, they have been changed to -- compliance enable pins. entity LH75410 is generic(PHYSICAL_PIN_MAP : string := "LQFP"); port ( data : INOUT BIT_VECTOR( 15 DOWNTO 0); --(15-8) Gpio PA(7-0) we_n : OUT BIT; -- memory write enable oe_n : OUT BIT; -- memory read enable wait_n : INOUT BIT; -- Gpio PB5/nwait input bus cycle extend bls1_n : INOUT BIT; -- Gpio PB4/byte strobe bls0_n : INOUT BIT; -- Gpio PB3/byte strobe ce3_n : INOUT BIT; -- Gpio PB2/chip enable ce2_n : INOUT BIT; -- Gpio PB1/chip enable ce1_n : INOUT BIT; -- Gpio PB0/chip enable ce0_n : OUT BIT; -- chip enable addr23 : INOUT BIT; addr22 : INOUT BIT; addr21 : INOUT BIT; addr20 : INOUT BIT; addr19 : INOUT BIT; addr18 : INOUT BIT; addr17 : INOUT BIT; addr16 : INOUT BIT; addr15 : OUT BIT; addr14 : OUT BIT; addr13 : OUT BIT; addr12 : OUT BIT; addr11 : OUT BIT; addr10 : OUT BIT; addr9 : OUT BIT; addr8 : OUT BIT; addr7 : OUT BIT; addr6 : OUT BIT; addr5 : OUT BIT; addr4 : OUT BIT; addr3 : OUT BIT; addr2 : OUT BIT; addr1 : OUT BIT; addr0 : OUT BIT; ureset_n : IN BIT; -- test mode select test2 : IN BIT; -- test mode select test1 : IN BIT; -- test mode select tms : IN BIT; -- jtag rtck : OUT BIT; -- jtag tclk : IN BIT; -- jtag tdi : IN BIT; -- jtag tdo : OUT BIT; -- jtag analog : linkage BIT_VECTOR(7 DOWNTO 0); -- analog, Gpi PE7-PE0 vrefp : linkage BIT; -- linear regualtor voltage reference rst_gbl_n : OUT BIT; -- rst_gbl_n intr_ext : INOUT BIT_VECTOR(6 DOWNTO 0); --Gpio PD(6-0)/intr_ext_a reset_n : IN BIT; -- reset xtal_in : linkage BIT; -- 14 mhz crystal xtal_out : linkage BIT; -- 14 mhz crystal xtal32_IN : linkage BIT; -- 32 mhz crystal xtal32_OUT : linkage BIT; -- 32 mhz cystal ssifrm : INOUT BIT; -- Gpio PF7/ssfrm ssiclk : INOUT BIT; -- Gpio PF6/ssicl ssirx : INOUT BIT; -- Gpio PF5/ssirx ssitx : INOUT BIT; -- Gpio PF4/ssitx cantx : INOUT BIT; -- Gpio PF3/can/uart canrx : INOUT BIT; -- Gpio PF2/can/uart uart2tx : INOUT BIT; -- Gpio PF1/uart transmit uart2rx : INOUT BIT; -- Gpio PF0/uart receive tmr3cap1 : INOUT BIT; -- Gpio PG6/timer capture/compare tmr3cap0 : INOUT BIT; -- Gpio PG5/timer capture/compare tmr2cap1 : INOUT BIT; -- Gpio PG4/timer capture/compare tmr2cap0 : INOUT BIT; -- Gpio PG3/timer capture/compare tmr1cap4 : INOUT BIT; -- Gpio PG2/timer capture tmr1cap3 : INOUT BIT; -- Gpio PG1/timer capture tmr1cap2 : INOUT BIT; -- Gpio PG0/timer capture tmr1cap1 : INOUT BIT; -- Gpio PH7/timer capture/compare tmr1cap0 : INOUT BIT; -- Gpio PH6/timer capture/compare tmclk : INOUT BIT; -- Gpio PH5/timer clk lcdveeen : INOUT BIT; -- Gpio PH4/lcd vee enable/mod lcdvdden : INOUT BIT; -- Gpio PH3/lcd vdd enable lcddspen : INOUT BIT; -- Gpio PH2/display enable/rev lcd_cls : INOUT BIT; -- Gpio PH1/HR-TFT lcd_ps : INOUT BIT; -- Gpio PH0/power save lcdcp : INOUT BIT; -- Gpio PI7/lcdcp lcdlp : INOUT BIT; -- Gpio PI/lcdlp lcdfp : INOUT BIT; -- Gpio PI/lcdfp lcdenab : INOUT BIT; -- Gpio PI/lcdenab videod : INOUT BIT_VECTOR( 11 DOWNTO 0); --Gpio PI(3-0)/video(11-8) --Gpio PJ(7-0)/video(7-0) VDDC : linkage bit_vector(0 to 1); VSSC : linkage bit_vector(0 to 1); VDD : linkage bit_vector(0 to 8); VSS : linkage bit_vector(0 to 8); VDDA : linkage bit_vector(0 to 1); VSSA : linkage bit_vector(0 to 1) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of LH75410 : entity is "STD_1149_1_1993"; attribute PIN_MAP of LH75410 : entity is PHYSICAL_PIN_MAP; constant LQFP : PIN_MAP_STRING := "addr23: 32," & "addr22: 33," & "addr21: 35," & "addr20: 36," & "addr19: 37," & "addr18: 38," & "addr17: 39," & "addr16: 40," & "addr15: 43," & "addr14: 44," & "addr13: 45," & "addr12: 46," & "addr11: 47," & "addr10: 49," & "addr9: 50," & "addr8: 51," & "addr7: 52," & "addr6: 53," & "addr5: 55," & "addr4: 56," & "addr3: 57," & "addr2: 58," & "addr1: 60," & "addr0: 61," & "analog: (89,90,91,92,93,94,95,96)," & "bls0_n: 27," & "bls1_n: 25," & "canrx: 104," & "cantx: 103," & "ce0_n: 31," & "ce1_n: 30," & "ce2_n: 29," & "ce3_n: 28," & "data: (1,2,4,5,6,7,9,10,12,13,15,16,18,19,20,21)," & "intr_ext: (72,73,74,76,77,78,79)," & "lcd_cls: 123," & "lcd_ps: 124," & "lcdcp: 125," & "lcddspen: 122," & "lcdenab: 130," & "lcdfp: 129," & "lcdlp: 128," & "lcdvdden: 121," & "lcdveeen: 120," & "oe_n: 23," & "reset_n: 81," & "rst_gbl_n: 71," & "rtck: 66," & "ssiclk: 100," & "ssifrm: 99," & "ssirx: 101," & "ssitx: 102," & "test1: 64," & "test2: 63," & "tmclk: 118," & "tmr1cap0: 117," & "tmr1cap1: 116," & "tmr1cap2: 115," & "tmr1cap3: 114," & "tmr1cap4: 113," & "tmr2cap0: 111," & "tmr2cap1: 110," & "tmr3cap0: 109," & "tmr3cap1: 108," & "uart2rx: 107," & "uart2tx: 105," & "ureset_n: 62," & "videod: (131,132,133,135,136,137,138,139,141,142,143,144)," & "vrefp: 70," & "wait_n: 24," & "we_n: 22," & "tdi: 68," & "tms: 65," & "tclk: 67," & "tdo: 69," & "xtal_in: 86," & "xtal_out: 87," & "xtal32_IN: 82," & "xtal32_OUT: 83," & "VDDC : (75,11),"& "VSSC : (14,80),"& "VDD : (3,17,34,42,54,98,112,126,134),"& "VSS : (8,26,41,48,59,106,119,127,140),"& "VDDA : (85,97), "& "VSSA : (84,88) "; attribute TAP_SCAN_IN of tdi : signal is true; attribute TAP_SCAN_MODE of tms : signal is true; attribute TAP_SCAN_OUT of tdo : signal is true; attribute TAP_SCAN_CLOCK of tclk : signal is (20.0e6, BOTH); attribute TAP_SCAN_RESET of reset_n : signal is true; attribute COMPLIANCE_PATTERNS of LH75410: entity is "(test1, test2) (11) "; attribute INSTRUCTION_LENGTH of LH75410 : entity is 3; attribute INSTRUCTION_OPCODE of LH75410 : entity is "extest (000)," & "bypass (111)," & "sample (001)," & "highz (010)," & "clamp (011)," & "idcode (100)"; attribute INSTRUCTION_CAPTURE of LH75410 : entity is "001"; attribute IDCODE_REGISTER of LH75410 : entity is "0000" & -- Version Number "0000011101010100" & -- Part Number "00000110000" & -- Manufacturer ID "1"; -- Required by IEEE Std. 1149.1-1990 attribute REGISTER_ACCESS of LH75410 : entity is "BOUNDARY (extest, sample), " & "DEVICE_ID (idcode), " & "BYPASS (bypass, highz, clamp)"; attribute BOUNDARY_LENGTH of LH75410 : entity is 273; attribute BOUNDARY_REGISTER of LH75410 : entity is "0 (BC_1, data(15), input, X)," & "1 (BC_1, data(15), output3, X, 2, 0, Z)," & "2 (BC_1, *, control, 0)," & "3 (BC_1, data(14), input, X)," & "4 (BC_1, data(14), output3, X, 5, 0, Z)," & "5 (BC_1, *, control, 0)," & "6 (BC_1, data(13), input, X)," & "7 (BC_1, data(13), output3, X, 8, 0, Z)," & "8 (BC_1, *, control, 0)," & "9 (BC_1, data(12), input, X)," & "10 (BC_1, data(12), output3, X, 11, 0, Z)," & "11 (BC_1, *, control, 0)," & "12 (BC_1, data(11), input, X)," & "13 (BC_1, data(11), output3, X, 14, 0, Z)," & "14 (BC_1, *, control, 0)," & "15 (BC_1, data(10), input, X)," & "16 (BC_1, data(10), output3, X, 17, 0, Z)," & "17 (BC_1, *, control, 0)," & "18 (BC_1, data(9), input, X)," & "19 (BC_1, data(9), output3, X, 20, 0, Z)," & "20 (BC_1, *, control, 0)," & "21 (BC_1, data(8), input, X)," & "22 (BC_1, data(8), output3, X, 23, 0, Z)," & "23 (BC_1, *, control, 0)," & "24 (BC_1, data(7), input, X)," & "25 (BC_1, data(7), output3, X, 26, 0, Z)," & "26 (BC_1, *, control, 0)," & "27 (BC_1, data(6), input, X)," & "28 (BC_1, data(6), output3, X, 29, 0, Z)," & "29 (BC_1, *, control, 0)," & "30 (BC_1, data(5), input, X)," & "31 (BC_1, data(5), output3, X, 32, 0, Z)," & "32 (BC_1, *, control, 0)," & "33 (BC_1, data(4), input, X)," & "34 (BC_1, data(4), output3, X, 35, 0, Z)," & "35 (BC_1, *, control, 0)," & "36 (BC_1, data(3), input, X)," & "37 (BC_1, data(3), output3, X, 38, 0, Z)," & "38 (BC_1, *, control, 0)," & "39 (BC_1, data(2), input, X)," & "40 (BC_1, data(2), output3, X, 41, 0, Z)," & "41 (BC_1, *, control, 0)," & "42 (BC_1, data(1), input, X)," & "43 (BC_1, data(1), output3, X, 44, 0, Z)," & "44 (BC_1, *, control, 0)," & "45 (BC_1, data(0), input, X)," & "46 (BC_1, data(0), output3, X, 47, 0, Z)," & "47 (BC_1, *, control, 0)," & "48 (bc_1, we_n, output3, X, 49, 0, Z)," & "49 (bc_1, *, control, 0)," & "50 (bc_1, oe_n, output3, X, 51, 0, Z)," & "51 (bc_1, *, control, 0)," & "52 (BC_1, wait_n, input, X)," & "53 (BC_1, wait_n, output3, X, 54, 0, Z)," & "54 (BC_1, *, control, 0)," & "55 (BC_1, bls1_n, input, X)," & "56 (BC_1, bls1_n, output3, X, 57, 0, Z)," & "57 (BC_1, *, control, 0)," & "58 (BC_1, bls0_n, input, X)," & "59 (BC_1, bls0_n, output3, X, 60, 0, Z)," & "60 (BC_1, *, control, 0)," & "61 (BC_1, ce3_n, input, X)," & "62 (BC_1, ce3_n, output3, X, 63, 0, Z)," & "63 (BC_1, *, control, 0)," & "64 (BC_1, ce2_n, input, X)," & "65 (BC_1, ce2_n, output3, X, 66, 0, Z)," & "66 (BC_1, *, control, 0)," & "67 (BC_1, ce1_n, input, X)," & "68 (BC_1, ce1_n, output3, X, 69, 0, Z)," & "69 (BC_1, *, control, 0)," & "70 (bc_1, ce0_n, output3, X, 71, 0, Z)," & "71 (bc_1, *, control, 0)," & "72 (BC_1, addr23, input, X)," & "73 (BC_1, addr23, output3, X, 74, 0, Z)," & "74 (BC_1, *, control, 0)," & "75 (BC_1, addr22, input, X)," & "76 (BC_1, addr22, output3, X, 77, 0, Z)," & "77 (BC_1, *, control, 0)," & "78 (BC_1, addr21, input, X)," & "79 (BC_1, addr21, output3, X, 80, 0, Z)," & "80 (BC_1, *, control, 0)," & "81 (BC_1, addr20, input, X)," & "82 (BC_1, addr20, output3, X, 83, 0, Z)," & "83 (BC_1, *, control, 0)," & "84 (BC_1, addr19, input, X)," & "85 (BC_1, addr19, output3, X, 86, 0, Z)," & "86 (BC_1, *, control, 0)," & "87 (BC_1, addr18, input, X)," & "88 (BC_1, addr18, output3, X, 89, 0, Z)," & "89 (BC_1, *, control, 0)," & "90 (BC_1, addr17, input, X)," & "91 (BC_1, addr17, output3, X, 92, 0, Z)," & "92 (BC_1, *, control, 0)," & "93 (BC_1, addr16, input, X)," & "94 (BC_1, addr16, output3, X, 95, 0, Z)," & "95 (BC_1, *, control, 0)," & "96 (bc_1, addr15, output3, X, 97, 0, Z)," & "97 (bc_1, *, control, 0)," & "98 (bc_1, addr14, output3, X, 99, 0, Z)," & "99 (bc_1, *, control, 0)," & "100 (bc_1, addr13, output3, X, 101, 0, Z)," & "101 (bc_1, *, control, 0)," & "102 (bc_1, addr12, output3, X, 103, 0, Z)," & "103 (bc_1, *, control, 0)," & "104 (bc_1, addr11, output3, X, 105, 0, Z)," & "105 (bc_1, *, control, 0)," & "106 (bc_1, addr10, output3, X, 107, 0, Z)," & "107 (bc_1, *, control, 0)," & "108 (bc_1, addr9, output3, X, 109, 0, Z)," & "109 (bc_1, *, control, 0)," & "110 (bc_1, addr8, output3, X, 111, 0, Z)," & "111 (bc_1, *, control, 0)," & "112 (bc_1, addr7, output3, X, 113, 0, Z)," & "113 (bc_1, *, control, 0)," & "114 (bc_1, addr6, output3, X, 115, 0, Z)," & "115 (bc_1, *, control, 0)," & "116 (bc_1, addr5, output3, X, 117, 0, Z)," & "117 (bc_1, *, control, 0)," & "118 (bc_1, addr4, output3, X, 119, 0, Z)," & "119 (bc_1, *, control, 0)," & "120 (bc_1, addr3, output3, X, 121, 0, Z)," & "121 (bc_1, *, control, 0)," & "122 (bc_1, addr2, output3, X, 123, 0, Z)," & "123 (bc_1, *, control, 0)," & "124 (bc_1, addr1, output3, X, 125, 0, Z)," & "125 (bc_1, *, control, 0)," & "126 (bc_1, addr0, output3, X, 127, 0, Z)," & "127 (bc_1, *, control, 0)," & "128 (bc_1, ureset_n, input, X)," & "129 (bc_1, *, internal, 1)," & "130 (bc_1, *, internal, 1)," & "131 (bc_1, rtck, output3, X, 132, 0, Z)," & "132 (bc_1, *, control, 0)," & "133 (bc_1, rst_gbl_n, output3, X, 134, 0, Z)," & "134 (bc_1, *, control, 0)," & "135 (BC_1, intr_ext(6), input, X)," & "136 (BC_1, intr_ext(6), output3, X, 137, 0, Z)," & "137 (BC_1, *, control, 0)," & "138 (BC_1, intr_ext(5), input, X)," & "139 (BC_1, intr_ext(5), output3, X, 140, 0, Z)," & "140 (BC_1, *, control, 0)," & "141 (BC_1, intr_ext(4), input, X)," & "142 (BC_1, intr_ext(4), output3, X, 143, 0, Z)," & "143 (BC_1, *, control, 0)," & "144 (BC_1, intr_ext(3), input, X)," & "145 (BC_1, intr_ext(3), output3, X, 146, 0, Z)," & "146 (BC_1, *, control, 0)," & "147 (BC_1, intr_ext(2), input, X)," & "148 (BC_1, intr_ext(2), output3, X, 149, 0, Z)," & "149 (BC_1, *, control, 0)," & "150 (BC_1, intr_ext(1), input, X)," & "151 (BC_1, intr_ext(1), output3, X, 152, 0, Z)," & "152 (BC_1, *, control, 0)," & "153 (BC_1, intr_ext(0), input, X)," & "154 (BC_1, intr_ext(0), output3, X, 155, 0, Z)," & "155 (BC_1, *, control, 0)," & "156 (BC_1, ssifrm, input, X)," & "157 (BC_1, ssifrm, output3, X, 158, 0, Z)," & "158 (BC_1, *, control, 0)," & "159 (BC_1, ssiclk, input, X)," & "160 (BC_1, ssiclk, output3, X, 161, 0, Z)," & "161 (BC_1, *, control, 0)," & "162 (BC_1, ssirx, input, X)," & "163 (BC_1, ssirx, output3, X, 164, 0, Z)," & "164 (BC_1, *, control, 0)," & "165 (BC_1, ssitx, input, X)," & "166 (BC_1, ssitx, output3, X, 167, 0, Z)," & "167 (BC_1, *, control, 0)," & "168 (BC_1, cantx, input, X)," & "169 (BC_1, cantx, output3, X, 170, 0, Z)," & "170 (BC_1, *, control, 0)," & "171 (BC_1, canrx, input, X)," & "172 (BC_1, canrx, output3, X, 173, 0, Z)," & "173 (BC_1, *, control, 0)," & "174 (BC_1, uart2tx, input, X)," & "175 (BC_1, uart2tx, output3, X, 176, 0, Z)," & "176 (BC_1, *, control, 0)," & "177 (BC_1, uart2rx, input, X)," & "178 (BC_1, uart2rx, output3, X, 179, 0, Z)," & "179 (BC_1, *, control, 0)," & "180 (BC_1, tmr3cap1, input, X)," & "181 (BC_1, tmr3cap1, output3, X, 182, 0, Z)," & "182 (BC_1, *, control, 0)," & "183 (BC_1, tmr3cap0, input, X)," & "184 (BC_1, tmr3cap0, output3, X, 185, 0, Z)," & "185 (BC_1, *, control, 0)," & "186 (BC_1, tmr2cap1, input, X)," & "187 (BC_1, tmr2cap1, output3, X, 188, 0, Z)," & "188 (BC_1, *, control, 0)," & "189 (BC_1, tmr2cap0, input, X)," & "190 (BC_1, tmr2cap0, output3, X, 191, 0, Z)," & "191 (BC_1, *, control, 0)," & "192 (BC_1, tmr1cap4, input, X)," & "193 (BC_1, tmr1cap4, output3, X, 194, 0, Z)," & "194 (BC_1, *, control, 0)," & "195 (BC_1, tmr1cap3, input, X)," & "196 (BC_1, tmr1cap3, output3, X, 197, 0, Z)," & "197 (BC_1, *, control, 0)," & "198 (BC_1, tmr1cap2, input, X)," & "199 (BC_1, tmr1cap2, output3, X, 200, 0, Z)," & "200 (BC_1, *, control, 0)," & "201 (BC_1, tmr1cap1, input, X)," & "202 (BC_1, tmr1cap1, output3, X, 203, 0, Z)," & "203 (BC_1, *, control, 0)," & "204 (BC_1, tmr1cap0, input, X)," & "205 (BC_1, tmr1cap0, output3, X, 206, 0, Z)," & "206 (BC_1, *, control, 0)," & "207 (BC_1, tmclk, input, X)," & "208 (BC_1, tmclk, output3, X, 209, 0, Z)," & "209 (BC_1, *, control, 0)," & "210 (BC_1, lcdveeen, input, X)," & "211 (BC_1, lcdveeen, output3, X, 212, 0, Z)," & "212 (BC_1, *, control, 0)," & "213 (BC_1, lcdvdden, input, X)," & "214 (BC_1, lcdvdden, output3, X, 215, 0, Z)," & "215 (BC_1, *, control, 0)," & "216 (BC_1, lcddspen, input, X)," & "217 (BC_1, lcddspen, output3, X, 218, 0, Z)," & "218 (BC_1, *, control, 0)," & "219 (BC_1, lcd_cls, input, X)," & "220 (BC_1, lcd_cls, output3, X, 221, 0, Z)," & "221 (BC_1, *, control, 0)," & "222 (BC_1, lcd_ps, input, X)," & "223 (BC_1, lcd_ps, output3, X, 224, 0, Z)," & "224 (BC_1, *, control, 0)," & "225 (BC_1, lcdcp, input, X)," & "226 (BC_1, lcdcp, output3, X, 227, 0, Z)," & "227 (BC_1, *, control, 0)," & "228 (BC_1, lcdlp, input, X)," & "229 (BC_1, lcdlp, output3, X, 230, 0, Z)," & "230 (BC_1, *, control, 0)," & "231 (BC_1, lcdfp, input, X)," & "232 (BC_1, lcdfp, output3, X, 233, 0, Z)," & "233 (BC_1, *, control, 0)," & "234 (BC_1, lcdenab, input, X)," & "235 (BC_1, lcdenab, output3, X, 236, 0, Z)," & "236 (BC_1, *, control, 0)," & "237 (BC_1, videod(11), input, X)," & "238 (BC_1, videod(11), output3, X, 239, 0, Z)," & "239 (BC_1, *, control, 0)," & "240 (BC_1, videod(10), input, X)," & "241 (BC_1, videod(10), output3, X, 242, 0, Z)," & "242 (BC_1, *, control, 0)," & "243 (BC_1, videod(9), input, X)," & "244 (BC_1, videod(9), output3, X, 245, 0, Z)," & "245 (BC_1, *, control, 0)," & "246 (BC_1, videod(8), input, X)," & "247 (BC_1, videod(8), output3, X, 248, 0, Z)," & "248 (BC_1, *, control, 0)," & "249 (BC_1, videod(7), input, X)," & "250 (BC_1, videod(7), output3, X, 251, 0, Z)," & "251 (BC_1, *, control, 0)," & "252 (BC_1, videod(6), input, X)," & "253 (BC_1, videod(6), output3, X, 254, 0, Z)," & "254 (BC_1, *, control, 0)," & "255 (BC_1, videod(5), input, X)," & "256 (BC_1, videod(5), output3, X, 257, 0, Z)," & "257 (BC_1, *, control, 0)," & "258 (BC_1, videod(4), input, X)," & "259 (BC_1, videod(4), output3, X, 260, 0, Z)," & "260 (BC_1, *, control, 0)," & "261 (BC_1, videod(3), input, X)," & "262 (BC_1, videod(3), output3, X, 263, 0, Z)," & "263 (BC_1, *, control, 0)," & "264 (BC_1, videod(2), input, X)," & "265 (BC_1, videod(2), output3, X, 266, 0, Z)," & "266 (BC_1, *, control, 0)," & "267 (BC_1, videod(1), input, X)," & "268 (BC_1, videod(1), output3, X, 269, 0, Z)," & "269 (BC_1, *, control, 0)," & "270 (BC_1, videod(0), input, X)," & "271 (BC_1, videod(0), output3, X, 272, 0, Z)," & "272 (BC_1, *, control, 0)"; end LH75410;