----------------------------------------------------------------------- -- Boundary Scan Description Language (IEEE P1149.1b) -- -- -- -- Device : LH79525 -- File Version : 1.2 -- File Name : LH79525_BSDL.txt -- File created : DEC 22, 2003 -- Package type : LQFP ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- IMPORTANT NOTICE -- -- This information is provided on an AS IS basis and without warranty. -- IN NO EVENT SHALL NXP BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL -- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF -- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR -- CUSTOMERS OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES -- WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES -- OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE. -- -- -- NXP does not represent or warrant that the information furnished -- hereunder is free of infringement of any third party patents, -- copyrights, trade secrets, or other intellectual property rights. -- NXP does not represent or warrant that the information is free of -- defect, or that it meets any particular standard, requirements or -- need of the user of the information or their customers. -- -- -- NXP reserves the right to change the information in this file -- without notice. ----------------------------------------------------------------------- -- $Id: LH79525_BSDL.txt.rca 1.2 Wed Sep 14 08:57:35 2005 wwhite Experimental $ ----------------------------------------------------------------------- entity LH79525 is generic(PHYSICAL_PIN_MAP : string := "LQFP"); port ( LINREGEN: LINKAGE BIT; -- linear regulator enable AN9 : LINKAGE BIT; -- AN9/PJ2 ADC input muxed with PJ2 AN8 : LINKAGE BIT; -- AN8/PJ4 ADC input muxed with PJ4 AN7 : LINKAGE BIT; -- AN7/PJ6/INT6 ADC input muxed with PJ6/INT6 AN6 : LINKAGE BIT; -- AN6/PJ7/INT7 ADC input muxed with PJ7/INT7 AN5 : LINKAGE BIT; -- AN5/PJ5/INT5 ADC input muxed with PJ5/INT5 AN4 : LINKAGE BIT; -- AN4/WIPER/PJ1 ADC input muxed with PJ1 AN3 : LINKAGE BIT; -- AN3/LR/Y-/PJ0 ADC input muxed with PJ0 AN2 : LINKAGE BIT; -- AN2/LL/Y+/PJ3 ADC input muxed with PJ3 AN1 : LINKAGE BIT; -- AN1/UR/X- ADC input AN0 : LINKAGE BIT; -- AN0/UL/X+ ADC input nRESETOUT: OUT BIT; -- System Reset Output CLKOUT : OUT BIT; -- System Reset Output nRESETIN: IN BIT; -- Reset Input INT4 : INOUT BIT; --INT4/CTCLK/BATCNTL PA7 : INOUT BIT; --PA7/CTCAP2B/CTCMP2B/SCL PA6 : INOUT BIT; --PA6/CTCAP2A/CTCMP2A/SDA PA5 : INOUT BIT; --PA5/CTCAP1B/CTCMP1B PA4 : INOUT BIT; --PA4/CTCAP1A/CTCMP1A PA3 : INOUT BIT; --PA3/CTCAP0B/CTCMP0B PA2 : INOUT BIT; --PA2/CTCAP0A/CTCMP0A PA1 : INOUT BIT; --PA1/INT3/UARTTX2/UARTIRTX2 PA0 : INOUT BIT; --PA0/INT2/UARTRX2/UARTIRRX2 PB7 : INOUT BIT; --PB7/INT1/UARTTX0/UARTIRTX0 PB6 : INOUT BIT; --PB6/INT0/UARTRX0/UARTIRRX0 PB5 : INOUT BIT; --PB5/SSPTX/I2STXD/UARTTX1/UARTIRTX1 PB4 : INOUT BIT; --PB4/SSPRX/I2SRXD/UARTRX1/UARTIRRX1 PB3 : INOUT BIT; --PB3/SSPCLK/I2SCLK PB2 : INOUT BIT; --PB2/SSPFRM/I2SWS PB1 : INOUT BIT; --PB1/DREQ/nUARTRTS0 PB0 : INOUT BIT; --PB1/nDACK/nUARTCTS0 nTRST : IN BIT; -- JTAG reset TDO : OUT BIT; -- JTAG test data out TDI : IN BIT; -- JTAG test data in TMS : IN BIT; -- JTAG Test mode select TCK : IN BIT; -- JTAG Test clock TEST1 : IN BIT; -- Test mode pin 1 TEST2 : IN BIT; -- Test mode pin 2 PC7 : INOUT BIT; -- PC7/A23/nFRE PC6 : INOUT BIT; -- PC6/A22/nFWE PC5 : INOUT BIT; -- PC5/A21 PC4 : INOUT BIT; -- PC4/A20 PC3 : INOUT BIT; -- PC3/A19 PC2 : INOUT BIT; -- PC2/A18 PC1 : INOUT BIT; -- PC1/A17 PC0 : INOUT BIT; -- PC0/A16 A15 : OUT BIT; -- Ex Mem Controller Address bit 15 A14 : OUT BIT; -- Ex Mem Controller Address bit 14 A13 : OUT BIT; -- Ex Mem Controller Address bit 13 A12 : OUT BIT; -- Ex Mem Controller Address bit 12 A11 : OUT BIT; -- Ex Mem Controller Address bit 11 A10 : OUT BIT; -- Ex Mem Controller Address bit 10 A9 : OUT BIT; -- Ex Mem Controller Address bit 9 A8 : OUT BIT; -- Ex Mem Controller Address bit 8 A7 : OUT BIT; -- Ex Mem Controller Address bit 7 A6 : OUT BIT; -- Ex Mem Controller Address bit 6 A5 : OUT BIT; -- Ex Mem Controller Address bit 5 A4 : OUT BIT; -- Ex Mem Controller Address bit 4 A3 : OUT BIT; -- Ex Mem Controller Address bit 3 A2 : OUT BIT; -- Ex Mem Controller Address bit 2 A1 : OUT BIT; -- Ex Mem Controller Address bit 1 A0 : OUT BIT; -- Ex Mem Controller Address bit 0 PD7 : INOUT BIT; --PD7/D15 (Data to/from mem controller) PD6 : INOUT BIT; --PD6/D14 (Data to/from mem controller) PD5 : INOUT BIT; --PD5/D13 (Data to/from mem controller) PD4 : INOUT BIT; --PD4/D12 (Data to/from mem controller) PD3 : INOUT BIT; --PD3/D11 (Data to/from mem controller) PD2 : INOUT BIT; --PD2/D10 (Data to/from mem controller) PD1 : INOUT BIT; --PD1/D9 (Data to/from mem controller) PD0 : INOUT BIT; --PD0/D8 (Data to/from mem controller) D7 : INOUT BIT; --Data to/from mem controller D6 : INOUT BIT; --Data to/from mem controller D5 : INOUT BIT; --Data to/from mem controller D4 : INOUT BIT; --Data to/from mem controller D3 : INOUT BIT; --Data to/from mem controller D2 : INOUT BIT; --Data to/from mem controller D1 : INOUT BIT; --Data to/from mem controller D0 : INOUT BIT; --Data to/from mem controller nCS3 : OUT BIT; --nCS3/PM3 Ex mem controller static chip select nCS2 : OUT BIT; --nCS2/PM2 Ex mem controller static chip select nCS1 : OUT BIT; --nCS1/PM1 Ex mem controller static chip select nCS0 : OUT BIT; --nCS0/PM0 Ex mem controller static chip select nOE : OUT BIT; --Ex mem controller output enable nBLE1 : OUT BIT; --nBLE1/PM5 Byte lane enable muxed with GPIO PM5 nBLE0 : INOUT BIT; --nBLE0/PM4 Byte lane enable muxed with PM4 nWE : OUT BIT; --Ex mem controller write enable nCAS : OUT BIT; --Ex mem controller column address strobe nRAS : OUT BIT; --Ex mem controller row address strobe nDCS1 : OUT BIT; --Ex mem controller dynamic chip select nDCS0 : OUT BIT; --Ex mem controller dynamic chip select SDCKE : OUT BIT; --Ex mem controller dynamic clock enable SDCLK : INOUT BIT; --Ex mem controller clock out DQM1 : OUT BIT; --Ex mem controller dynamic mem data mask output DQM0 : OUT BIT; --Ex mem controller dynamic mem data mask output XTAL32IN: LINKAGE BIT; --32.768KHZ Crystal Clock Input XTAL32OUT: LINKAGE BIT; --32.768KHZ Crystal Clock Output XTALIN : LINKAGE BIT; --Crystal Clock Input XTALOUT : LINKAGE BIT; --Crystal Clock Output USBDN : LINKAGE BIT; -- USB Data Positive (differential input) USBDP : LINKAGE BIT; -- USB Data Negative (differential input) PE7 : INOUT BIT;--PE7/nWAIT/nDEOT PE6 : INOUT BIT; --PE6/LCDVEEN/LCDMOD PE5 : INOUT BIT; --PE5/LCDVDDEN PE4 : INOUT BIT; --PE4/LCDSPLEN/LCDREV PE3 : INOUT BIT; --PE3/LCDCLS PE2 : INOUT BIT; --PE2/LCDPS PE1 : INOUT BIT; --PE1/LCDDCLK PE0 : INOUT BIT; --PE0/LCDLP/LCDHRLP PF7 : INOUT BIT; --PF7/LCDFP/LCDSPS PF6 : INOUT BIT; --PF6/LCDEN/LCDSPL PF5 : INOUT BIT; --PF5/LCDVD11 PF4 : INOUT BIT; --PF4/LCDVD10 PF3 : INOUT BIT; --PF4/LCDVD9 PF2 : INOUT BIT; --PF2/LCDVD8 PF1 : INOUT BIT; --PF1/LCDVD7 PF0 : INOUT BIT; --PF0/LCDVD6 PG7 : INOUT BIT; --PG7/LCDVD5 PG6 : INOUT BIT; --PG6/LCDVD4 PG5 : INOUT BIT; --PG5/LCDVD3 PG4 : INOUT BIT; --PG4/LCDVD2 PG3 : INOUT BIT; --PG3/LCDVD1 PG2 : INOUT BIT; --PG2/LCDVD0 PG1 : INOUT BIT; --PG1/ETHERTXCLK PG0 : INOUT BIT; --PG0/ETHERTXEN PH7 : INOUT BIT; --PH7/ETHERTX3 PH6 : INOUT BIT; --PH6/ETHERTX2 PH5 : INOUT BIT; --PH5/ETHERTX1 PH4 : INOUT BIT; --PH4/ETHERTX0 PH3 : INOUT BIT; --PH3/ETHERTXER PH2 : INOUT BIT; --PH2/ETHERRXCLK PH1 : INOUT BIT; --PH1/ETHERRXDV PH0 : INOUT BIT; --PH0/ETHERRX3 PI7 : INOUT BIT; --PI7/ETHERRX2 PI6 : INOUT BIT; --PI6/ETHERRX1 PI5 : INOUT BIT; --PI5/ETHERRX0 PI4 : INOUT BIT; --PI4/ETHERRXER PI3 : INOUT BIT; --PI3/ETHERCRS PI2 : INOUT BIT; -- PI2/ETHERCOL PI1 : INOUT BIT; -- PI1/ETHERMDIO PI0 : INOUT BIT; -- PI0/ETHERMDC VDD : LINKAGE BIT_VECTOR(1 to 11); -- I/O RING VSS VSS : LINKAGE BIT_VECTOR(1 to 11); -- I/O RING VSS VDDC : LINKAGE BIT_VECTOR(1 to 4); -- Digital Core VDD VSSC : LINKAGE BIT_VECTOR(1 to 4); -- Digital Core GND VDDA0 : LINKAGE BIT; -- Analog power for PLL1 VSSA0 : LINKAGE BIT; -- Analog GND for PLL1 VSSA1 : LINKAGE BIT; -- Analog GND for PLL1 VDDA1 : LINKAGE BIT; -- Analog power for PLL2 VDDA2 : LINKAGE BIT; -- Analog power for PLL2 VSSA2 : LINKAGE BIT -- Analog GND for PLL2 ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of LH79525 : entity is "STD_1149_1_1993"; attribute PIN_MAP of LH79525 : entity is PHYSICAL_PIN_MAP; constant LQFP : PIN_MAP_STRING := "PI2 : 1," & "PI1 : 2," & "PI0 : 4," & "nTRST : 8," & "LINREGEN : 9," & "VDDA0 : 10," & "AN0 : 11," & "AN6 : 12," & "AN7 : 13," & "AN1 : 14," & "AN5 : 15," & "AN8 : 16," & "AN2 : 17," & "AN9 : 18," & "AN4 : 19," & "AN3 : 20," & "VSSA0 : 21," & "nRESETOUT : 22," & "CLKOUT : 23," & "nRESETIN : 24," & "INT4 : 25," & "PA7 : 28," & "PA6 : 29," & "PA5 : 30," & "PA4 : 31," & "PA3 : 32," & "PA2 : 34," & "PA1 : 35," & "PA0 : 36," & "PB7 : 37," & "PB6 : 38," & "PB5 : 39," & "PB4 : 40," & "PB3 : 41," & "PB2 : 42," & "PB1 : 43," & "PB0 : 44," & "TDO : 45," & "TDI : 46," & "TEST1 : 47," & "TEST2 : 48," & "TMS : 50," & "TCK : 51," & "PC7 : 52," & "PC6 : 53," & "PC5 : 54," & "PC4 : 55," & "PC3 : 56," & "PC2 : 58," & "PC1 : 59," & "PC0 : 60," & "A15 : 61," & "A14 : 62," & "A13 : 63," & "A12 : 65," & "A11 : 67," & "A10 : 69," & "A9 : 70," & "A8 : 71," & "A7 : 72," & "A6 : 73," & "A5 : 74," & "A4 : 76," & "A3 : 77," & "A2 : 78," & "A1 : 79," & "A0 : 80," & "PD7 : 82," & "PD6 : 83," & "PD5 : 84," & "PD4 : 85," & "PD3 : 87," & "PD2 : 88," & "PD1 : 89," & "PD0 : 90," & "D7 : 91," & "D6 : 93," & "D5 : 94," & "D4 : 95," & "D3 : 96," & "D2 : 97," & "D1 : 98," & "D0 : 99," & "nCS3 : 100," & "nCS2 : 102," & "nCS1 : 103," & "nCS0 : 104," & "nOE : 106," & "nBLE1 : 109," & "nBLE0 : 110," & "nWE : 111," & "nCAS : 112," & "nRAS : 113," & "nDCS1 : 114," & "nDCS0 : 115," & "SDCKE : 116," & "SDCLK : 117," & "DQM1 : 118," & "DQM0 : 119," & "PE7 : 120," & "VSSA1 : 121," & "VDDA1 : 122," & "VDDA2 : 123," & "VSSA2 : 124," & "XTAL32IN : 125," & "XTAL32OUT : 126," & "XTALIN : 127," & "XTALOUT : 128," & "USBDN : 130," & "USBDP : 131," & "PE6 : 133," & "PE5 : 134," & "PE4 : 136," & "PE3 : 137," & "PE2 : 138," & "PE1 : 139," & "PE0 : 141," & "PF7 : 142," & "PF6 : 143," & "PF5 : 145," & "PF4 : 146," & "PF3 : 147," & "PF2 : 149," & "PF1 : 151," & "PF0 : 153," & "PG7 : 154," & "PG6 : 155," & "PG5 : 156," & "PG4 : 157," & "PG3 : 158," & "PG2 : 159," & "PG1 : 161," & "PG0 : 162," & "PH7 : 163," & "PH6 : 164," & "PH5 : 165," & "PH4 : 166," & "PH3 : 167," & "PH2 : 169," & "PH1 : 170," & "PH0 : 171," & "PI7 : 172," & "PI6 : 173," & "PI5 : 174," & "PI4 : 175," & "PI3 : 176," & "VDD : (3,26,33,57,75,86,101,129," & "135,144,160)," & "VSS : (5,27,49,68,81,92,108,132," & "140,152,168)," & "VDDC : (6,66,107,150)," & "VSSC : (7,64,105,148)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6,BOTH); attribute TAP_SCAN_RESET of nTRST : signal is true; attribute COMPLIANCE_PATTERNS of LH79525: entity is "(TEST1, TEST2,nRESETIN ) (111)"; attribute INSTRUCTION_LENGTH of LH79525 : entity is 3; attribute INSTRUCTION_OPCODE of LH79525 : entity is "extest (000)," & "bypass (111)," & "sample (001)," & "highz (010)," & "clamp (011)," & "idcode (100)"; attribute INSTRUCTION_CAPTURE of LH79525 : entity is "001"; attribute IDCODE_REGISTER of LH79525 : entity is "0000" & -- Version Number "1001010100100100" & -- Part number "00000110000" & -- Manufactuer ID "1"; -- Required by IEEE Std. 1149.1 attribute REGISTER_ACCESS of LH79525 : entity is "BOUNDARY (extest,sample), " & "DEVICE_ID (idcode), " & "BYPASS (bypass, highz, clamp)"; --{********************************************************} --{ The first cell, cell 0 is closest to TDO } --{ BC_1: used on all control and Output3 cells } --{ BC_4: used on all inputs } --{********************************************************} attribute BOUNDARY_LENGTH of LH79525 : entity is 313; attribute BOUNDARY_REGISTER of LH79525 : entity is -- # cell name function safe control disable disable -- type bit signal value result "0 (BC_1, *, control, 0 )," & "1 (BC_1, PB0, output3, X, 0, 0, Z)," & "2 (BC_4, PB0, observe_only, X )," & "3 (BC_1, *, control, 0 )," & "4 (BC_1, PB1, output3, X, 3, 0, Z)," & "5 (BC_4, PB1, observe_only, X )," & "6 (BC_1, *, control, 0 )," & "7 (BC_1, PB2, output3, X, 6, 0, Z)," & "8 (BC_4, PB2, observe_only, X )," & "9 (BC_1, *, control, 0 )," & "10 (BC_1, PB3, output3, X, 9, 0, Z)," & "11 (BC_4, PB3, observe_only, X )," & "12 (BC_1, *, control, 0 )," & "13 (BC_1, PB4, output3, X, 12, 0, Z)," & "14 (BC_4, PB4, observe_only, X )," & "15 (BC_1, *, control, 0 )," & "16 (BC_1, PB5, output3, X, 15, 0, Z)," & "17 (BC_4, PB5, observe_only, X )," & "18 (BC_1, *, control, 0 )," & "19 (BC_1, PB6, output3, X, 18, 0, Z)," & "20 (BC_4, PB6, observe_only, X )," & "21 (BC_1, *, control, 0 )," & "22 (BC_1, PB7, output3, X, 21, 0, Z)," & "23 (BC_4, PB7, observe_only, X )," & "24 (BC_1, *, control, 0 )," & "25 (BC_1, PA0, output3, X, 24, 0, Z)," & "26 (BC_4, PA0, observe_only, X )," & "27 (BC_1, *, control, 0 )," & "28 (BC_1, PA1, output3, X, 27, 0, Z)," & "29 (BC_4, PA1, observe_only, X )," & "30 (BC_1, *, control, 0 )," & "31 (BC_1, PA2, output3, X, 30, 0, Z)," & "32 (BC_4, PA2, observe_only, X )," & "33 (BC_1, *, control, 0 )," & "34 (BC_1, PA3, output3, X, 33, 0, Z)," & "35 (BC_4, PA3, observe_only, X )," & "36 (BC_1, *, control, 0 )," & "37 (BC_1, PA4, output3, X, 36, 0, Z)," & "38 (BC_4, PA4, observe_only, X )," & "39 (BC_1, *, control, 0 )," & "40 (BC_1, PA5, output3, X, 39, 0, Z)," & "41 (BC_4, PA5, observe_only, X )," & "42 (BC_1, *, control, 0 )," & "43 (BC_1, PA6, output3, X, 42, 0, Z)," & "44 (BC_4, PA6, observe_only, X )," & "45 (BC_1, *, control, 0 )," & "46 (BC_1, PA7, output3, X, 45, 0, Z)," & "47 (BC_4, PA7, observe_only, X )," & "48 (BC_1, *, control, 0 )," & "49 (BC_1, INT4, output3, X, 48, 0, Z)," & "50 (BC_4, INT4, observe_only, X )," & "51 (BC_1, *, control, 0 )," & "52 (BC_1, CLKOUT, output3, X, 51, 0, Z)," & "53 (BC_1, *, control, 0 )," & "54 (BC_1, nRESETOUT,output3, X, 53, 0, Z)," & "55 (BC_1, *, control, 0 )," & "56 (BC_1, PI0, output3, X, 55, 0, Z)," & "57 (BC_4, PI0, observe_only, X )," & "58 (BC_1, *, control, 0 )," & "59 (BC_1, PI1, output3, X, 58, 0, Z)," & "60 (BC_4, PI1, observe_only, X )," & "61 (BC_1, *, control, 0 )," & "62 (BC_1, PI2, output3, X, 61, 0, Z)," & "63 (BC_4, PI2, observe_only, X )," & "64 (BC_1, *, control, 0 )," & "65 (BC_1, PI3, output3, X, 64, 0, Z)," & "66 (BC_4, PI3, observe_only, X )," & "67 (BC_1, *, control, 0 )," & "68 (BC_1, PI4, output3, X, 67, 0, Z)," & "69 (BC_4, PI4, observe_only, X )," & "70 (BC_1, *, control, 0 )," & "71 (BC_1, PI5, output3, X, 70, 0, Z)," & "72 (BC_4, PI5, observe_only, X )," & "73 (BC_1, *, control, 0 )," & "74 (BC_1, PI6, output3, X, 73, 0, Z)," & "75 (BC_4, PI6, observe_only, X )," & "76 (BC_1, *, control, 0 )," & "77 (BC_1, PI7, output3, X, 76, 0, Z)," & "78 (BC_4, PI7, observe_only, X )," & "79 (BC_1, *, control, 0 )," & "80 (BC_1, PH0, output3, X, 79, 0, Z)," & "81 (BC_4, PH0, observe_only, X )," & "82 (BC_1, *, control, 0 )," & "83 (BC_1, PH1, output3, X, 82, 0, Z)," & "84 (BC_4, PH1, observe_only, X )," & "85 (BC_1, *, control, 0 )," & "86 (BC_1, PH2, output3, X, 85, 0, Z)," & "87 (BC_4, PH2, observe_only, X )," & "88 (BC_1, *, control, 0 )," & "89 (BC_1, PH3, output3, X, 88, 0, Z)," & "90 (BC_4, PH3, observe_only, X )," & "91 (BC_1, *, control, 0 )," & "92 (BC_1, PH4, output3, X, 91, 0, Z)," & "93 (BC_4, PH4, observe_only, X )," & "94 (BC_1, *, control, 0 )," & "95 (BC_1, PH5, output3, X, 94, 0, Z)," & "96 (BC_4, PH5, observe_only, X )," & "97 (BC_1, *, control, 0 )," & "98 (BC_1, PH6, output3, X, 97, 0, Z)," & "99 (BC_4, PH6, observe_only, X )," & "100 (BC_1, *, control, 0 )," & "101 (BC_1, PH7, output3, X, 100, 0, Z)," & "102 (BC_4, PH7, observe_only, X )," & "103 (BC_1, *, control, 0 )," & "104 (BC_1, PG0, output3, X, 103, 0, Z)," & "105 (BC_4, PG0, observe_only, X )," & "106 (BC_1, *, control, 0 )," & "107 (BC_1, PG1, output3, X, 106, 0, Z)," & "108 (BC_4, PG1, observe_only, X )," & "109 (BC_1, *, control, 0 )," & "110 (BC_1, PG2, output3, X, 109, 0, Z)," & "111 (BC_4, PG2, observe_only, X )," & "112 (BC_1, *, control, 0 )," & "113 (BC_1, PG3, output3, X, 112, 0, Z)," & "114 (BC_4, PG3, observe_only, X )," & "115 (BC_1, *, control, 0 )," & "116 (BC_1, PG4, output3, X, 115, 0, Z)," & "117 (BC_4, PG4, observe_only, X )," & "118 (BC_1, *, control, 0 )," & "119 (BC_1, PG5, output3, X, 118, 0, Z)," & "120 (BC_4, PG5, observe_only, X )," & "121 (BC_1, *, control, 0 )," & "122 (BC_1, PG6, output3, X, 121, 0, Z)," & "123 (BC_4, PG6, observe_only, X )," & "124 (BC_1, *, control, 0 )," & "125 (BC_1, PG7, output3, X, 124, 0, Z)," & "126 (BC_4, PG7, observe_only, X )," & "127 (BC_1, *, control, 0 )," & "128 (BC_1, PF0, output3, X, 127, 0, Z)," & "129 (BC_4, PF0, observe_only, X )," & "130 (BC_1, *, control, 0 )," & "131 (BC_1, PF1, output3, X, 130, 0, Z)," & "132 (BC_4, PF1, observe_only, X )," & "133 (BC_1, *, control, 0 )," & "134 (BC_1, PF2, output3, X, 133, 0, Z)," & "135 (BC_4, PF2, observe_only, X )," & "136 (BC_1, *, control, 0 )," & "137 (BC_1, PF3, output3, X, 136, 0, Z)," & "138 (BC_4, PF3, observe_only, X )," & "139 (BC_1, *, control, 0 )," & "140 (BC_1, PF4, output3, X, 139, 0, Z)," & "141 (BC_4, PF4, observe_only, X )," & "142 (BC_1, *, control, 0 )," & "143 (BC_1, PF5, output3, X, 142, 0, Z)," & "144 (BC_4, PF5, observe_only, X )," & "145 (BC_1, *, control, 0 )," & "146 (BC_1, PF6, output3, X, 145, 0, Z)," & "147 (BC_4, PF6, observe_only, X )," & "148 (BC_1, *, control, 0 )," & "149 (BC_1, PF7, output3, X, 148, 0, Z)," & "150 (BC_4, PF7, observe_only, X )," & "151 (BC_1, *, control, 0 )," & "152 (BC_1, PE0, output3, X, 151, 0, Z)," & "153 (BC_4, PE0, observe_only, X )," & "154 (BC_1, *, control, 0 )," & "155 (BC_1, PE1, output3, X, 154, 0, Z)," & "156 (BC_4, PE1, observe_only, X )," & "157 (BC_1, *, control, 0 )," & "158 (BC_1, PE2, output3, X, 157, 0, Z)," & "159 (BC_4, PE2, observe_only, X )," & "160 (BC_1, *, control, 0 )," & "161 (BC_1, PE3, output3, X, 160, 0, Z)," & "162 (BC_4, PE3, observe_only, X )," & "163 (BC_1, *, control, 0 )," & "164 (BC_1, PE4, output3, X, 163, 0, Z)," & "165 (BC_4, PE4, observe_only, X )," & "166 (BC_1, *, control, 0 )," & "167 (BC_1, PE5, output3, X, 166, 0, Z)," & "168 (BC_4, PE5, observe_only, X )," & "169 (BC_1, *, control, 0 )," & "170 (BC_1, PE6, output3, X, 169, 0, Z)," & "171 (BC_4, PE6, observe_only, X )," & "172 (BC_1, *, control, 0 )," & "173 (BC_1, PE7, output3, X, 172, 0, Z)," & "174 (BC_4, PE7, observe_only, X )," & "175 (BC_1, *, control, 0 )," & "176 (BC_1, DQM0, output3, X, 175, 0, Z)," & "177 (BC_1, *, control, 0 )," & "178 (BC_1, DQM1, output3, X, 177, 0, Z)," & "179 (BC_1, *, control, 0 )," & "180 (BC_1, SDCLK, output3, X, 179, 0, Z)," & "181 (BC_4, SDCLK, observe_only, X )," & "182 (BC_1, *, control, 0 )," & "183 (BC_1, SDCKE, output3, X, 182, 0, Z)," & "184 (BC_1, *, control, 0 )," & "185 (BC_1, nDCS0, output3, X, 184, 0, Z)," & "186 (BC_1, *, control, 0 )," & "187 (BC_1, nDCS1, output3, X, 186, 0, Z)," & "188 (BC_1, *, control, 0 )," & "189 (BC_1, nRAS, output3, X, 188, 0, Z)," & "190 (BC_1, *, control, 0 )," & "191 (BC_1, nCAS, output3, X, 190, 0, Z)," & "192 (BC_1, *, control, 0 )," & "193 (BC_1, nWE, output3, X, 192, 0, Z)," & "194 (BC_1, *, control, 0 )," & "195 (BC_1, nBLE0, output3, X, 194, 0, Z)," & "196 (BC_4, nBLE0, observe_only, X )," & "197 (BC_1, *, control, 0 )," & "198 (BC_1, nBLE1, output3, X, 197, 0, Z)," & "199 (BC_1, *, control, 0 )," & "200 (BC_1, nOE, output3, X, 199, 0, Z)," & "201 (BC_1, *, control, 0 )," & "202 (BC_1, nCS0, output3, X, 201, 0, Z)," & "203 (BC_1, *, control, 0 )," & "204 (BC_1, nCS1, output3, X, 203, 0, Z)," & "205 (BC_1, *, control, 0 )," & "206 (BC_1, nCS2, output3, X, 205, 0, Z)," & "207 (BC_1, *, control, 0 )," & "208 (BC_1, nCS3, output3, X, 207, 0, Z)," & "209 (BC_1, *, control, 0 )," & "210 (BC_1, D0, output3, X, 209, 0, Z)," & "211 (BC_4, D0, observe_only, X )," & "212 (BC_1, *, control, 0 )," & "213 (BC_1, D1, output3, X, 212, 0, Z)," & "214 (BC_4, D1, observe_only, X )," & "215 (BC_1, *, control, 0 )," & "216 (BC_1, D2, output3, X, 215, 0, Z)," & "217 (BC_4, D2, observe_only, X )," & "218 (BC_1, *, control, 0 )," & "219 (BC_1, D3, output3, X, 218, 0, Z)," & "220 (BC_4, D3, observe_only, X )," & "221 (BC_1, *, control, 0 )," & "222 (BC_1, D4, output3, X, 221, 0, Z)," & "223 (BC_4, D4, observe_only, X )," & "224 (BC_1, *, control, 0 )," & "225 (BC_1, D5, output3, X, 224, 0, Z)," & "226 (BC_4, D5, observe_only, X )," & "227 (BC_1, *, control, 0 )," & "228 (BC_1, D6, output3, X, 227, 0, Z)," & "229 (BC_4, D6, observe_only, X )," & "230 (BC_1, *, control, 0 )," & "231 (BC_1, D7, output3, X, 230, 0, Z)," & "232 (BC_4, D7, observe_only, X )," & "233 (BC_1, *, control, 0 )," & "234 (BC_1, PD0, output3, X, 233, 0, Z)," & "235 (BC_4, PD0, observe_only, X )," & "236 (BC_1, *, control, 0 )," & "237 (BC_1, PD1, output3, X, 236, 0, Z)," & "238 (BC_4, PD1, observe_only, X )," & "239 (BC_1, *, control, 0 )," & "240 (BC_1, PD2, output3, X, 239, 0, Z)," & "241 (BC_4, PD2, observe_only, X )," & "242 (BC_1, *, control, 0 )," & "243 (BC_1, PD3, output3, X, 242, 0, Z)," & "244 (BC_4, PD3, observe_only, X )," & "245 (BC_1, *, control, 0 )," & "246 (BC_1, PD4, output3, X, 245, 0, Z)," & "247 (BC_4, PD4, observe_only, X )," & "248 (BC_1, *, control, 0 )," & "249 (BC_1, PD5, output3, X, 248, 0, Z)," & "250 (BC_4, PD5, observe_only, X )," & "251 (BC_1, *, control, 0 )," & "252 (BC_1, PD6, output3, X, 251, 0, Z)," & "253 (BC_4, PD6, observe_only, X )," & "254 (BC_1, *, control, 0 )," & "255 (BC_1, PD7, output3, X, 254, 0, Z)," & "256 (BC_4, PD7, observe_only, X )," & "257 (BC_1, *, control, 0 )," & "258 (BC_1, A0, output3, X, 257, 0, Z)," & "259 (BC_1, *, control, 0 )," & "260 (BC_1, A1, output3, X, 259, 0, Z)," & "261 (BC_1, *, control, 0 )," & "262 (BC_1, A2, output3, X, 261, 0, Z)," & "263 (BC_1, *, control, 0 )," & "264 (BC_1, A3, output3, X, 263, 0, Z)," & "265 (BC_1, *, control, 0 )," & "266 (BC_1, A4, output3, X, 265, 0, Z)," & "267 (BC_1, *, control, 0 )," & "268 (BC_1, A5, output3, X, 267, 0, Z)," & "269 (BC_1, *, control, 0 )," & "270 (BC_1, A6, output3, X, 269, 0, Z)," & "271 (BC_1, *, control, 0 )," & "272 (BC_1, A7, output3, X, 271, 0, Z)," & "273 (BC_1, *, control, 0 )," & "274 (BC_1, A8, output3, X, 273, 0, Z)," & "275 (BC_1, *, control, 0 )," & "276 (BC_1, A9, output3, X, 275, 0, Z)," & "277 (BC_1, *, control, 0 )," & "278 (BC_1, A10, output3, X, 277, 0, Z)," & "279 (BC_1, *, control, 0 )," & "280 (BC_1, A11, output3, X, 279, 0, Z)," & "281 (BC_1, *, control, 0 )," & "282 (BC_1, A12, output3, X, 281, 0, Z)," & "283 (BC_1, *, control, 0 )," & "284 (BC_1, A13, output3, X, 283, 0, Z)," & "285 (BC_1, *, control, 0 )," & "286 (BC_1, A14, output3, X, 285, 0, Z)," & "287 (BC_1, *, control, 0 )," & "288 (BC_1, A15, output3, X, 287, 0, Z)," & "289 (BC_1, *, control, 0 )," & "290 (BC_1, PC0, output3, X, 289, 0, Z)," & "291 (BC_4, PC0, observe_only, X )," & "292 (BC_1, *, control, 0 )," & "293 (BC_1, PC1, output3, X, 292, 0, Z)," & "294 (BC_4, PC1, observe_only, X )," & "295 (BC_1, *, control, 0 )," & "296 (BC_1, PC2, output3, X, 295, 0, Z)," & "297 (BC_4, PC2, observe_only, X )," & "298 (BC_1, *, control, 0 )," & "299 (BC_1, PC3, output3, X, 298, 0, Z)," & "300 (BC_4, PC3, observe_only, X )," & "301 (BC_1, *, control, 0 )," & "302 (BC_1, PC4, output3, X, 301, 0, Z)," & "303 (BC_4, PC4, observe_only, X )," & "304 (BC_1, *, control, 0 )," & "305 (BC_1, PC5, output3, X, 304, 0, Z)," & "306 (BC_4, PC5, observe_only, X )," & "307 (BC_1, *, control, 0 )," & "308 (BC_1, PC6, output3, X, 307, 0, Z)," & "309 (BC_4, PC6, observe_only, X )," & "310 (BC_1, *, control, 0 )," & "311 (BC_1, PC7, output3, X, 310, 0, Z)," & "312 (BC_4, PC7, observe_only, X )"; end LH79525;