-- Copyright Intel Corporation 1999 --**************************************************************************** -- Intel Corporation makes no warranty for the use of its products -- and assumes no responsibility for any errors which may appear in -- this document nor does it make a commitment to update the information -- contained herein. --**************************************************************************** -- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1990 -- compliant devices. This language is under consideration by the IEEE for -- formal inclusion within a supplement to the 1149.1-1990 standard. The -- generation of the supplement entails an extensive IEEE review and a formal -- acceptance balloting procedure which may cP2Pnge the resultant form of the -- language. Be aware tP2Pt this process may extend well into 1993, and at -- this time the IEEE does not endorse or hold an opinion on the language. --**************************************************************************** -- -- i960 (TM) Processor BSDL Model -- Project code P2P -- File **NOT** verified electrically -- --------------------------------------------------------- -- Rev 0.0 14 Nov 1995 -- Rev 1.0 14 APR 1998 -- added lcdinitz, entity VH_Processor is generic(PHYSICAL_PIN_MAP : string:= "BGA"); port (AD : inout bit_vector(0 to 31); ADSBAR : out bit; ALE : out bit; BEBAR : out bit_vector(0 to 3); BLASTEBMBAR : inout bit; CASBAR : out bit_vector(0 to 7); CEBAR : out bit_vector(0 to 1); CLKMODE0BAR : in bit; CLKMODE1BAR : in bit; DACKBAR_PLLEN : inout bit; DALE : out bit_vector(0 to 1); DCRST_MODEBAR : inout bit; DENBIBAR : inout bit; DP : inout bit_vector(0 to 3); DREQBAR : in bit; DTRBAR : out bit; DWEBAR : out bit_vector(0 to 1); FAILBAR : out bit; HOLD : in bit; HOLDA : out bit; LCDINITZ : in bit; LEAFBAR : out bit_vector(0 to 1); LOCKONCEBAR : inout bit; LRDYRCVBAR_STEST : inout bit; LRSTBAR : out bit; MA : out bit_vector(0 to 11); MWEBAR : out bit_vector(0 to 3); NC : linkage bit_vector(0 to 31); NMIBAR : in bit; P_AD : inout bit_vector(0 to 31); P_CLK : in bit; P_CXBE_BAR : inout bit_vector(0 to 3); P_DEVSEL_BAR : inout bit; P_FRAME_BAR : inout bit; P_GNT_BAR : in bit; P_IDSEL : in bit; P_INTA_BAR : out bit; P_INTB_BAR : out bit; P_INTC_BAR : out bit; P_INTD_BAR : out bit; P_IRDY_BAR : inout bit; P_LOCK_BAR : in bit; P_PAR : inout bit; P_PERR_BAR : inout bit; P_REQ_BAR : out bit; P_RST_BAR : in bit; P_SERR_BAR : inout bit; P_STOP_BAR : inout bit; P_TRDY_BAR : inout bit; RASBAR : out bit_vector(0 to 3); RDYRCVBAR : in bit; SCL : inout bit; SDA : inout bit; TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TRSTBAR : in bit; WAITBAR : out bit; WIDTHHLTD0SYNC : inout bit; WIDTHHLTD1RETRY: inout bit; WRBAR : out bit; XINTBAR : in bit_vector(0 to 5); XINTBAR6 : in bit; XINTBAR7 : in bit; VCC : linkage bit_vector(0 to 59); VCCPLL : linkage bit_vector(0 to 1); VCC3 : linkage bit_vector(0 to 2); REFVCCP5 : linkage bit; VSS : linkage bit_vector(0 to 57) ); use STD_1149_1_1990.all; use i960P2P_a.all; attribute PIN_MAP of VH_Processor : entity is PHYSICAL_PIN_MAP; constant BGA:PIN_MAP_STRING := "AD : (V11, Y11, V12, W12, Y12, V13, T13, Y13, V14, U14,"& " Y16, W17, V16, V17, V18, Y18, Y19, T17, U18, V19,"& " T18, V20, P17, R18, T19, U20, M16, P18, T20, P19,"& " N18, L16),"& "ADSBAR : J16,"& "ALE : L18,"& "BEBAR : (K16, M19, M18, M17),"& "BLASTEBMBAR : J17,"& "CASBAR : (U1, T2, R3, P4, T1, N5, P3, P1),"& "CEBAR : (L5, L3),"& "CLKMODE0BAR : C2,"& "CLKMODE1BAR : D3,"& "DACKBAR_PLLEN : C3,"& "DALE : (K3, K5),"& "DCRST_MODEBAR : T9,"& "DENBIBAR : L20,"& "DP : (E2, D1, E3, C1),"& "DREQBAR : B1,"& "DTRBAR : K18,"& "DWEBAR : (M2, M1),"& "FAILBAR : T8,"& "HOLD : Y8,"& "HOLDA : V9,"& "LCDINITZ : Y7,"& "LEAFBAR : (L1, K1),"& "LOCKONCEBAR : V8,"& "LRDYRCVBAR_STEST: Y9,"& "LRSTBAR : W5,"& "MA : (J1, J2, J3, J4, H3, G2, F1, G3, H5, E1,"& " G4, F3),"& "MWEBAR : (N3, M5, M4, M3),"& "NC : (C9, D9, D20, E5, E6, E7, E8, E9, E14, E15,"& " E16, E17, E18, E19, F5, F16, G1, G5, G16,"& " N16, P5, P16, R5, R16, T5, T6, T11, T16, V7,"& " W1, W16, Y17),"& "NMIBAR : W9,"& "P_AD : (B3, C4, D5, A3, C5, B5, C6, D7, C7, B7,"& " A7, C8, B9, A9, A10, C10, C14, A16, D14, E13,"& " C15, B16, A17, C16, B18, C17, D16, C18, B20,C19,"& " D18, E20),"& "P_CLK : W20,"& "P_CXBE_BAR : (A5, E10, B14, A19),"& "P_DEVSEL_BAR : C12,"& "P_FRAME_BAR : E12,"& "P_GNT_BAR : F20,"& "P_IDSEL : A18,"& "P_INTA_BAR : J20,"& "P_INTB_BAR : H18,"& "P_INTC_BAR : H16,"& "P_INTD_BAR : G18,"& "P_IRDY_BAR : C13,"& "P_LOCK_BAR : B12,"& "P_PAR : A11,"& "P_PERR_BAR : A12,"& "P_REQ_BAR : F18,"& "P_RST_BAR : G17,"& "P_SERR_BAR : C11,"& "P_STOP_BAR : E11,"& "P_TRDY_BAR : A14,"& "RASBAR : (T4, U3, V1, T3),"& "RDYRCVBAR : T10,"& "SCL : J19,"& "SDA : J18,"& "TCK : T14,"& "TDI : T15,"& "TDO : V10,"& "TMS : V15,"& "TRSTBAR : Y14,"& "WAITBAR : A2,"& "WIDTHHLTD0SYNC : U7,"& "WIDTHHLTD1RETRY: V6,"& "WRBAR : K20,"& "XINTBAR : (T7, Y4, V5, Y3, V4, Y2),"& "XINTBAR6 : V3,"& "XINTBAR7 : V2,"& "VCC : (A8, A13, B4, B8, B13, B17, D2, D6, D10, D11, D15,"& " D19, F4, F6, F14, F15, F17, G6, H1, H2, H19, H20, K4,"& " K17, L4, L17, N1, N2, N19, N20, P15, R4, R6, R7, R15,"& " R17, U2, U6, U10, U11, U15, U19, W4, W8, W13, Y5, A4,"& " D12, G19, J5, M20, P2, U5, U9, U12, U16, W3, W7, W14,"& " W18),"& "VCCPLL : (Y10, G20),"& "VCC3 : (C20, E4, T12),"& "REFVCCP5 : P20,"& "VSS : (A1, A6, A15, A20, B2, B6, B10, B11, B15, B19,"& " D4, D8, D13, D17, F2, F19, H4, H17, J9, J10,"& " J11, J12, K2, K9, K10, K11, K12, K19, L2, L9,"& " L10, L11, L12, L19, M9, M10, M11, M12, N4, N17,"& " R1, R2, R19, R20, U4, U8, U13, U17, W2, W6, W10,"& " W11, W15, W19, Y1, Y6, Y15, Y20)"; attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Reset of TRSTBAR : signal is true; attribute Tap_Scan_Clock of TCK : signal is (16.0e6, BOTH); attribute Instruction_Length of VH_Processor: entity is 4; attribute Instruction_Opcode of VH_Processor: entity is "BYPASS (1111)," & "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "RUBIST (0111)," & "CLAMP (0100)," & "HIGHZ (1000)," & "Reserved (1011, 1100, 0101, 0110)"; attribute Instruction_Capture of VH_Processor: entity is "0001"; attribute Instruction_Private of VH_Processor: entity is "Reserved" ; attribute Idcode_Register of VH_Processor: entity is --0x08864013 "0000" & --version, "1000100001100100" & --part number "00000001001" & --manufacturers identity "1"; --required by the standard attribute Register_Access of VH_Processor: entity is "Runbist[1] (RUBIST)," & "Bypass (CLAMP, HIGHZ)"; --{*******************************************************************} --{ The first cell, cell 0, is closest to TDO } --{ BC_1:Control, Output3 BC_4: Input, Clock } --{ CBSC_1: Bidirectional, CBSC_2: Bidirectional_in, CBSC_3: Bidirectional_out } --{*******************************************************************} attribute Boundary_Cells of VH_Processor: entity is "BC_4, BC_1, CBSC_1, CBSC_2, CBSC_3"; attribute Boundary_Length of VH_Processor: entity is 192; attribute Boundary_Register of VH_Processor: entity is -- # cell name function safe bit control disable disable -- type signal value result "0 (CBSC_1, LRDYRCVBAR_STEST, bidir, X, 19, 1, Z)," & "1 (BC_4, RDYRCVBAR, input, X)," & "2 (BC_1, *, control, 1)," & "3 (BC_4, NMIBAR, input, X)," & "4 (BC_1, HOLDA, output3, X, 20, 1, Z)," & "5 (BC_4, HOLD, input, X)," & "6 (BC_4, LCDINITZ, input, X)," & "7 (CBSC_1, LOCKONCEBAR, bidir, X, 21, 1, Z)," & "8 (CBSC_1, DCRST_MODEBAR, bidir, X, 21, 1, Z)," & "9 (BC_1, FAILBAR, output3, X, 20, 1, Z)," & "10 (CBSC_1, WIDTHHLTD0SYNC, bidir, X, 21, 1, Z)," & "11 (CBSC_1, WIDTHHLTD1RETRY,bidir, X, 21, 1, Z)," & "12 (BC_1, LRSTBAR, output3, X, 20, 1, Z)," & "13 (BC_4, XINTBAR(0), input, X)," & "14 (BC_4, XINTBAR(1), input, X)," & "15 (BC_4, XINTBAR(2), input, X)," & "16 (BC_4, XINTBAR(3), input, X)," & "17 (BC_4, XINTBAR(4), input, X)," & "18 (BC_4, XINTBAR(5), input, X)," & "19 (BC_1, *, control, 1)," & "20 (BC_1, *, control, 1)," & "21 (BC_1, *, control, 1)," & "22 (BC_4, XINTBAR6, input, X)," & "23 (BC_4, XINTBAR7, input, X)," & "24 (BC_1, RASBAR(0), output3, X, 48, 1, Z)," & "25 (BC_1, RASBAR(1), output3, X, 48, 1, Z)," & "26 (BC_1, RASBAR(2), output3, X, 48, 1, Z)," & "27 (BC_1, RASBAR(3), output3, X, 48, 1, Z)," & "28 (BC_1, CASBAR(0), output3, X, 48, 1, Z)," & "29 (BC_1, CASBAR(1), output3, X, 48, 1, Z)," & "30 (BC_1, CASBAR(2), output3, X, 48, 1, Z)," & "31 (BC_1, CASBAR(3), output3, X, 48, 1, Z)," & "32 (BC_1, CASBAR(4), output3, X, 48, 1, Z)," & "33 (BC_1, CASBAR(5), output3, X, 48, 1, Z)," & "34 (BC_1, CASBAR(6), output3, X, 48, 1, Z)," & "35 (BC_1, CASBAR(7), output3, X, 48, 1, Z)," & "36 (BC_1, MWEBAR(0), output3, X, 48, 1, Z)," & "37 (BC_1, MWEBAR(1), output3, X, 48, 1, Z)," & "38 (BC_1, MWEBAR(2), output3, X, 48, 1, Z)," & "39 (BC_1, MWEBAR(3), output3, X, 48, 1, Z)," & "40 (BC_1, DWEBAR(0), output3, X, 48, 1, Z)," & "41 (BC_1, DWEBAR(1), output3, X, 48, 1, Z)," & "42 (BC_1, CEBAR(0), output3, X, 48, 1, Z)," & "43 (BC_1, CEBAR(1), output3, X, 48, 1, Z)," & "44 (BC_1, LEAFBAR(0), output3, X, 48, 1, Z)," & "45 (BC_1, LEAFBAR(1), output3, X, 48, 1, Z)," & "46 (BC_1, DALE(0), output3, X, 48, 1, Z)," & "47 (BC_1, DALE(1), output3, X, 48, 1, Z)," & "48 (BC_1, *, control, 1)," & "49 (BC_1, MA(0), output3, X, 48, 1, Z)," & "50 (BC_1, MA(1), output3, X, 48, 1, Z)," & "51 (BC_1, MA(2), output3, X, 48, 1, Z)," & "52 (BC_1, MA(3), output3, X, 48, 1, Z)," & "53 (BC_1, MA(4), output3, X, 48, 1, Z)," & "54 (BC_1, MA(5), output3, X, 48, 1, Z)," & "55 (BC_1, MA(6), output3, X, 48, 1, Z)," & "56 (BC_1, MA(7), output3, X, 48, 1, Z)," & "57 (BC_1, MA(8), output3, X, 48, 1, Z)," & "58 (BC_1, MA(9), output3, X, 48, 1, Z)," & "59 (BC_1, MA(10), output3, X, 48, 1, Z)," & "60 (BC_1, MA(11), output3, X, 48, 1, Z)," & "61 (CBSC_1, DP(0), bidir, X, 63, 1, Z)," & "62 (CBSC_1, DP(1), bidir, X, 63, 1, Z)," & "63 (BC_1, *, control, 1)," & "64 (CBSC_1, DP(2), bidir, X, 63, 1, Z)," & "65 (CBSC_1, DP(3), bidir, X, 63, 1, Z)," & "66 (BC_4, CLKMODE0BAR, input, X)," & "67 (BC_4, CLKMODE1BAR, input, X)," & "68 (BC_4, DREQBAR, input, X)," & "69 (CBSC_1, DACKBAR_PLLEN, bidir, X, 71, 1, Z)," & "70 (BC_1, WAITBAR, output3, X, 72, 1, Z)," & "71 (BC_1, *, control, 1)," & "72 (BC_1, *, control, 1)," & "73 (CBSC_1, P_AD(0), bidir, X, 87, 1, Z)," & "74 (CBSC_1, P_AD(1), bidir, X, 87, 1, Z)," & "75 (CBSC_1, P_AD(2), bidir, X, 87, 1, Z)," & "76 (CBSC_1, P_AD(3), bidir, X, 87, 1, Z)," & "77 (CBSC_1, P_AD(4), bidir, X, 87, 1, Z)," & "78 (CBSC_1, P_AD(5), bidir, X, 87, 1, Z)," & "79 (CBSC_1, P_AD(6), bidir, X, 87, 1, Z)," & "80 (CBSC_1, P_AD(7), bidir, X, 87, 1, Z)," & "81 (CBSC_1, P_CXBE_BAR(0), bidir, X, 108, 1, Z)," & "82 (CBSC_1, P_AD(8), bidir, X, 87, 1, Z)," & "83 (CBSC_1, P_AD(9), bidir, X, 87, 1, Z)," & "84 (CBSC_1, P_AD(10), bidir, X, 87, 1, Z)," & "85 (CBSC_1, P_AD(11), bidir, X, 87, 1, Z)," & "86 (CBSC_1, P_AD(12), bidir, X, 87, 1, Z)," & "87 (BC_1, *, control, 1)," & "88 (CBSC_1, P_AD(13), bidir, X, 87, 1, Z)," & "89 (CBSC_1, P_AD(14), bidir, X, 87, 1, Z)," & "90 (CBSC_1, P_AD(15), bidir, X, 87, 1, Z)," & "91 (CBSC_1, P_CXBE_BAR(1), bidir, X, 108, 1, Z)," & "92 (CBSC_1, P_PAR, bidir, X, 95, 1, Z)," & "93 (BC_1, *, control, 1)," & "94 (BC_1, *, control, 1)," & "95 (BC_1, *, control, 1)," & "96 (CBSC_1, P_SERR_BAR, bidir, X, 94, 1, Z)," & "97 (CBSC_1, P_PERR_BAR, bidir, X, 93, 1, Z)," & "98 (BC_4, P_LOCK_BAR, input, X)," & "99 (CBSC_1, P_STOP_BAR, bidir, X, 101, 1, Z)," & "100 (CBSC_1, P_DEVSEL_BAR, bidir, X, 101, 1, Z)," & "101 (BC_1, *, control, 1)," & "102 (BC_1, *, control, 1)," & "103 (CBSC_1, P_TRDY_BAR, bidir, X, 101, 1, Z)," & "104 (CBSC_1, P_IRDY_BAR, bidir, X, 102, 1, Z)," & "105 (CBSC_1, P_FRAME_BAR, bidir, X, 107, 1, Z)," & "106 (CBSC_1, P_CXBE_BAR(2), bidir, X, 108, 1, Z)," & "107 (BC_1, *, control, 1)," & "108 (BC_1, *, control, 1)," & "109 (CBSC_1, P_AD(16), bidir, X, 119, 1, Z)," & "110 (CBSC_1, P_AD(17), bidir, X, 119, 1, Z)," & "111 (CBSC_1, P_AD(18), bidir, X, 119, 1, Z)," & "112 (CBSC_1, P_AD(19), bidir, X, 119, 1, Z)," & "113 (CBSC_1, P_AD(20), bidir, X, 119, 1, Z)," & "114 (CBSC_1, P_AD(21), bidir, X, 119, 1, Z)," & "115 (CBSC_1, P_AD(22), bidir, X, 119, 1, Z)," & "116 (CBSC_1, P_AD(23), bidir, X, 119, 1, Z)," & "117 (BC_4, P_IDSEL, input, X)," & "118 (CBSC_1, P_CXBE_BAR(3), bidir, X, 108, 1, Z)," & "119 (BC_1, *, control, 1)," & "120 (CBSC_1, P_AD(24), bidir, X, 119, 1, Z)," & "121 (CBSC_1, P_AD(25), bidir, X, 119, 1, Z)," & "122 (CBSC_1, P_AD(26), bidir, X, 119, 1, Z)," & "123 (CBSC_1, P_AD(27), bidir, X, 119, 1, Z)," & "124 (CBSC_1, P_AD(28), bidir, X, 119, 1, Z)," & "125 (BC_1, *, control, 1)," & "126 (CBSC_1, P_AD(29), bidir, X, 125, 1, Z)," & "127 (CBSC_1, P_AD(30), bidir, X, 125, 1, Z)," & "128 (CBSC_1, P_AD(31), bidir, X, 125, 1, Z)," & "129 (BC_1, P_REQ_BAR, output3, X, 131, 1, Z)," & "130 (BC_4, P_GNT_BAR, input, X)," & "131 (BC_1, *, control, 1)," & "132 (BC_1, *, control, 1)," & "133 (BC_1, *, control, 1)," & "134 (BC_1, *, control, 1)," & "135 (BC_1, *, control, 1)," & "136 (BC_4, P_RST_BAR, input, X)," & "137 (BC_1, P_INTD_BAR, output3, X, 132, 1, Z)," & "138 (BC_1, P_INTC_BAR, output3, X, 133, 1, Z)," & "139 (BC_1, P_INTB_BAR, output3, X, 134, 1, Z)," & "140 (BC_1, P_INTA_BAR, output3, X, 135, 1, Z)," & "141 (CBSC_1, SCL, bidir, X, 143, 1, Z)," & "142 (CBSC_1, SDA, bidir, X, 144, 1, Z)," & "143 (BC_1, *, control, 1)," & "144 (BC_1, *, control, 1)," & "145 (CBSC_1, BLASTEBMBAR, bidir, X, 153, 1, Z)," & "146 (BC_1, ADSBAR, output3, X, 154, 1, Z)," & "147 (BC_1, WRBAR, output3, X, 154, 1, Z)," & "148 (BC_1, DTRBAR, output3, X, 154, 1, Z)," & "149 (CBSC_1, DENBIBAR, bidir, X, 153, 1, Z)," & "150 (BC_1, ALE, output3, X, 154, 1, Z)," & "151 (BC_1, BEBAR(0), output3, X, 154, 1, Z)," & "152 (BC_1, BEBAR(1), output3, X, 154, 1, Z)," & "153 (BC_1, *, control, 1)," & "154 (BC_1, *, control, 1)," & "155 (BC_1, BEBAR(2), output3, X, 154, 1, Z)," & "156 (BC_1, BEBAR(3), output3, X, 154, 1, Z)," & "157 (CBSC_1, AD(31), bidir, X, 172, 1, Z)," & "158 (CBSC_1, AD(30), bidir, X, 172, 1, Z)," & "159 (CBSC_1, AD(29), bidir, X, 172, 1, Z)," & "160 (CBSC_1, AD(28), bidir, X, 172, 1, Z)," & "161 (CBSC_1, AD(27), bidir, X, 172, 1, Z)," & "162 (CBSC_1, AD(26), bidir, X, 172, 1, Z)," & "163 (CBSC_1, AD(25), bidir, X, 172, 1, Z)," & "164 (CBSC_1, AD(24), bidir, X, 172, 1, Z)," & "165 (CBSC_1, AD(23), bidir, X, 172, 1, Z)," & "166 (CBSC_1, AD(22), bidir, X, 172, 1, Z)," & "167 (CBSC_1, AD(21), bidir, X, 172, 1, Z)," & "168 (CBSC_1, AD(20), bidir, X, 172, 1, Z)," & "169 (CBSC_1, AD(19), bidir, X, 172, 1, Z)," & "170 (BC_4, P_CLK, input, X)," & "171 (CBSC_1, AD(18), bidir, X, 172, 1, Z)," & "172 (BC_1, *, control, 1)," & "173 (CBSC_1, AD(17), bidir, X, 172, 1, Z)," & "174 (CBSC_1, AD(16), bidir, X, 172, 1, Z)," & "175 (CBSC_1, AD(15), bidir, X, 172, 1, Z)," & "176 (CBSC_1, AD(14), bidir, X, 172, 1, Z)," & "177 (CBSC_1, AD(13), bidir, X, 172, 1, Z)," & "178 (CBSC_1, AD(12), bidir, X, 172, 1, Z)," & "179 (CBSC_1, AD(11), bidir, X, 172, 1, Z)," & "180 (CBSC_1, AD(10), bidir, X, 172, 1, Z)," & "181 (CBSC_1, AD(9), bidir, X, 186, 1, Z)," & "182 (CBSC_1, AD(8), bidir, X, 186, 1, Z)," & "183 (CBSC_1, AD(7), bidir, X, 186, 1, Z)," & "184 (CBSC_1, AD(6), bidir, X, 186, 1, Z)," & "185 (CBSC_1, AD(5), bidir, X, 186, 1, Z)," & "186 (BC_1, *, control, 1)," & "187 (CBSC_1, AD(4), bidir, X, 186, 1, Z)," & "188 (CBSC_1, AD(3), bidir, X, 186, 1, Z)," & "189 (CBSC_1, AD(2), bidir, X, 186, 1, Z)," & "190 (CBSC_1, AD(1), bidir, X, 186, 1, Z)," & "191 (CBSC_1, AD(0), bidir, X, 186, 1, Z)"; end VH_Processor;