-- -- Intel Pentium(R) 75/90/100/120/133/150/166/200 Processor BSDL File -- compiled together from the datasheets, tested on a Pentium 90 -- Created: November 2015 by Matt Goring -- entity Pentium_P54C is generic(PHYSICAL_PIN_MAP: string := "SPGA_296"); -- Staggered PGA Socket 5/7 (296/320) port( A20M : in bit; -- address bit 20 mask A : inout bit_vector(31 downto 3); -- Address bus ADS : inout bit; -- address status ADSC : inout bit; -- address status AHOLD : in bit; -- address hold AP : inout bit; -- Address parity APCHK : inout bit; -- address parity check -- APICEN : in bit; -- [PICD1] Advanced Programmable Interrupt Controller Enable BE : inout bit_vector(7 downto 0); -- byte enable BF : in bit_vector(1 downto 0); -- Bus Frequency BOFF : in bit; -- backoff BP : inout bit_vector(3 downto 0); -- breakpoint, [PM]1:0 = performance monitoring BRDY : in bit; -- burst ready BRDYC : in bit; -- burst ready BREQ : inout bit; -- bus request BUSCHK : in bit; -- bus check CACHE : inout bit; -- cache CLK : in bit; -- BCLK, main clock CPUTYP : in bit; -- CPU type D_C : inout bit; -- data/code D_P : inout bit; -- dual/primary D : inout bit_vector(63 downto 0); -- data lines DP : inout bit_vector(7 downto 0); -- data parity -- DPEN : inout bit; -- [PICD0] Dual processing enable EADS : in bit; -- external address EWBE : in bit; -- external write buffer empty FERR : inout bit; -- floating point error FLUSH : in bit; -- cache flush FRCMC : in bit; -- functional redundancy checking HIT : inout bit; -- hit HITM : inout bit; -- hit to a modified line HLDA : inout bit; -- bus hold acknowledge HOLD : in bit; -- bus hold request IERR : inout bit; -- internal error IGNNE : in bit; -- ignore numeric error INIT : in bit; -- initialization INV : in bit; -- invalidation KEN : in bit; -- cache enable LINT0INTR : in bit; -- maskable interrupt / local interrupt 0 LINT1NMI : in bit; -- non-maskable interrupt / local interrupt 1 LOCK : inout bit; -- bus lock M_IO : inout bit; -- memory/input-output NA : in bit; -- next address PBGNT : inout bit; -- Private bus grant PBREQ : inout bit; -- Private bus request PCD : inout bit; -- page cache disable PCHK : inout bit; -- parity check PEN : in bit; -- parity enable PHIT : inout bit; -- Private hit PHITM : inout bit; -- Private modified hit PICCLK : in bit; -- programmable interrupt controller clock PICD : inout bit_vector(0 to 1); -- [APICEN] [DPEN] Programmable interrupt controller data lines -- PM_BP : out bit_vector(1 downto 0); -- [BP] performance monitoring PRDY : inout bit; -- probe ready PWT : inout bit; -- page write through R_S : in bit; -- run/stop RESET : in bit; -- RESET SCYC : inout bit; -- split cycle SMI : in bit; -- system management interrupt SMIACT : inout bit; -- system management interrupt active STPCLK : in bit; -- stop clock TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TRST : in bit; W_R : inout bit; -- Write/read WB_WT : in bit; -- write back/write through NC : linkage bit_vector(1 to 15); -- NO CONNECTS VCC : linkage bit_vector(1 to 53); -- VCC 3.3V VSS : linkage bit_vector(1 to 53) -- GND or VSS ); use STD_1149_1_1994.all; attribute PIN_MAP of Pentium_P54C : entity is PHYSICAL_PIN_MAP; constant SPGA_296 : PIN_MAP_STRING := "A20M : AK8, " & "A : (AJ33, AM36, AK34, AK36, AG33, AH34, AJ35, AG35, AE33, AH36, AF34, AL21, AK22, AL23, " & " AK24, AL25, AK26, AL27, AK28, AL29, AL31, AN31, AK30, AM32, AL33, AN33, AK32, AM34, AL35), " & "ADS : AJ5, " & "ADSC : AM2, " & "AHOLD : V4, " & "AP : AK2, " & "APCHK : AE5, " & "BE : (AK16, AL15, AK14, AL13, AK12, AL11, AK10, AL9), " & -- out (7 - 5) inout (4 - 0) "BF : (X34, Y33), " & "BOFF : Z4, " & "BP : (S5, S3, R4, Q3), " & "BRDY : X4, " & "BRDYC : Y3, " & "BREQ : AJ1, " & "BUSCHK : AL7, " & "CACHE : U3, " & "CLK : AK18, " & "CPUTYP : Q35, " & "D_C : AK4, " & "D_P : AE35, " & "D : ( N3, M4, L3, L5, K4, J5, J3, H4, " & -- 63 to 0 " G3, E1, G5, E3, F4, D2, E5, D4, " & " C3, E7, C5, D6, B4, E9, A5, D8, " & " D10, C9, D12, C11, D14, C13, D16, C15, " & " C17, D20, C19, D22, C21, D24, C23, C27, " & " D26, A31, C29, B30, D28, A33, C31, B32, " & " A35, C33, B34, D32, B36, C35, C37, D34, " & " E33, E35, F34, F36, G33, J35, G35, K34), " & "DP : (N5, F2, F6, C7, D18, C25, D30, D36), " & "EADS : AM4, " & "EWBE : W3, " & "FERR : Q5, " & "FLUSH : AN7, " & "FRCMC : Y35, " & "HIT : AK6, " & "HITM : AL5, " & "HLDA : AJ3, " & "HOLD : AB4, " & "IERR : P4, " & "IGNNE : AA35, " & "INIT : AA33, " & "INV : U5, " & "KEN : W5, " & "LINT0INTR : AD34, " & "LINT1NMI : AC33, " & "LOCK : AH4, " & "M_IO : T4, " & "NA : Y5, " & "PBGNT : AD4, " & "PBREQ : AE3, " & "PCD : AG5, " & "PCHK : AF4, " & "PEN : Z34, " & "PHIT : AA3, " & "PHITM : AC3, " & "PICCLK : H34, " & "PICD : (J33, L35), " & "PRDY : AC5, " & "PWT : AL3, " & "R_S : AC35, " & "RESET : AK20, " & "SCYC : AL17, " & "SMI : AB34, " & "SMIACT : AG3, " & "STPCLK : V34, " & "TCK : M34, " & "TDI : N35, " & "TDO : N33, " & "TMS : P34, " & "TRST : Q33, " & "W_R : AM6, " & "WB_WT : AA5, " & "VCC : ( A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29, E37, G1, G37, J1, J37, L1, " & " L33, L37, N1, N37, Q1, Q37, S1, S37, T34, U1, U33, U37, W1, W37, Y1, Y37, AA1, AA37, " & " AC1, AC37, AE1, AE37, AG1, AG37, AN9, AN11, AN13, AN15, AN17, AN19, AN21, AN23, AN25, AN27, AN29), " & "VSS : ( B6, B8, B10, B12, B14, B16, B18, B20, B22, B24, B26, B28, H2, H36, K2, K36, " & " M2, M36, P2, P36, R2, R36, T2, T36, U35, V2, V36, X2, X36, Z2, Z36, AB2, " & " AB36, AD2, AD36, AF2, AF36, AH2, AJ37, AL37, AM8, AM10, AM12, AM14, AM16, AM18, AM20, AM22, " & " AM24, AM26, AM28, AM30, AN37), " & "NC : (A3, A37, B2, C1, R34, S33, S35, W33, W35, AL1, AL19, AN1, AN3, AN5, AN35) "; -- -- Scan Port Identification -- attribute TAP_SCAN_IN of TDI :signal is true; attribute TAP_SCAN_OUT of TDO :signal is true; attribute TAP_SCAN_MODE of TMS :signal is true; attribute TAP_SCAN_RESET of TRST :signal is true; attribute TAP_SCAN_CLOCK of TCK :signal is (16.0e6, both); -- -- Instruction Register and Op-codes -- attribute Instruction_Length of Pentium_P54C: entity is 13; attribute Instruction_Opcode of Pentium_P54C: entity is "EXTEST (0000000000000), " & -- xxxxxxxxx0000 "SAMPLE (0000000000001), " & -- xxxxxxxxx0001 "IDCODE (0000000000010), " & -- xxxxxxxxx0010 -- "RUNBIST (0000000000111), " & -- xxxxxxxxx0111 "HIGHZ (0000000001011), " & -- xxxxxxxxx1011 "BYPASS (1111111111111) " ; -- xxxxxxxxx1111 -- "Private (xxxxxxxxx0011, xxxxxxxxx0100, xxxxxxxxx0101, xxxxxxxxx0110, " & -- "xxxxxxxxx1000, xxxxxxxxx1001, xxxxxxxxx1010, xxxxxxxxx1100) "; attribute Instruction_Capture of Pentium_P54C: entity is "0000000000001"; attribute Instruction_Disable of Pentium_P54C: entity is "HIGHZ"; -- attribute Instruction_Private of Pentium_P54C: entity is "Private"; -- -- Pentium IDCODE Register -- attribute Idcode_Register of Pentium_P54C: entity is "xxxx" & -- Version, stepping "1000001010101000" & -- Part number "00000001001" & -- Manufacturer's identity "1"; -- Required by the 1149.1 standard -- -- Pentium Data Register Access -- attribute Register_Access of Pentium_P54C: entity is "BOUNDARY (EXTEST, SAMPLE), " & -- "RUNBIST (RUNBIST), " & "IDCODE (IDCODE), " & "BYPASS (HIGHZ, BYPASS)"; -- -- Pentium Boundary Register Description -- -- Cell 0 (Bottom) is closest to TDO -- attribute BOUNDARY_CELLS of Pentium_P54C: entity is "BC_2, BS_3, BS_4, BS_G"; attribute BOUNDARY_LENGTH of Pentium_P54C: entity is 191; attribute BOUNDARY_REGISTER of Pentium_P54C: entity is -- num cell port function safe [ccell disval rslt] "190 (BS_G, *, control, 1 ), " & -- (Disapsba) PICD0, PICD1 "189 (BS_G, PICD(1), bidir, 1, 190, 1, Weak0 ), " & "188 (BS_G, PICD(0), bidir, 1, 190, 1, Weak1 ), " & "187 (BY_3, *, internal, 0 ), " & "186 (BS_4, PICCLK, input, 1 ), " & "185 (BS_G, D(0), bidir, 1, 133, 1, Z ), " & "184 (BS_G, D(1), bidir, 1, 133, 1, Z ), " & "183 (BS_G, D(2), bidir, 1, 133, 1, Z ), " & "182 (BS_G, D(3), bidir, 1, 133, 1, Z ), " & "181 (BS_G, D(4), bidir, 1, 133, 1, Z ), " & "180 (BS_G, D(5), bidir, 1, 133, 1, Z ), " & "179 (BS_G, D(6), bidir, 1, 133, 1, Z ), " & "178 (BS_G, D(7), bidir, 1, 133, 1, Z ), " & "177 (BS_G, DP(0), bidir, 1, 133, 1, Z ), " & "176 (BS_G, D(8), bidir, 1, 133, 1, Z ), " & "175 (BS_G, D(9), bidir, 1, 133, 1, Z ), " & "174 (BS_G, D(10), bidir, 1, 133, 1, Z ), " & "173 (BS_G, D(11), bidir, 1, 133, 1, Z ), " & "172 (BS_G, D(12), bidir, 1, 133, 1, Z ), " & "171 (BS_G, D(13), bidir, 1, 133, 1, Z ), " & "170 (BS_G, D(14), bidir, 1, 133, 1, Z ), " & "169 (BS_G, D(15), bidir, 1, 133, 1, Z ), " & "168 (BS_G, DP(1), bidir, 1, 133, 1, Z ), " & "167 (BS_G, D(16), bidir, 1, 133, 1, Z ), " & "166 (BS_G, D(17), bidir, 1, 133, 1, Z ), " & "165 (BS_G, D(18), bidir, 1, 133, 1, Z ), " & "164 (BS_G, D(19), bidir, 1, 133, 1, Z ), " & "163 (BS_G, D(20), bidir, 1, 133, 1, Z ), " & "162 (BS_G, D(21), bidir, 1, 133, 1, Z ), " & "161 (BS_G, D(22), bidir, 1, 133, 1, Z ), " & "160 (BS_G, D(23), bidir, 1, 133, 1, Z ), " & "159 (BS_G, DP(2), bidir, 1, 133, 1, Z ), " & "158 (BS_G, D(24), bidir, 1, 133, 1, Z ), " & "157 (BS_G, D(25), bidir, 1, 133, 1, Z ), " & "156 (BS_G, D(26), bidir, 1, 133, 1, Z ), " & "155 (BS_G, D(27), bidir, 1, 133, 1, Z ), " & "154 (BS_G, D(28), bidir, 1, 133, 1, Z ), " & "153 (BS_G, D(29), bidir, 1, 133, 1, Z ), " & "152 (BS_G, D(30), bidir, 1, 133, 1, Z ), " & "151 (BS_G, D(31), bidir, 1, 133, 1, Z ), " & "150 (BS_G, DP(3), bidir, 1, 133, 1, Z ), " & "149 (BS_G, D(32), bidir, 1, 133, 1, Z ), " & "148 (BS_G, D(33), bidir, 1, 133, 1, Z ), " & "147 (BS_G, D(34), bidir, 1, 133, 1, Z ), " & "146 (BS_G, D(35), bidir, 1, 133, 1, Z ), " & "145 (BS_G, D(36), bidir, 1, 133, 1, Z ), " & "144 (BS_G, D(37), bidir, 1, 133, 1, Z ), " & "143 (BS_G, D(38), bidir, 1, 133, 1, Z ), " & "142 (BS_G, D(39), bidir, 1, 133, 1, Z ), " & "141 (BS_G, DP(4), bidir, 1, 133, 1, Z ), " & "140 (BS_G, D(40), bidir, 1, 133, 1, Z ), " & "139 (BS_G, D(41), bidir, 1, 133, 1, Z ), " & "138 (BS_G, D(42), bidir, 1, 133, 1, Z ), " & "137 (BS_G, D(43), bidir, 1, 133, 1, Z ), " & "136 (BS_G, D(44), bidir, 1, 133, 1, Z ), " & "135 (BS_G, D(45), bidir, 1, 133, 1, Z ), " & "134 (BS_G, D(46), bidir, 1, 133, 1, Z ), " & "133 (BS_G, *, control, 1 ), " & -- (Diswr) DP7-DP0, D63-D0 "132 (BS_G, D(47), bidir, 1, 133, 1, Z ), " & "131 (BS_G, DP(5), bidir, 1, 133, 1, Z ), " & "130 (BS_G, D(48), bidir, 1, 133, 1, Z ), " & "129 (BS_G, D(49), bidir, 1, 133, 1, Z ), " & "128 (BS_G, D(50), bidir, 1, 133, 1, Z ), " & "127 (BS_G, D(51), bidir, 1, 133, 1, Z ), " & "126 (BS_G, D(52), bidir, 1, 133, 1, Z ), " & "125 (BS_G, D(53), bidir, 1, 133, 1, Z ), " & "124 (BS_G, D(54), bidir, 1, 133, 1, Z ), " & "123 (BS_G, D(55), bidir, 1, 133, 1, Z ), " & "122 (BS_G, DP(6), bidir, 1, 133, 1, Z ), " & "121 (BS_G, D(56), bidir, 1, 133, 1, Z ), " & "120 (BS_G, D(57), bidir, 1, 133, 1, Z ), " & "119 (BS_G, D(58), bidir, 1, 133, 1, Z ), " & "118 (BS_G, D(59), bidir, 1, 133, 1, Z ), " & "117 (BS_G, D(60), bidir, 1, 133, 1, Z ), " & "116 (BS_G, D(61), bidir, 1, 133, 1, Z ), " & "115 (BS_G, D(62), bidir, 1, 133, 1, Z ), " & "114 (BS_G, D(63), bidir, 1, 133, 1, Z ), " & "113 (BS_G, DP(7), bidir, 1, 133, 1, Z ), " & "112 (BS_G, IERR, bidir, 1, 90, 1, Z ), " & "111 (BC_2, FERR, bidir, 1, 89, 1, Z ), " & "110 (BS_2, BP(0), bidir, 1, 93, 1, Z ), " & "109 (BS_2, BP(1), bidir, 1, 93, 1, Z ), " & "108 (BS_2, BP(2), bidir, 1, 93, 1, Z ), " & "107 (BS_2, BP(3), bidir, 1, 93, 1, Z ), " & "106 (BS_2, M_IO, bidir, 1, 96, 1, Z ), " & "105 (BS_2, CACHE, bidir, 1, 96, 1, Z ), " & "104 (BS_4, EWBE, input, 1 ), " & "103 (BS_4, INV, input, 1 ), " & "102 (BS_4, AHOLD, input, 1 ), " & "101 (BS_4, KEN, input, 1 ), " & "100 (BS_4, BRDYC, input, 1 ), " & " 99 (BS_4, BRDY, input, 1 ), " & " 98 (BS_4, BOFF, input, 1 ), " & " 97 (BS_4, NA, input, 1 ), " & " 96 (BS_G, *, control, 1 ), " & -- (Disbus) SCYC, BE7#-BE0#, W/R#, D/C#, PWT, PCD, CACHE#, M/IO# " 95 (BS_G, *, control, 1 ), " & -- (Dismisch) HIT#, HITM#, HLDA, BREQ#, SMIACT# " 94 (BS_G, *, control, 1 ), " & -- (Disbus1) ADS#, ADSC#, LOCK# " 93 (BS_G, *, control, 1 ), " & -- (Dismisc) APCHK#, PCHK#, PRDY#, BP3, BP2, PM1/BP1, PM0/BP0 " 92 (BS_G, *, control, 1 ), " & -- (Disua2bus) PBGNT# " 91 (BS_G, *, control, 1 ), " & -- (Disua1bus) PBREQ#, PHIT#, PHITM# " 90 (BS_G, *, control, 1 ), " & -- (Dismisca) IERR# " 89 (BS_G, *, control, 1 ), " & -- (Dismiscfa) D/P#, FERR# " 88 (BS_4, WB_WT, input, 1 ), " & " 87 (BS_4, HOLD, input, 1 ), " & " 86 (BS_G, PHITM, bidir, 1, 91, 1, Weak1 ), " & " 85 (BS_G, PHIT, bidir, 1, 91, 1, Weak1 ), " & " 84 (BS_G, PBREQ, bidir, 1, 91, 1, Weak1 ), " & " 83 (BS_G, PBGNT, bidir, 1, 92, 1, Weak1 ), " & " 82 (BS_2, SMIACT, bidir, 1, 95, 1, Z ), " & " 81 (BS_2, PRDY, bidir, 1, 93, 1, Z ), " & " 80 (BS_2, PCHK, bidir, 1, 93, 1, Z ), " & " 79 (BS_2, APCHK, bidir, 1, 93, 1, Z ), " & " 78 (BS_2, BREQ, bidir, 1, 95, 1, Z ), " & " 77 (BS_2, HLDA, bidir, 1, 95, 1, Z ), " & " 76 (BS_G, AP, bidir, 1, 51, 1, Z ), " & " 75 (BS_2, LOCK, bidir, 1, 94, 1, Z ), " & " 74 (BS_2, ADSC, bidir, 1, 94, 1, Z ), " & " 73 (BS_2, PCD, bidir, 1, 96, 1, Z ), " & " 72 (BS_2, PWT, bidir, 1, 96, 1, Z ), " & " 71 (BS_2, D_C, bidir, 1, 96, 1, Z ), " & " 70 (BS_4, EADS, input, 1 ), " & " 69 (BS_2, ADS, bidir, 1, 94, 1, Z ), " & " 68 (BS_2, HITM, bidir, 1, 95, 1, Z ), " & " 67 (BS_2, HIT, bidir, 1, 95, 1, Z ), " & " 66 (BS_2, W_R, bidir, 1, 96, 1, Z ), " & " 65 (BS_4, BUSCHK, input, 1 ), " & " 64 (BS_4, FLUSH, input, 1 ), " & " 63 (BS_4, A20M, input, 1 ), " & " 62 (BS_G, BE(0), bidir, 1, 96, 1, Weak0 ), " & " 61 (BS_G, BE(1), bidir, 1, 96, 1, Weak0 ), " & " 60 (BS_G, BE(2), bidir, 1, 96, 1, Weak0 ), " & " 59 (BS_G, BE(3), bidir, 1, 96, 1, Weak0 ), " & " 58 (BS_G, BE(4), bidir, 1, 96, 1, Weak0 ), " & " 57 (BS_G, BE(5), bidir, 1, 96, 1, Weak0 ), " & " 56 (BS_G, BE(6), bidir, 1, 96, 1, Weak0 ), " & " 55 (BS_G, BE(7), bidir, 1, 96, 1, Weak0 ), " & " 54 (BS_2, SCYC, bidir, 1, 96, 1, Z ), " & " 53 (BS_4, CLK, input, 1 ), " & -- aka BCLK " 52 (BS_4, RESET, input, 1 ), " & " 51 (BS_G, *, control, 1 ), " & -- (Disabus) A31-A3, AP " 50 (BS_G, A(20), bidir, 1, 51, 1, Z ), " & " 49 (BS_G, A(19), bidir, 1, 51, 1, Z ), " & " 48 (BS_G, A(18), bidir, 1, 51, 1, Z ), " & " 47 (BS_G, A(17), bidir, 1, 51, 1, Z ), " & " 46 (BS_G, A(16), bidir, 1, 51, 1, Z ), " & " 45 (BS_G, A(15), bidir, 1, 51, 1, Z ), " & " 44 (BS_G, A(14), bidir, 1, 51, 1, Z ), " & " 43 (BS_G, A(13), bidir, 1, 51, 1, Z ), " & " 42 (BS_G, A(12), bidir, 1, 51, 1, Z ), " & " 41 (BS_G, A(11), bidir, 1, 51, 1, Z ), " & " 40 (BS_G, A(10), bidir, 1, 51, 1, Z ), " & " 39 (BS_G, A(9), bidir, 1, 51, 1, Z ), " & " 38 (BS_G, A(8), bidir, 1, 51, 1, Z ), " & " 37 (BS_G, A(7), bidir, 1, 51, 1, Z ), " & " 36 (BS_G, A(6), bidir, 1, 51, 1, Z ), " & " 35 (BS_G, A(5), bidir, 1, 51, 1, Z ), " & " 34 (BS_G, A(4), bidir, 1, 51, 1, Z ), " & " 33 (BS_G, A(3), bidir, 1, 51, 1, Z ), " & " 32 (BS_G, A(31), bidir, 1, 51, 1, Z ), " & " 31 (BS_G, A(30), bidir, 1, 51, 1, Z ), " & " 30 (BS_G, A(29), bidir, 1, 51, 1, Z ), " & " 29 (BS_G, A(28), bidir, 1, 51, 1, Z ), " & " 28 (BS_G, A(27), bidir, 1, 51, 1, Z ), " & " 27 (BS_G, A(26), bidir, 1, 51, 1, Z ), " & " 26 (BS_G, A(25), bidir, 1, 51, 1, Z ), " & " 25 (BS_G, A(24), bidir, 1, 51, 1, Z ), " & " 24 (BS_G, A(23), bidir, 1, 51, 1, Z ), " & " 23 (BS_G, A(22), bidir, 1, 51, 1, Z ), " & " 22 (BS_G, A(21), bidir, 1, 51, 1, Z ), " & " 21 (BS_2, D_P, bidir, 1, 89, 1, Z ), " & " 20 (BS_4, LINT1NMI, input, 1 ), " & -- NMI " 19 (BS_4, R_S, input, 1 ), " & " 18 (BS_4, LINT0INTR, input, 1 ), " & -- INTR " 17 (BS_4, SMI, input, 1 ), " & " 16 (BS_4, IGNNE, input, 1 ), " & " 15 (BS_4, INIT, input, 1 ), " & " 14 (BS_4, PEN, input, 1 ), " & " 13 (BS_4, FRCMC, input, 1 ), " & " 12 (BY_3, *, internal, 1 ), " & " 11 (BY_3, *, internal, 0 ), " & " 10 (BS_G, BF(0), input, 1 ), " & " 9 (BS_G, BF(1), input, 1 ), " & " 8 (BY_3, *, internal, 1 ), " & " 7 (BS_4, STPCLK, input, 1 ), " & " 6 (BY_3, *, internal, 0 ), " & " 5 (BY_3, *, internal, 1 ), " & " 4 (BY_3, *, internal, 0 ), " & " 3 (BY_3, *, internal, 0 ), " & " 2 (BY_3, *, internal, 0 ), " & " 1 (BY_3, *, internal, 1 ), " & " 0 (BS_4, CPUTYP, input, 1 ) " ; end Pentium_P54C;