-- Generated by boundaryScanGenerate 2016.4 Wed Dec 07 21:52:49 GMT 2016 on 07/25/17 21:31:12 -- BSDL Version 2001 entity ATHENA_TOP is generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME"); port ( -- Port List JTAG_TDI : in bit; SMB_S_ADDR1 : inout bit; STR_INIT_SEL0 : inout bit; PORT_GOOD0_N : inout bit; PCIERX_P40 : in bit; PCIERX_N40 : in bit; PCIERX_P41 : in bit; PCIERX_N41 : in bit; PCIERX_P42 : in bit; PCIERX_N42 : in bit; PCIERX_P43 : in bit; PCIERX_N43 : in bit; PCIETX_P40 : out bit; PCIETX_N40 : out bit; PCIETX_P41 : out bit; PCIETX_N41 : out bit; PCIETX_P42 : out bit; PCIETX_N42 : out bit; PCIETX_P43 : out bit; PCIETX_N43 : out bit; PCIERX_P44 : in bit; PCIERX_N44 : in bit; PCIERX_P45 : in bit; PCIERX_N45 : in bit; PCIERX_P46 : in bit; PCIERX_N46 : in bit; PCIERX_P47 : in bit; PCIERX_N47 : in bit; PCIETX_P44 : out bit; PCIETX_N44 : out bit; PCIETX_P45 : out bit; PCIETX_N45 : out bit; PCIETX_P46 : out bit; PCIETX_N46 : out bit; PCIETX_P47 : out bit; PCIETX_N47 : out bit; PCIETX_P60 : out bit; PCIETX_N60 : out bit; PCIETX_P61 : out bit; PCIETX_N61 : out bit; PCIETX_P62 : out bit; PCIETX_N62 : out bit; PCIETX_P63 : out bit; PCIETX_N63 : out bit; PCIERX_P60 : in bit; PCIERX_N60 : in bit; PCIERX_P61 : in bit; PCIERX_N61 : in bit; PCIERX_P62 : in bit; PCIERX_N62 : in bit; PCIERX_P63 : in bit; PCIERX_N63 : in bit; PCIETX_P56 : out bit; PCIETX_N56 : out bit; PCIETX_P57 : out bit; PCIETX_N57 : out bit; PCIETX_P58 : out bit; PCIETX_N58 : out bit; PCIETX_P59 : out bit; PCIETX_N59 : out bit; PCIERX_P56 : in bit; PCIERX_N56 : in bit; PCIERX_P57 : in bit; PCIERX_N57 : in bit; PCIERX_P58 : in bit; PCIERX_N58 : in bit; PCIERX_P59 : in bit; PCIERX_N59 : in bit; STR_BLK2_PORT_CNFG0 : inout bit; GPIO3_9 : inout bit; STR_BLK3_PORT_CNFG2 : inout bit; FATAL_ERROR_N : inout bit; GPIO3_5 : inout bit; STR_BLK0_PORT_CNFG2 : inout bit; STR_BLK2_PORT_CNFG1 : inout bit; GPIO2_4 : inout bit; STR_BLK2_PORT_CNFG2 : inout bit; SPARE_DIGIO_5 : inout bit; GPIO2_8 : inout bit; STR_INIT_SEC0 : inout bit; GPIO2_2 : inout bit; GPIO2_0 : inout bit; SPARE_DIGIO_0 : inout bit; PCIETX_P52 : out bit; PCIETX_N52 : out bit; PCIETX_P53 : out bit; PCIETX_N53 : out bit; PCIETX_P54 : out bit; PCIETX_N54 : out bit; PCIETX_P55 : out bit; PCIETX_N55 : out bit; PCIERX_P52 : in bit; PCIERX_N52 : in bit; PCIERX_P53 : in bit; PCIERX_N53 : in bit; PCIERX_P54 : in bit; PCIERX_N54 : in bit; PCIERX_P55 : in bit; PCIERX_N55 : in bit; GPIO2_7 : inout bit; GPIO2_1 : inout bit; SPARE_DIGIO_1 : inout bit; GPIO2_5 : inout bit; GPIO2_3 : inout bit; SPARE_DIGIO_2 : inout bit; NT_PERST4_N : inout bit; NT_PERST2_N : inout bit; PCIERX_P48 : in bit; PCIERX_N48 : in bit; PCIERX_P49 : in bit; PCIERX_N49 : in bit; PCIERX_P50 : in bit; PCIERX_N50 : in bit; PCIERX_P51 : in bit; PCIERX_N51 : in bit; PCIETX_P48 : out bit; PCIETX_N48 : out bit; PCIETX_P49 : out bit; PCIETX_N49 : out bit; PCIETX_P50 : out bit; PCIETX_N50 : out bit; PCIETX_P51 : out bit; PCIETX_N51 : out bit; QSPI_DQ0 : inout bit; GPIO2_9 : inout bit; GPIO4_5 : inout bit; GPIO3_1 : inout bit; QSPI_DQ1 : inout bit; SPARE_DIGIO_3 : inout bit; GPIO4_4 : inout bit; SPARE_DIGIO_6 : inout bit; QSPI_CS_N : inout bit; SPARE_DIGIO_4 : inout bit; QSPI_CLK : inout bit; SPARE_DIGIO_7 : inout bit; GPIO0_0 : inout bit; SMB_M_DATA : inout bit; SMB_M_ATTN_N : inout bit; SPARE_DIGIO_8 : inout bit; GPIO0_1 : inout bit; SMB_M_CLK : inout bit; GPIO2_6 : inout bit; SPARE_DIGIO_9 : inout bit; GPIO0_5 : inout bit; INTA6_N : inout bit; STR_CLK_SEL : inout bit; SPARE_DIGIO_10 : inout bit; GPIO0_2 : inout bit; GPIO4_6 : inout bit; STR_INIT_SEC1 : inout bit; GPIO4_9 : inout bit; GPIO0_3 : inout bit; GPIO0_4 : inout bit; NT_PERST6_N : inout bit; GPIO0_7 : inout bit; GPIO0_6 : inout bit; STR_BLK0_PORT_CNFG0 : inout bit; GPIO0_9 : inout bit; GPIO0_8 : inout bit; NT_PERST0_N : inout bit; PCIERX_P15 : in bit; PCIERX_N15 : in bit; PCIERX_P14 : in bit; PCIERX_N14 : in bit; PCIERX_P13 : in bit; PCIERX_N13 : in bit; PCIERX_P12 : in bit; PCIERX_N12 : in bit; PCIETX_P15 : out bit; PCIETX_N15 : out bit; PCIETX_P14 : out bit; PCIETX_N14 : out bit; PCIETX_P13 : out bit; PCIETX_N13 : out bit; PCIETX_P12 : out bit; PCIETX_N12 : out bit; PCIERX_P11 : in bit; PCIERX_N11 : in bit; PCIERX_P10 : in bit; PCIERX_N10 : in bit; PCIERX_P9 : in bit; PCIERX_N9 : in bit; PCIERX_P8 : in bit; PCIERX_N8 : in bit; PCIETX_P11 : out bit; PCIETX_N11 : out bit; PCIETX_P10 : out bit; PCIETX_N10 : out bit; PCIETX_P9 : out bit; PCIETX_N9 : out bit; PCIETX_P8 : out bit; PCIETX_N8 : out bit; PCIETX_P4 : out bit; PCIETX_N4 : out bit; PCIETX_P5 : out bit; PCIETX_N5 : out bit; PCIETX_P6 : out bit; PCIETX_N6 : out bit; PCIETX_P7 : out bit; PCIETX_N7 : out bit; PCIERX_P4 : in bit; PCIERX_N4 : in bit; PCIERX_P5 : in bit; PCIERX_N5 : in bit; PCIERX_P6 : in bit; PCIERX_N6 : in bit; PCIERX_P7 : in bit; PCIERX_N7 : in bit; PCIETX_P0 : out bit; PCIETX_N0 : out bit; PCIETX_P1 : out bit; PCIETX_N1 : out bit; PCIETX_P2 : out bit; PCIETX_N2 : out bit; PCIETX_P3 : out bit; PCIETX_N3 : out bit; PCIERX_P0 : in bit; PCIERX_N0 : in bit; PCIERX_P1 : in bit; PCIERX_N1 : in bit; PCIERX_P2 : in bit; PCIERX_N2 : in bit; PCIERX_P3 : in bit; PCIERX_N3 : in bit; STR_BLK0_PORT_CNFG1 : inout bit; GPIO1_1 : inout bit; GPIO3_4 : inout bit; STR_TEST_EN : in bit; GPIO1_5 : inout bit; GPIO1_9 : inout bit; GPIO4_8 : inout bit; GPIO1_7 : inout bit; GPIO1_8 : inout bit; GPIO1_4 : inout bit; GPIO1_2 : inout bit; PERST0_N : inout bit; GPIO1_0 : inout bit; GPIO1_3 : inout bit; SPARE_DIGIO_16 : inout bit; SMB_S_ATTN_N : inout bit; GPIO3_2 : inout bit; GPIO1_6 : inout bit; SPARE_DIGIO_15 : inout bit; PERST2_N : inout bit; INTA4_N : inout bit; INTA2_N : inout bit; SPARE_DIGIO_14 : inout bit; PERST4_N : inout bit; PERST6_N : inout bit; STR_INIT_SEL1 : inout bit; SPARE_DIGIO_13 : inout bit; GPIO4_7 : inout bit; GPIO3_3 : inout bit; GPIO4_2 : inout bit; SPARE_DIGIO_12 : inout bit; GPIO4_1 : inout bit; SPARE_DIGIO_11 : inout bit; GPIO4_3 : inout bit; PCIETX_P32 : out bit; PCIETX_N32 : out bit; PCIETX_P33 : out bit; PCIETX_N33 : out bit; PCIETX_P34 : out bit; PCIETX_N34 : out bit; PCIETX_P35 : out bit; PCIETX_N35 : out bit; PCIERX_P32 : in bit; PCIERX_N32 : in bit; PCIERX_P33 : in bit; PCIERX_N33 : in bit; PCIERX_P34 : in bit; PCIERX_N34 : in bit; PCIERX_P35 : in bit; PCIERX_N35 : in bit; GPIO3_0 : inout bit; QSPI_DQ2 : inout bit; GPIO3_7 : inout bit; GPIO3_6 : inout bit; SMB_S_ADDR2 : inout bit; RESET_N : in bit; QSPI_DQ3 : inout bit; STR_INIT_VP1 : inout bit; JTAG_TMS : in bit; JTAG_TCK : in bit; PCIERX_P36 : in bit; PCIERX_N36 : in bit; PCIERX_P37 : in bit; PCIERX_N37 : in bit; PCIERX_P38 : in bit; PCIERX_N38 : in bit; PCIERX_P39 : in bit; PCIERX_N39 : in bit; PCIETX_P36 : out bit; PCIETX_N36 : out bit; PCIETX_P37 : out bit; PCIETX_N37 : out bit; PCIETX_P38 : out bit; PCIETX_N38 : out bit; PCIETX_P39 : out bit; PCIETX_N39 : out bit; SMB_S_CLK : inout bit; INTA0_N : inout bit; SMB_S_DATA : inout bit; STR_BLK3_PORT_CNFG1 : inout bit; JTAG_TRST_N : in bit; STR_INIT_VP0 : inout bit; GPIO3_8 : inout bit; GPIO4_0 : inout bit; IOEXTENDER_ATTN_N : inout bit; STR_BLK3_PORT_CNFG0 : inout bit; SMB_S_ADDR0 : inout bit; JTAG_TDO : out bit; REF_CLK_P_Q15 : linkage bit; REF_CLK_N_Q15 : linkage bit; REF_CLK_P_Q14 : linkage bit; REF_CLK_N_Q14 : linkage bit; REFRES_Q15 : linkage bit; REFRES_Q14 : linkage bit; ATEST1_Q15 : linkage bit; ATEST1_Q14 : linkage bit; ATEST0_Q15 : linkage bit; ATEST0_Q14 : linkage bit; REF_CLK_P_Q13 : linkage bit; REF_CLK_N_Q13 : linkage bit; REF_CLK_P_Q12 : linkage bit; REF_CLK_N_Q12 : linkage bit; REFRES_Q13 : linkage bit; REFRES_Q12 : linkage bit; ATEST1_Q13 : linkage bit; ATEST1_Q12 : linkage bit; ATEST0_Q13 : linkage bit; ATEST0_Q12 : linkage bit; REF_CLK_P_Q11 : linkage bit; REF_CLK_N_Q11 : linkage bit; REF_CLK_P_Q10 : linkage bit; REF_CLK_N_Q10 : linkage bit; REFRES_Q11 : linkage bit; REFRES_Q10 : linkage bit; ATEST1_Q11 : linkage bit; ATEST1_Q10 : linkage bit; ATEST0_Q11 : linkage bit; ATEST0_Q10 : linkage bit; REF_CLK_P_Q9 : linkage bit; REF_CLK_N_Q9 : linkage bit; REF_CLK_P_Q8 : linkage bit; REF_CLK_N_Q8 : linkage bit; REFRES_Q9 : linkage bit; REFRES_Q8 : linkage bit; ATEST1_Q9 : linkage bit; ATEST1_Q8 : linkage bit; ATEST0_Q9 : linkage bit; ATEST0_Q8 : linkage bit; REF_CLK_P_Q3 : linkage bit; REF_CLK_N_Q3 : linkage bit; REF_CLK_P_Q2 : linkage bit; REF_CLK_N_Q2 : linkage bit; REFRES_Q3 : linkage bit; REFRES_Q2 : linkage bit; ATEST1_Q3 : linkage bit; ATEST1_Q2 : linkage bit; ATEST0_Q3 : linkage bit; ATEST0_Q2 : linkage bit; REF_CLK_P_Q1 : linkage bit; REF_CLK_N_Q1 : linkage bit; REF_CLK_P_Q0 : linkage bit; REF_CLK_N_Q0 : linkage bit; REFRES_Q1 : linkage bit; REFRES_Q0 : linkage bit; ATEST1_Q1 : linkage bit; ATEST1_Q0 : linkage bit; ATEST0_Q1 : linkage bit; ATEST0_Q0 : linkage bit; SPARE_ANAIO_4 : linkage bit; SPARE_ANAIO_3 : linkage bit; SPARE_ANAIO_2 : linkage bit; SPARE_ANAIO_1 : linkage bit; SPARE_ANAIO_0 : linkage bit; TEMP_DIODEP : linkage bit; TEMP_DIODEN : linkage bit; REF_RES_PLL : linkage bit; ATEST_PLL : linkage bit; ADC_IN0 : linkage bit; ADC_IN1 : linkage bit; ADC_IN2 : linkage bit; ADC_IN3 : linkage bit; ADC_IN4 : linkage bit; REF_CLK_P_PLL : linkage bit; REF_CLK_N_PLL : linkage bit; VQPS : linkage bit); use STD_1149_1_2001.all; use STD_1149_6_2003.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of ATHENA_TOP: entity is "STD_1149_1_2001"; --Pin mappings attribute PIN_MAP of ATHENA_TOP: entity is PHYSICAL_PIN_MAP; constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := "JTAG_TDI : 339 , " & "SMB_S_ADDR1 : 369 , " & "STR_INIT_SEL0 : 350 , " & "PORT_GOOD0_N : 386 , " & "PCIERX_P40 : 113 , " & "PCIERX_N40 : 114 , " & "PCIERX_P41 : 109 , " & "PCIERX_N41 : 110 , " & "PCIERX_P42 : 105 , " & "PCIERX_N42 : 106 , " & "PCIERX_P43 : 101 , " & "PCIERX_N43 : 102 , " & "PCIETX_P40 : 115 , " & "PCIETX_N40 : 116 , " & "PCIETX_P41 : 111 , " & "PCIETX_N41 : 112 , " & "PCIETX_P42 : 107 , " & "PCIETX_N42 : 108 , " & "PCIETX_P43 : 103 , " & "PCIETX_N43 : 104 , " & "PCIERX_P44 : 97 , " & "PCIERX_N44 : 98 , " & "PCIERX_P45 : 93 , " & "PCIERX_N45 : 94 , " & "PCIERX_P46 : 89 , " & "PCIERX_N46 : 90 , " & "PCIERX_P47 : 85 , " & "PCIERX_N47 : 86 , " & "PCIETX_P44 : 99 , " & "PCIETX_N44 : 100 , " & "PCIETX_P45 : 95 , " & "PCIETX_N45 : 96 , " & "PCIETX_P46 : 91 , " & "PCIETX_N46 : 92 , " & "PCIETX_P47 : 87 , " & "PCIETX_N47 : 88 , " & "PCIETX_P60 : 15 , " & "PCIETX_N60 : 16 , " & "PCIETX_P61 : 11 , " & "PCIETX_N61 : 12 , " & "PCIETX_P62 : 7 , " & "PCIETX_N62 : 8 , " & "PCIETX_P63 : 3 , " & "PCIETX_N63 : 4 , " & "PCIERX_P60 : 13 , " & "PCIERX_N60 : 14 , " & "PCIERX_P61 : 9 , " & "PCIERX_N61 : 10 , " & "PCIERX_P62 : 5 , " & "PCIERX_N62 : 6 , " & "PCIERX_P63 : 1 , " & "PCIERX_N63 : 2 , " & "PCIETX_P56 : 31 , " & "PCIETX_N56 : 32 , " & "PCIETX_P57 : 27 , " & "PCIETX_N57 : 28 , " & "PCIETX_P58 : 23 , " & "PCIETX_N58 : 24 , " & "PCIETX_P59 : 19 , " & "PCIETX_N59 : 20 , " & "PCIERX_P56 : 29 , " & "PCIERX_N56 : 30 , " & "PCIERX_P57 : 25 , " & "PCIERX_N57 : 26 , " & "PCIERX_P58 : 21 , " & "PCIERX_N58 : 22 , " & "PCIERX_P59 : 17 , " & "PCIERX_N59 : 18 , " & "STR_BLK2_PORT_CNFG0 : 359 , " & "GPIO3_9 : 295 , " & "STR_BLK3_PORT_CNFG2 : 360 , " & "FATAL_ERROR_N : 385 , " & "GPIO3_5 : 299 , " & "STR_BLK0_PORT_CNFG2 : 354 , " & "STR_BLK2_PORT_CNFG1 : 358 , " & "GPIO2_4 : 290 , " & "STR_BLK2_PORT_CNFG2 : 357 , " & "SPARE_DIGIO_5 : 327 , " & "GPIO2_8 : 286 , " & "STR_INIT_SEC0 : 352 , " & "GPIO2_2 : 292 , " & "GPIO2_0 : 294 , " & "SPARE_DIGIO_0 : 332 , " & "PCIETX_P52 : 57 , " & "PCIETX_N52 : 58 , " & "PCIETX_P53 : 53 , " & "PCIETX_N53 : 54 , " & "PCIETX_P54 : 49 , " & "PCIETX_N54 : 50 , " & "PCIETX_P55 : 45 , " & "PCIETX_N55 : 46 , " & "PCIERX_P52 : 55 , " & "PCIERX_N52 : 56 , " & "PCIERX_P53 : 51 , " & "PCIERX_N53 : 52 , " & "PCIERX_P54 : 47 , " & "PCIERX_N54 : 48 , " & "PCIERX_P55 : 43 , " & "PCIERX_N55 : 44 , " & "GPIO2_7 : 287 , " & "GPIO2_1 : 293 , " & "SPARE_DIGIO_1 : 331 , " & "GPIO2_5 : 289 , " & "GPIO2_3 : 291 , " & "SPARE_DIGIO_2 : 330 , " & "NT_PERST4_N : 208 , " & "NT_PERST2_N : 255 , " & "PCIERX_P48 : 71 , " & "PCIERX_N48 : 72 , " & "PCIERX_P49 : 67 , " & "PCIERX_N49 : 68 , " & "PCIERX_P50 : 63 , " & "PCIERX_N50 : 64 , " & "PCIERX_P51 : 59 , " & "PCIERX_N51 : 60 , " & "PCIETX_P48 : 73 , " & "PCIETX_N48 : 74 , " & "PCIETX_P49 : 69 , " & "PCIETX_N49 : 70 , " & "PCIETX_P50 : 65 , " & "PCIETX_N50 : 66 , " & "PCIETX_P51 : 61 , " & "PCIETX_N51 : 62 , " & "QSPI_DQ0 : 383 , " & "GPIO2_9 : 285 , " & "GPIO4_5 : 309 , " & "GPIO3_1 : 303 , " & "QSPI_DQ1 : 382 , " & "SPARE_DIGIO_3 : 329 , " & "GPIO4_4 : 310 , " & "SPARE_DIGIO_6 : 326 , " & "QSPI_CS_N : 378 , " & "SPARE_DIGIO_4 : 328 , " & "QSPI_CLK : 379 , " & "SPARE_DIGIO_7 : 325 , " & "GPIO0_0 : 274 , " & "SMB_M_DATA : 366 , " & "SMB_M_ATTN_N : 363 , " & "SPARE_DIGIO_8 : 324 , " & "GPIO0_1 : 273 , " & "SMB_M_CLK : 365 , " & "GPIO2_6 : 288 , " & "SPARE_DIGIO_9 : 323 , " & "GPIO0_5 : 269 , " & "INTA6_N : 209 , " & "STR_CLK_SEL : 353 , " & "SPARE_DIGIO_10 : 322 , " & "GPIO0_2 : 272 , " & "GPIO4_6 : 308 , " & "STR_INIT_SEC1 : 351 , " & "GPIO4_9 : 305 , " & "GPIO0_3 : 271 , " & "GPIO0_4 : 270 , " & "NT_PERST6_N : 207 , " & "GPIO0_7 : 267 , " & "GPIO0_6 : 268 , " & "STR_BLK0_PORT_CNFG0 : 356 , " & "GPIO0_9 : 265 , " & "GPIO0_8 : 266 , " & "NT_PERST0_N : 256 , " & "PCIERX_P15 : 169 , " & "PCIERX_N15 : 170 , " & "PCIERX_P14 : 173 , " & "PCIERX_N14 : 174 , " & "PCIERX_P13 : 177 , " & "PCIERX_N13 : 178 , " & "PCIERX_P12 : 181 , " & "PCIERX_N12 : 182 , " & "PCIETX_P15 : 171 , " & "PCIETX_N15 : 172 , " & "PCIETX_P14 : 175 , " & "PCIETX_N14 : 176 , " & "PCIETX_P13 : 179 , " & "PCIETX_N13 : 180 , " & "PCIETX_P12 : 183 , " & "PCIETX_N12 : 184 , " & "PCIERX_P11 : 185 , " & "PCIERX_N11 : 186 , " & "PCIERX_P10 : 189 , " & "PCIERX_N10 : 190 , " & "PCIERX_P9 : 193 , " & "PCIERX_N9 : 194 , " & "PCIERX_P8 : 197 , " & "PCIERX_N8 : 198 , " & "PCIETX_P11 : 187 , " & "PCIETX_N11 : 188 , " & "PCIETX_P10 : 191 , " & "PCIETX_N10 : 192 , " & "PCIETX_P9 : 195 , " & "PCIETX_N9 : 196 , " & "PCIETX_P8 : 199 , " & "PCIETX_N8 : 200 , " & "PCIETX_P4 : 231 , " & "PCIETX_N4 : 232 , " & "PCIETX_P5 : 227 , " & "PCIETX_N5 : 228 , " & "PCIETX_P6 : 223 , " & "PCIETX_N6 : 224 , " & "PCIETX_P7 : 219 , " & "PCIETX_N7 : 220 , " & "PCIERX_P4 : 229 , " & "PCIERX_N4 : 230 , " & "PCIERX_P5 : 225 , " & "PCIERX_N5 : 226 , " & "PCIERX_P6 : 221 , " & "PCIERX_N6 : 222 , " & "PCIERX_P7 : 217 , " & "PCIERX_N7 : 218 , " & "PCIETX_P0 : 247 , " & "PCIETX_N0 : 248 , " & "PCIETX_P1 : 243 , " & "PCIETX_N1 : 244 , " & "PCIETX_P2 : 239 , " & "PCIETX_N2 : 240 , " & "PCIETX_P3 : 235 , " & "PCIETX_N3 : 236 , " & "PCIERX_P0 : 245 , " & "PCIERX_N0 : 246 , " & "PCIERX_P1 : 241 , " & "PCIERX_N1 : 242 , " & "PCIERX_P2 : 237 , " & "PCIERX_N2 : 238 , " & "PCIERX_P3 : 233 , " & "PCIERX_N3 : 234 , " & "STR_BLK0_PORT_CNFG1 : 355 , " & "GPIO1_1 : 283 , " & "GPIO3_4 : 300 , " & "STR_TEST_EN : 315 , " & "GPIO1_5 : 279 , " & "GPIO1_9 : 275 , " & "GPIO4_8 : 306 , " & "GPIO1_7 : 277 , " & "GPIO1_8 : 276 , " & "GPIO1_4 : 280 , " & "GPIO1_2 : 282 , " & "PERST0_N : 254 , " & "GPIO1_0 : 284 , " & "GPIO1_3 : 281 , " & "SPARE_DIGIO_16 : 316 , " & "SMB_S_ATTN_N : 367 , " & "GPIO3_2 : 302 , " & "GPIO1_6 : 278 , " & "SPARE_DIGIO_15 : 317 , " & "PERST2_N : 253 , " & "INTA4_N : 210 , " & "INTA2_N : 257 , " & "SPARE_DIGIO_14 : 318 , " & "PERST4_N : 206 , " & "PERST6_N : 205 , " & "STR_INIT_SEL1 : 349 , " & "SPARE_DIGIO_13 : 319 , " & "GPIO4_7 : 307 , " & "GPIO3_3 : 301 , " & "GPIO4_2 : 312 , " & "SPARE_DIGIO_12 : 320 , " & "GPIO4_1 : 313 , " & "SPARE_DIGIO_11 : 321 , " & "GPIO4_3 : 311 , " & "PCIETX_P32 : 157 , " & "PCIETX_N32 : 158 , " & "PCIETX_P33 : 153 , " & "PCIETX_N33 : 154 , " & "PCIETX_P34 : 149 , " & "PCIETX_N34 : 150 , " & "PCIETX_P35 : 145 , " & "PCIETX_N35 : 146 , " & "PCIERX_P32 : 155 , " & "PCIERX_N32 : 156 , " & "PCIERX_P33 : 151 , " & "PCIERX_N33 : 152 , " & "PCIERX_P34 : 147 , " & "PCIERX_N34 : 148 , " & "PCIERX_P35 : 143 , " & "PCIERX_N35 : 144 , " & "GPIO3_0 : 304 , " & "QSPI_DQ2 : 381 , " & "GPIO3_7 : 297 , " & "GPIO3_6 : 298 , " & "SMB_S_ADDR2 : 368 , " & "RESET_N : 384 , " & "QSPI_DQ3 : 380 , " & "STR_INIT_VP1 : 347 , " & "JTAG_TMS : 340 , " & "JTAG_TCK : 338 , " & "PCIERX_P36 : 139 , " & "PCIERX_N36 : 140 , " & "PCIERX_P37 : 135 , " & "PCIERX_N37 : 136 , " & "PCIERX_P38 : 131 , " & "PCIERX_N38 : 132 , " & "PCIERX_P39 : 127 , " & "PCIERX_N39 : 128 , " & "PCIETX_P36 : 141 , " & "PCIETX_N36 : 142 , " & "PCIETX_P37 : 137 , " & "PCIETX_N37 : 138 , " & "PCIETX_P38 : 133 , " & "PCIETX_N38 : 134 , " & "PCIETX_P39 : 129 , " & "PCIETX_N39 : 130 , " & "SMB_S_CLK : 371 , " & "INTA0_N : 258 , " & "SMB_S_DATA : 372 , " & "STR_BLK3_PORT_CNFG1 : 361 , " & "JTAG_TRST_N : 341 , " & "STR_INIT_VP0 : 348 , " & "GPIO3_8 : 296 , " & "GPIO4_0 : 314 , " & "IOEXTENDER_ATTN_N : 364 , " & "STR_BLK3_PORT_CNFG0 : 362 , " & "SMB_S_ADDR0 : 370 , " & "JTAG_TDO : 342 , " & "REF_CLK_P_Q15 : 33 , " & "REF_CLK_N_Q15 : 34 , " & "REF_CLK_P_Q14 : 35 , " & "REF_CLK_N_Q14 : 36 , " & "REFRES_Q15 : 37 , " & "REFRES_Q14 : 38 , " & "ATEST1_Q15 : 39 , " & "ATEST1_Q14 : 40 , " & "ATEST0_Q15 : 41 , " & "ATEST0_Q14 : 42 , " & "REF_CLK_P_Q13 : 75 , " & "REF_CLK_N_Q13 : 76 , " & "REF_CLK_P_Q12 : 77 , " & "REF_CLK_N_Q12 : 78 , " & "REFRES_Q13 : 79 , " & "REFRES_Q12 : 80 , " & "ATEST1_Q13 : 81 , " & "ATEST1_Q12 : 82 , " & "ATEST0_Q13 : 83 , " & "ATEST0_Q12 : 84 , " & "REF_CLK_P_Q11 : 117 , " & "REF_CLK_N_Q11 : 118 , " & "REF_CLK_P_Q10 : 119 , " & "REF_CLK_N_Q10 : 120 , " & "REFRES_Q11 : 121 , " & "REFRES_Q10 : 122 , " & "ATEST1_Q11 : 123 , " & "ATEST1_Q10 : 124 , " & "ATEST0_Q11 : 125 , " & "ATEST0_Q10 : 126 , " & "REF_CLK_P_Q9 : 159 , " & "REF_CLK_N_Q9 : 160 , " & "REF_CLK_P_Q8 : 161 , " & "REF_CLK_N_Q8 : 162 , " & "REFRES_Q9 : 163 , " & "REFRES_Q8 : 164 , " & "ATEST1_Q9 : 165 , " & "ATEST1_Q8 : 166 , " & "ATEST0_Q9 : 167 , " & "ATEST0_Q8 : 168 , " & "REF_CLK_P_Q3 : 201 , " & "REF_CLK_N_Q3 : 202 , " & "REF_CLK_P_Q2 : 203 , " & "REF_CLK_N_Q2 : 204 , " & "REFRES_Q3 : 211 , " & "REFRES_Q2 : 212 , " & "ATEST1_Q3 : 213 , " & "ATEST1_Q2 : 214 , " & "ATEST0_Q3 : 215 , " & "ATEST0_Q2 : 216 , " & "REF_CLK_P_Q1 : 249 , " & "REF_CLK_N_Q1 : 250 , " & "REF_CLK_P_Q0 : 251 , " & "REF_CLK_N_Q0 : 252 , " & "REFRES_Q1 : 259 , " & "REFRES_Q0 : 260 , " & "ATEST1_Q1 : 261 , " & "ATEST1_Q0 : 262 , " & "ATEST0_Q1 : 263 , " & "ATEST0_Q0 : 264 , " & "SPARE_ANAIO_4 : 333 , " & "SPARE_ANAIO_3 : 334 , " & "SPARE_ANAIO_2 : 335 , " & "SPARE_ANAIO_1 : 336 , " & "SPARE_ANAIO_0 : 337 , " & "TEMP_DIODEP : 343 , " & "TEMP_DIODEN : 344 , " & "REF_RES_PLL : 345 , " & "ATEST_PLL : 346 , " & "ADC_IN0 : 373 , " & "ADC_IN1 : 374 , " & "ADC_IN2 : 375 , " & "ADC_IN3 : 376 , " & "ADC_IN4 : 377 , " & "REF_CLK_P_PLL : 387 , " & "REF_CLK_N_PLL : 388 , " & "VQPS : 389 " ; attribute PORT_GROUPING of ATHENA_TOP : entity is "Differential_Voltage ( (PCIERX_P40, PCIERX_N40), " & "(PCIERX_P41, PCIERX_N41), " & "(PCIERX_P42, PCIERX_N42), " & "(PCIERX_P43, PCIERX_N43), " & "(PCIETX_P40, PCIETX_N40), " & "(PCIETX_P41, PCIETX_N41), " & "(PCIETX_P42, PCIETX_N42), " & "(PCIETX_P43, PCIETX_N43), " & "(PCIERX_P44, PCIERX_N44), " & "(PCIERX_P45, PCIERX_N45), " & "(PCIERX_P46, PCIERX_N46), " & "(PCIERX_P47, PCIERX_N47), " & "(PCIETX_P44, PCIETX_N44), " & "(PCIETX_P45, PCIETX_N45), " & "(PCIETX_P46, PCIETX_N46), " & "(PCIETX_P47, PCIETX_N47), " & "(PCIETX_P60, PCIETX_N60), " & "(PCIETX_P61, PCIETX_N61), " & "(PCIETX_P62, PCIETX_N62), " & "(PCIETX_P63, PCIETX_N63), " & "(PCIERX_P60, PCIERX_N60), " & "(PCIERX_P61, PCIERX_N61), " & "(PCIERX_P62, PCIERX_N62), " & "(PCIERX_P63, PCIERX_N63), " & "(PCIETX_P56, PCIETX_N56), " & "(PCIETX_P57, PCIETX_N57), " & "(PCIETX_P58, PCIETX_N58), " & "(PCIETX_P59, PCIETX_N59), " & "(PCIERX_P56, PCIERX_N56), " & "(PCIERX_P57, PCIERX_N57), " & "(PCIERX_P58, PCIERX_N58), " & "(PCIERX_P59, PCIERX_N59), " & "(PCIETX_P52, PCIETX_N52), " & "(PCIETX_P53, PCIETX_N53), " & "(PCIETX_P54, PCIETX_N54), " & "(PCIETX_P55, PCIETX_N55), " & "(PCIERX_P52, PCIERX_N52), " & "(PCIERX_P53, PCIERX_N53), " & "(PCIERX_P54, PCIERX_N54), " & "(PCIERX_P55, PCIERX_N55), " & "(PCIERX_P48, PCIERX_N48), " & "(PCIERX_P49, PCIERX_N49), " & "(PCIERX_P50, PCIERX_N50), " & "(PCIERX_P51, PCIERX_N51), " & "(PCIETX_P48, PCIETX_N48), " & "(PCIETX_P49, PCIETX_N49), " & "(PCIETX_P50, PCIETX_N50), " & "(PCIETX_P51, PCIETX_N51), " & "(PCIERX_P15, PCIERX_N15), " & "(PCIERX_P14, PCIERX_N14), " & "(PCIERX_P13, PCIERX_N13), " & "(PCIERX_P12, PCIERX_N12), " & "(PCIETX_P15, PCIETX_N15), " & "(PCIETX_P14, PCIETX_N14), " & "(PCIETX_P13, PCIETX_N13), " & "(PCIETX_P12, PCIETX_N12), " & "(PCIERX_P11, PCIERX_N11), " & "(PCIERX_P10, PCIERX_N10), " & "(PCIERX_P9, PCIERX_N9), " & "(PCIERX_P8, PCIERX_N8), " & "(PCIETX_P11, PCIETX_N11), " & "(PCIETX_P10, PCIETX_N10), " & "(PCIETX_P9, PCIETX_N9), " & "(PCIETX_P8, PCIETX_N8), " & "(PCIETX_P4, PCIETX_N4), " & "(PCIETX_P5, PCIETX_N5), " & "(PCIETX_P6, PCIETX_N6), " & "(PCIETX_P7, PCIETX_N7), " & "(PCIERX_P4, PCIERX_N4), " & "(PCIERX_P5, PCIERX_N5), " & "(PCIERX_P6, PCIERX_N6), " & "(PCIERX_P7, PCIERX_N7), " & "(PCIETX_P0, PCIETX_N0), " & "(PCIETX_P1, PCIETX_N1), " & "(PCIETX_P2, PCIETX_N2), " & "(PCIETX_P3, PCIETX_N3), " & "(PCIERX_P0, PCIERX_N0), " & "(PCIERX_P1, PCIERX_N1), " & "(PCIERX_P2, PCIERX_N2), " & "(PCIERX_P3, PCIERX_N3), " & "(PCIETX_P32, PCIETX_N32), " & "(PCIETX_P33, PCIETX_N33), " & "(PCIETX_P34, PCIETX_N34), " & "(PCIETX_P35, PCIETX_N35), " & "(PCIERX_P32, PCIERX_N32), " & "(PCIERX_P33, PCIERX_N33), " & "(PCIERX_P34, PCIERX_N34), " & "(PCIERX_P35, PCIERX_N35), " & "(PCIERX_P36, PCIERX_N36), " & "(PCIERX_P37, PCIERX_N37), " & "(PCIERX_P38, PCIERX_N38), " & "(PCIERX_P39, PCIERX_N39), " & "(PCIETX_P36, PCIETX_N36), " & "(PCIETX_P37, PCIETX_N37), " & "(PCIETX_P38, PCIETX_N38), " & "(PCIETX_P39, PCIETX_N39)) " ; attribute TAP_SCAN_RESET of JTAG_TRST_N : signal is true; attribute TAP_SCAN_IN of JTAG_TDI : signal is true; attribute TAP_SCAN_MODE of JTAG_TMS : signal is true; attribute TAP_SCAN_OUT of JTAG_TDO : signal is true; attribute TAP_SCAN_CLOCK of JTAG_TCK : signal is (3.3000000000000000000e+07, BOTH); attribute COMPLIANCE_PATTERNS of ATHENA_TOP : entity is "(STR_TEST_EN) (1)"; attribute INSTRUCTION_LENGTH of ATHENA_TOP: entity is 31; attribute INSTRUCTION_OPCODE of ATHENA_TOP: entity is "IDCODE (1111111111111111111111111111110)," & "BYPASS (1111111111111111111111111111111)," & "EXTEST (1111111111111111111111111101000)," & "EXTEST_PULSE (1111111111111101111111111101000)," & "EXTEST_TRAIN (1111111111111011111111111101000)," & "SAMPLE (1111111111111111111111111111000)," & "PRELOAD (1111111111111111111111111111000)," & "HIGHZ (1111111111111111111111111001111)," & "CLAMP (1111111111111111111111111101111) " ; attribute INSTRUCTION_CAPTURE of ATHENA_TOP: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of ATHENA_TOP: entity is "0000" & -- version "1100000110011101" & -- part number "01001010110" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of ATHENA_TOP: entity is "BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," & "DEVICE_ID ( IDCODE ), " & "BOUNDARY ( SAMPLE, PRELOAD, EXTEST )," & "BYPASS ( HIGHZ, CLAMP, BYPASS ) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of ATHENA_TOP: entity is 419; attribute BOUNDARY_REGISTER of ATHENA_TOP: entity is -- num cell port function safe [ccell disval rslt] " 418 (BC_2 , * , control , 1 ) ,"& " 417 (LV_BC_7 , SMB_S_ADDR1 , bidir , X , 418 , 1 , Z ),"& " 416 (BC_2 , * , control , 1 ) ,"& " 415 (LV_BC_7 , STR_INIT_SEL0 , bidir , X , 416 , 1 , Z ),"& " 414 (BC_2 , * , control , 1 ) ,"& " 413 (LV_BC_7 , PORT_GOOD0_N , bidir , X , 414 , 1 , Z ),"& " 412 (BC_4 , PCIERX_N40 , observe_only , X ) ,"& " 411 (BC_4 , PCIERX_P40 , observe_only , X ) ,"& " 410 (BC_4 , PCIERX_N41 , observe_only , X ) ,"& " 409 (BC_4 , PCIERX_P41 , observe_only , X ) ,"& " 408 (BC_4 , PCIERX_N42 , observe_only , X ) ,"& " 407 (BC_4 , PCIERX_P42 , observe_only , X ) ,"& " 406 (BC_4 , PCIERX_N43 , observe_only , X ) ,"& " 405 (BC_4 , PCIERX_P43 , observe_only , X ) ,"& " 404 (BC_2 , * , control , 0 ) ,"& " 403 (AC_2 , PCIETX_P40 , output3 , X , 404 , 0 , Z ),"& " 402 (BC_2 , * , control , 0 ) ,"& " 401 (AC_2 , PCIETX_P41 , output3 , X , 402 , 0 , Z ),"& " 400 (BC_2 , * , control , 0 ) ,"& " 399 (AC_2 , PCIETX_P42 , output3 , X , 400 , 0 , Z ),"& " 398 (BC_2 , * , control , 0 ) ,"& " 397 (AC_2 , PCIETX_P43 , output3 , X , 398 , 0 , Z ),"& " 396 (BC_4 , PCIERX_N44 , observe_only , X ) ,"& " 395 (BC_4 , PCIERX_P44 , observe_only , X ) ,"& " 394 (BC_4 , PCIERX_N45 , observe_only , X ) ,"& " 393 (BC_4 , PCIERX_P45 , observe_only , X ) ,"& " 392 (BC_4 , PCIERX_N46 , observe_only , X ) ,"& " 391 (BC_4 , PCIERX_P46 , observe_only , X ) ,"& " 390 (BC_4 , PCIERX_N47 , observe_only , X ) ,"& " 389 (BC_4 , PCIERX_P47 , observe_only , X ) ,"& " 388 (BC_2 , * , control , 0 ) ,"& " 387 (AC_2 , PCIETX_P44 , output3 , X , 388 , 0 , Z ),"& " 386 (BC_2 , * , control , 0 ) ,"& " 385 (AC_2 , PCIETX_P45 , output3 , X , 386 , 0 , Z ),"& " 384 (BC_2 , * , control , 0 ) ,"& " 383 (AC_2 , PCIETX_P46 , output3 , X , 384 , 0 , Z ),"& " 382 (BC_2 , * , control , 0 ) ,"& " 381 (AC_2 , PCIETX_P47 , output3 , X , 382 , 0 , Z ),"& " 380 (BC_2 , * , control , 0 ) ,"& " 379 (AC_2 , PCIETX_P60 , output3 , X , 380 , 0 , Z ),"& " 378 (BC_2 , * , control , 0 ) ,"& " 377 (AC_2 , PCIETX_P61 , output3 , X , 378 , 0 , Z ),"& " 376 (BC_2 , * , control , 0 ) ,"& " 375 (AC_2 , PCIETX_P62 , output3 , X , 376 , 0 , Z ),"& " 374 (BC_2 , * , control , 0 ) ,"& " 373 (AC_2 , PCIETX_P63 , output3 , X , 374 , 0 , Z ),"& " 372 (BC_4 , PCIERX_N60 , observe_only , X ) ,"& " 371 (BC_4 , PCIERX_P60 , observe_only , X ) ,"& " 370 (BC_4 , PCIERX_N61 , observe_only , X ) ,"& " 369 (BC_4 , PCIERX_P61 , observe_only , X ) ,"& " 368 (BC_4 , PCIERX_N62 , observe_only , X ) ,"& " 367 (BC_4 , PCIERX_P62 , observe_only , X ) ,"& " 366 (BC_4 , PCIERX_N63 , observe_only , X ) ,"& " 365 (BC_4 , PCIERX_P63 , observe_only , X ) ,"& " 364 (BC_2 , * , control , 0 ) ,"& " 363 (AC_2 , PCIETX_P56 , output3 , X , 364 , 0 , Z ),"& " 362 (BC_2 , * , control , 0 ) ,"& " 361 (AC_2 , PCIETX_P57 , output3 , X , 362 , 0 , Z ),"& " 360 (BC_2 , * , control , 0 ) ,"& " 359 (AC_2 , PCIETX_P58 , output3 , X , 360 , 0 , Z ),"& " 358 (BC_2 , * , control , 0 ) ,"& " 357 (AC_2 , PCIETX_P59 , output3 , X , 358 , 0 , Z ),"& " 356 (BC_4 , PCIERX_N56 , observe_only , X ) ,"& " 355 (BC_4 , PCIERX_P56 , observe_only , X ) ,"& " 354 (BC_4 , PCIERX_N57 , observe_only , X ) ,"& " 353 (BC_4 , PCIERX_P57 , observe_only , X ) ,"& " 352 (BC_4 , PCIERX_N58 , observe_only , X ) ,"& " 351 (BC_4 , PCIERX_P58 , observe_only , X ) ,"& " 350 (BC_4 , PCIERX_N59 , observe_only , X ) ,"& " 349 (BC_4 , PCIERX_P59 , observe_only , X ) ,"& " 348 (BC_2 , * , control , 1 ) ,"& " 347 (LV_BC_7 , STR_BLK2_PORT_CNFG0 , bidir , X , 348 , 1 , Z ),"& " 346 (BC_2 , * , control , 1 ) ,"& " 345 (LV_BC_7 , GPIO3_9 , bidir , X , 346 , 1 , Z ),"& " 344 (BC_2 , * , control , 1 ) ,"& " 343 (LV_BC_7 , STR_BLK3_PORT_CNFG2 , bidir , X , 344 , 1 , Z ),"& " 342 (BC_2 , * , control , 1 ) ,"& " 341 (LV_BC_7 , FATAL_ERROR_N , bidir , X , 342 , 1 , Z ),"& " 340 (BC_2 , * , control , 1 ) ,"& " 339 (LV_BC_7 , GPIO3_5 , bidir , X , 340 , 1 , Z ),"& " 338 (BC_2 , * , control , 1 ) ,"& " 337 (LV_BC_7 , STR_BLK0_PORT_CNFG2 , bidir , X , 338 , 1 , Z ),"& " 336 (BC_2 , * , control , 1 ) ,"& " 335 (LV_BC_7 , STR_BLK2_PORT_CNFG1 , bidir , X , 336 , 1 , Z ),"& " 334 (BC_2 , * , control , 1 ) ,"& " 333 (LV_BC_7 , GPIO2_4 , bidir , X , 334 , 1 , Z ),"& " 332 (BC_2 , * , control , 1 ) ,"& " 331 (LV_BC_7 , STR_BLK2_PORT_CNFG2 , bidir , X , 332 , 1 , Z ),"& " 330 (BC_2 , * , control , 1 ) ,"& " 329 (LV_BC_7 , SPARE_DIGIO_5 , bidir , X , 330 , 1 , Z ),"& " 328 (BC_2 , * , control , 1 ) ,"& " 327 (LV_BC_7 , GPIO2_8 , bidir , X , 328 , 1 , Z ),"& " 326 (BC_2 , * , control , 1 ) ,"& " 325 (LV_BC_7 , STR_INIT_SEC0 , bidir , X , 326 , 1 , Z ),"& " 324 (BC_2 , * , control , 1 ) ,"& " 323 (LV_BC_7 , GPIO2_2 , bidir , X , 324 , 1 , Z ),"& " 322 (BC_2 , * , control , 1 ) ,"& " 321 (LV_BC_7 , GPIO2_0 , bidir , X , 322 , 1 , Z ),"& " 320 (BC_2 , * , control , 1 ) ,"& " 319 (LV_BC_7 , SPARE_DIGIO_0 , bidir , X , 320 , 1 , Z ),"& " 318 (BC_2 , * , control , 0 ) ,"& " 317 (AC_2 , PCIETX_P52 , output3 , X , 318 , 0 , Z ),"& " 316 (BC_2 , * , control , 0 ) ,"& " 315 (AC_2 , PCIETX_P53 , output3 , X , 316 , 0 , Z ),"& " 314 (BC_2 , * , control , 0 ) ,"& " 313 (AC_2 , PCIETX_P54 , output3 , X , 314 , 0 , Z ),"& " 312 (BC_2 , * , control , 0 ) ,"& " 311 (AC_2 , PCIETX_P55 , output3 , X , 312 , 0 , Z ),"& " 310 (BC_4 , PCIERX_N52 , observe_only , X ) ,"& " 309 (BC_4 , PCIERX_P52 , observe_only , X ) ,"& " 308 (BC_4 , PCIERX_N53 , observe_only , X ) ,"& " 307 (BC_4 , PCIERX_P53 , observe_only , X ) ,"& " 306 (BC_4 , PCIERX_N54 , observe_only , X ) ,"& " 305 (BC_4 , PCIERX_P54 , observe_only , X ) ,"& " 304 (BC_4 , PCIERX_N55 , observe_only , X ) ,"& " 303 (BC_4 , PCIERX_P55 , observe_only , X ) ,"& " 302 (BC_2 , * , control , 1 ) ,"& " 301 (LV_BC_7 , GPIO2_7 , bidir , X , 302 , 1 , Z ),"& " 300 (BC_2 , * , control , 1 ) ,"& " 299 (LV_BC_7 , GPIO2_1 , bidir , X , 300 , 1 , Z ),"& " 298 (BC_2 , * , control , 1 ) ,"& " 297 (LV_BC_7 , SPARE_DIGIO_1 , bidir , X , 298 , 1 , Z ),"& " 296 (BC_2 , * , control , 1 ) ,"& " 295 (LV_BC_7 , GPIO2_5 , bidir , X , 296 , 1 , Z ),"& " 294 (BC_2 , * , control , 1 ) ,"& " 293 (LV_BC_7 , GPIO2_3 , bidir , X , 294 , 1 , Z ),"& " 292 (BC_2 , * , control , 1 ) ,"& " 291 (LV_BC_7 , SPARE_DIGIO_2 , bidir , X , 292 , 1 , Z ),"& " 290 (BC_2 , * , control , 1 ) ,"& " 289 (LV_BC_7 , NT_PERST4_N , bidir , X , 290 , 1 , Z ),"& " 288 (BC_2 , * , control , 1 ) ,"& " 287 (LV_BC_7 , NT_PERST2_N , bidir , X , 288 , 1 , Z ),"& " 286 (BC_4 , PCIERX_N48 , observe_only , X ) ,"& " 285 (BC_4 , PCIERX_P48 , observe_only , X ) ,"& " 284 (BC_4 , PCIERX_N49 , observe_only , X ) ,"& " 283 (BC_4 , PCIERX_P49 , observe_only , X ) ,"& " 282 (BC_4 , PCIERX_N50 , observe_only , X ) ,"& " 281 (BC_4 , PCIERX_P50 , observe_only , X ) ,"& " 280 (BC_4 , PCIERX_N51 , observe_only , X ) ,"& " 279 (BC_4 , PCIERX_P51 , observe_only , X ) ,"& " 278 (BC_2 , * , control , 0 ) ,"& " 277 (AC_2 , PCIETX_P48 , output3 , X , 278 , 0 , Z ),"& " 276 (BC_2 , * , control , 0 ) ,"& " 275 (AC_2 , PCIETX_P49 , output3 , X , 276 , 0 , Z ),"& " 274 (BC_2 , * , control , 0 ) ,"& " 273 (AC_2 , PCIETX_P50 , output3 , X , 274 , 0 , Z ),"& " 272 (BC_2 , * , control , 0 ) ,"& " 271 (AC_2 , PCIETX_P51 , output3 , X , 272 , 0 , Z ),"& " 270 (BC_2 , * , control , 1 ) ,"& " 269 (LV_BC_7 , QSPI_DQ0 , bidir , X , 270 , 1 , Z ),"& " 268 (BC_2 , * , control , 1 ) ,"& " 267 (LV_BC_7 , GPIO2_9 , bidir , X , 268 , 1 , Z ),"& " 266 (BC_2 , * , control , 1 ) ,"& " 265 (LV_BC_7 , GPIO4_5 , bidir , X , 266 , 1 , Z ),"& " 264 (BC_2 , * , control , 1 ) ,"& " 263 (LV_BC_7 , GPIO3_1 , bidir , X , 264 , 1 , Z ),"& " 262 (BC_2 , * , control , 1 ) ,"& " 261 (LV_BC_7 , QSPI_DQ1 , bidir , X , 262 , 1 , Z ),"& " 260 (BC_2 , * , control , 1 ) ,"& " 259 (LV_BC_7 , SPARE_DIGIO_3 , bidir , X , 260 , 1 , Z ),"& " 258 (BC_2 , * , control , 1 ) ,"& " 257 (LV_BC_7 , GPIO4_4 , bidir , X , 258 , 1 , Z ),"& " 256 (BC_2 , * , control , 1 ) ,"& " 255 (LV_BC_7 , SPARE_DIGIO_6 , bidir , X , 256 , 1 , Z ),"& " 254 (BC_2 , * , control , 1 ) ,"& " 253 (LV_BC_7 , QSPI_CS_N , bidir , X , 254 , 1 , Z ),"& " 252 (BC_2 , * , control , 1 ) ,"& " 251 (LV_BC_7 , SPARE_DIGIO_4 , bidir , X , 252 , 1 , Z ),"& " 250 (BC_2 , * , control , 1 ) ,"& " 249 (LV_BC_7 , QSPI_CLK , bidir , X , 250 , 1 , Z ),"& " 248 (BC_2 , * , control , 1 ) ,"& " 247 (LV_BC_7 , SPARE_DIGIO_7 , bidir , X , 248 , 1 , Z ),"& " 246 (BC_2 , * , control , 1 ) ,"& " 245 (LV_BC_7 , GPIO0_0 , bidir , X , 246 , 1 , Z ),"& " 244 (BC_2 , * , control , 1 ) ,"& " 243 (LV_BC_7 , SMB_M_DATA , bidir , X , 244 , 1 , Z ),"& " 242 (BC_2 , * , control , 1 ) ,"& " 241 (LV_BC_7 , SMB_M_ATTN_N , bidir , X , 242 , 1 , Z ),"& " 240 (BC_2 , * , control , 1 ) ,"& " 239 (LV_BC_7 , SPARE_DIGIO_8 , bidir , X , 240 , 1 , Z ),"& " 238 (BC_2 , * , control , 1 ) ,"& " 237 (LV_BC_7 , GPIO0_1 , bidir , X , 238 , 1 , Z ),"& " 236 (BC_2 , * , control , 1 ) ,"& " 235 (LV_BC_7 , SMB_M_CLK , bidir , X , 236 , 1 , Z ),"& " 234 (BC_2 , * , control , 1 ) ,"& " 233 (LV_BC_7 , GPIO2_6 , bidir , X , 234 , 1 , Z ),"& " 232 (BC_2 , * , control , 1 ) ,"& " 231 (LV_BC_7 , SPARE_DIGIO_9 , bidir , X , 232 , 1 , Z ),"& " 230 (BC_2 , * , control , 1 ) ,"& " 229 (LV_BC_7 , GPIO0_5 , bidir , X , 230 , 1 , Z ),"& " 228 (BC_2 , * , control , 1 ) ,"& " 227 (LV_BC_7 , INTA6_N , bidir , X , 228 , 1 , Z ),"& " 226 (BC_2 , * , control , 1 ) ,"& " 225 (LV_BC_7 , STR_CLK_SEL , bidir , X , 226 , 1 , Z ),"& " 224 (BC_2 , * , control , 1 ) ,"& " 223 (LV_BC_7 , SPARE_DIGIO_10 , bidir , X , 224 , 1 , Z ),"& " 222 (BC_2 , * , control , 1 ) ,"& " 221 (LV_BC_7 , GPIO0_2 , bidir , X , 222 , 1 , Z ),"& " 220 (BC_2 , * , control , 1 ) ,"& " 219 (LV_BC_7 , GPIO4_6 , bidir , X , 220 , 1 , Z ),"& " 218 (BC_2 , * , control , 1 ) ,"& " 217 (LV_BC_7 , STR_INIT_SEC1 , bidir , X , 218 , 1 , Z ),"& " 216 (BC_2 , * , control , 1 ) ,"& " 215 (LV_BC_7 , GPIO4_9 , bidir , X , 216 , 1 , Z ),"& " 214 (BC_2 , * , control , 1 ) ,"& " 213 (LV_BC_7 , GPIO0_3 , bidir , X , 214 , 1 , Z ),"& " 212 (BC_2 , * , control , 1 ) ,"& " 211 (LV_BC_7 , GPIO0_4 , bidir , X , 212 , 1 , Z ),"& " 210 (BC_2 , * , control , 1 ) ,"& " 209 (LV_BC_7 , NT_PERST6_N , bidir , X , 210 , 1 , Z ),"& " 208 (BC_2 , * , control , 1 ) ,"& " 207 (LV_BC_7 , GPIO0_7 , bidir , X , 208 , 1 , Z ),"& " 206 (BC_2 , * , control , 1 ) ,"& " 205 (LV_BC_7 , GPIO0_6 , bidir , X , 206 , 1 , Z ),"& " 204 (BC_2 , * , control , 1 ) ,"& " 203 (LV_BC_7 , STR_BLK0_PORT_CNFG0 , bidir , X , 204 , 1 , Z ),"& " 202 (BC_2 , * , control , 1 ) ,"& " 201 (LV_BC_7 , GPIO0_9 , bidir , X , 202 , 1 , Z ),"& " 200 (BC_2 , * , control , 1 ) ,"& " 199 (LV_BC_7 , GPIO0_8 , bidir , X , 200 , 1 , Z ),"& " 198 (BC_2 , * , control , 1 ) ,"& " 197 (LV_BC_7 , NT_PERST0_N , bidir , X , 198 , 1 , Z ),"& " 196 (BC_4 , PCIERX_N15 , observe_only , X ) ,"& " 195 (BC_4 , PCIERX_P15 , observe_only , X ) ,"& " 194 (BC_4 , PCIERX_N14 , observe_only , X ) ,"& " 193 (BC_4 , PCIERX_P14 , observe_only , X ) ,"& " 192 (BC_4 , PCIERX_N13 , observe_only , X ) ,"& " 191 (BC_4 , PCIERX_P13 , observe_only , X ) ,"& " 190 (BC_4 , PCIERX_N12 , observe_only , X ) ,"& " 189 (BC_4 , PCIERX_P12 , observe_only , X ) ,"& " 188 (BC_2 , * , control , 0 ) ,"& " 187 (AC_2 , PCIETX_P15 , output3 , X , 188 , 0 , Z ),"& " 186 (BC_2 , * , control , 0 ) ,"& " 185 (AC_2 , PCIETX_P14 , output3 , X , 186 , 0 , Z ),"& " 184 (BC_2 , * , control , 0 ) ,"& " 183 (AC_2 , PCIETX_P13 , output3 , X , 184 , 0 , Z ),"& " 182 (BC_2 , * , control , 0 ) ,"& " 181 (AC_2 , PCIETX_P12 , output3 , X , 182 , 0 , Z ),"& " 180 (BC_4 , PCIERX_N11 , observe_only , X ) ,"& " 179 (BC_4 , PCIERX_P11 , observe_only , X ) ,"& " 178 (BC_4 , PCIERX_N10 , observe_only , X ) ,"& " 177 (BC_4 , PCIERX_P10 , observe_only , X ) ,"& " 176 (BC_4 , PCIERX_N9 , observe_only , X ) ,"& " 175 (BC_4 , PCIERX_P9 , observe_only , X ) ,"& " 174 (BC_4 , PCIERX_N8 , observe_only , X ) ,"& " 173 (BC_4 , PCIERX_P8 , observe_only , X ) ,"& " 172 (BC_2 , * , control , 0 ) ,"& " 171 (AC_2 , PCIETX_P11 , output3 , X , 172 , 0 , Z ),"& " 170 (BC_2 , * , control , 0 ) ,"& " 169 (AC_2 , PCIETX_P10 , output3 , X , 170 , 0 , Z ),"& " 168 (BC_2 , * , control , 0 ) ,"& " 167 (AC_2 , PCIETX_P9 , output3 , X , 168 , 0 , Z ),"& " 166 (BC_2 , * , control , 0 ) ,"& " 165 (AC_2 , PCIETX_P8 , output3 , X , 166 , 0 , Z ),"& " 164 (BC_2 , * , control , 0 ) ,"& " 163 (AC_2 , PCIETX_P4 , output3 , X , 164 , 0 , Z ),"& " 162 (BC_2 , * , control , 0 ) ,"& " 161 (AC_2 , PCIETX_P5 , output3 , X , 162 , 0 , Z ),"& " 160 (BC_2 , * , control , 0 ) ,"& " 159 (AC_2 , PCIETX_P6 , output3 , X , 160 , 0 , Z ),"& " 158 (BC_2 , * , control , 0 ) ,"& " 157 (AC_2 , PCIETX_P7 , output3 , X , 158 , 0 , Z ),"& " 156 (BC_4 , PCIERX_N4 , observe_only , X ) ,"& " 155 (BC_4 , PCIERX_P4 , observe_only , X ) ,"& " 154 (BC_4 , PCIERX_N5 , observe_only , X ) ,"& " 153 (BC_4 , PCIERX_P5 , observe_only , X ) ,"& " 152 (BC_4 , PCIERX_N6 , observe_only , X ) ,"& " 151 (BC_4 , PCIERX_P6 , observe_only , X ) ,"& " 150 (BC_4 , PCIERX_N7 , observe_only , X ) ,"& " 149 (BC_4 , PCIERX_P7 , observe_only , X ) ,"& " 148 (BC_2 , * , control , 0 ) ,"& " 147 (AC_2 , PCIETX_P0 , output3 , X , 148 , 0 , Z ),"& " 146 (BC_2 , * , control , 0 ) ,"& " 145 (AC_2 , PCIETX_P1 , output3 , X , 146 , 0 , Z ),"& " 144 (BC_2 , * , control , 0 ) ,"& " 143 (AC_2 , PCIETX_P2 , output3 , X , 144 , 0 , Z ),"& " 142 (BC_2 , * , control , 0 ) ,"& " 141 (AC_2 , PCIETX_P3 , output3 , X , 142 , 0 , Z ),"& " 140 (BC_4 , PCIERX_N0 , observe_only , X ) ,"& " 139 (BC_4 , PCIERX_P0 , observe_only , X ) ,"& " 138 (BC_4 , PCIERX_N1 , observe_only , X ) ,"& " 137 (BC_4 , PCIERX_P1 , observe_only , X ) ,"& " 136 (BC_4 , PCIERX_N2 , observe_only , X ) ,"& " 135 (BC_4 , PCIERX_P2 , observe_only , X ) ,"& " 134 (BC_4 , PCIERX_N3 , observe_only , X ) ,"& " 133 (BC_4 , PCIERX_P3 , observe_only , X ) ,"& " 132 (BC_2 , * , control , 1 ) ,"& " 131 (LV_BC_7 , STR_BLK0_PORT_CNFG1 , bidir , X , 132 , 1 , Z ),"& " 130 (BC_2 , * , control , 1 ) ,"& " 129 (LV_BC_7 , GPIO1_1 , bidir , X , 130 , 1 , Z ),"& " 128 (BC_2 , * , control , 1 ) ,"& " 127 (LV_BC_7 , GPIO3_4 , bidir , X , 128 , 1 , Z ),"& " 126 (BC_2 , * , control , 1 ) ,"& " 125 (LV_BC_7 , GPIO1_5 , bidir , X , 126 , 1 , Z ),"& " 124 (BC_2 , * , control , 1 ) ,"& " 123 (LV_BC_7 , GPIO1_9 , bidir , X , 124 , 1 , Z ),"& " 122 (BC_2 , * , control , 1 ) ,"& " 121 (LV_BC_7 , GPIO4_8 , bidir , X , 122 , 1 , Z ),"& " 120 (BC_2 , * , control , 1 ) ,"& " 119 (LV_BC_7 , GPIO1_7 , bidir , X , 120 , 1 , Z ),"& " 118 (BC_2 , * , control , 1 ) ,"& " 117 (LV_BC_7 , GPIO1_8 , bidir , X , 118 , 1 , Z ),"& " 116 (BC_2 , * , control , 1 ) ,"& " 115 (LV_BC_7 , GPIO1_4 , bidir , X , 116 , 1 , Z ),"& " 114 (BC_2 , * , control , 1 ) ,"& " 113 (LV_BC_7 , GPIO1_2 , bidir , X , 114 , 1 , Z ),"& " 112 (BC_2 , * , control , 1 ) ,"& " 111 (LV_BC_7 , PERST0_N , bidir , X , 112 , 1 , Z ),"& " 110 (BC_2 , * , control , 1 ) ,"& " 109 (LV_BC_7 , GPIO1_0 , bidir , X , 110 , 1 , Z ),"& " 108 (BC_2 , * , control , 1 ) ,"& " 107 (LV_BC_7 , GPIO1_3 , bidir , X , 108 , 1 , Z ),"& " 106 (BC_2 , * , control , 1 ) ,"& " 105 (LV_BC_7 , SPARE_DIGIO_16 , bidir , X , 106 , 1 , Z ),"& " 104 (BC_2 , * , control , 1 ) ,"& " 103 (LV_BC_7 , SMB_S_ATTN_N , bidir , X , 104 , 1 , Z ),"& " 102 (BC_2 , * , control , 1 ) ,"& " 101 (LV_BC_7 , GPIO3_2 , bidir , X , 102 , 1 , Z ),"& " 100 (BC_2 , * , control , 1 ) ,"& " 99 (LV_BC_7 , GPIO1_6 , bidir , X , 100 , 1 , Z ),"& " 98 (BC_2 , * , control , 1 ) ,"& " 97 (LV_BC_7 , SPARE_DIGIO_15 , bidir , X , 98 , 1 , Z ),"& " 96 (BC_2 , * , control , 1 ) ,"& " 95 (LV_BC_7 , PERST2_N , bidir , X , 96 , 1 , Z ),"& " 94 (BC_2 , * , control , 1 ) ,"& " 93 (LV_BC_7 , INTA4_N , bidir , X , 94 , 1 , Z ),"& " 92 (BC_2 , * , control , 1 ) ,"& " 91 (LV_BC_7 , INTA2_N , bidir , X , 92 , 1 , Z ),"& " 90 (BC_2 , * , control , 1 ) ,"& " 89 (LV_BC_7 , SPARE_DIGIO_14 , bidir , X , 90 , 1 , Z ),"& " 88 (BC_2 , * , control , 1 ) ,"& " 87 (LV_BC_7 , PERST4_N , bidir , X , 88 , 1 , Z ),"& " 86 (BC_2 , * , control , 1 ) ,"& " 85 (LV_BC_7 , PERST6_N , bidir , X , 86 , 1 , Z ),"& " 84 (BC_2 , * , control , 1 ) ,"& " 83 (LV_BC_7 , STR_INIT_SEL1 , bidir , X , 84 , 1 , Z ),"& " 82 (BC_2 , * , control , 1 ) ,"& " 81 (LV_BC_7 , SPARE_DIGIO_13 , bidir , X , 82 , 1 , Z ),"& " 80 (BC_2 , * , control , 1 ) ,"& " 79 (LV_BC_7 , GPIO4_7 , bidir , X , 80 , 1 , Z ),"& " 78 (BC_2 , * , control , 1 ) ,"& " 77 (LV_BC_7 , GPIO3_3 , bidir , X , 78 , 1 , Z ),"& " 76 (BC_2 , * , control , 1 ) ,"& " 75 (LV_BC_7 , GPIO4_2 , bidir , X , 76 , 1 , Z ),"& " 74 (BC_2 , * , control , 1 ) ,"& " 73 (LV_BC_7 , SPARE_DIGIO_12 , bidir , X , 74 , 1 , Z ),"& " 72 (BC_2 , * , control , 1 ) ,"& " 71 (LV_BC_7 , GPIO4_1 , bidir , X , 72 , 1 , Z ),"& " 70 (BC_2 , * , control , 1 ) ,"& " 69 (LV_BC_7 , SPARE_DIGIO_11 , bidir , X , 70 , 1 , Z ),"& " 68 (BC_2 , * , control , 1 ) ,"& " 67 (LV_BC_7 , GPIO4_3 , bidir , X , 68 , 1 , Z ),"& " 66 (BC_2 , * , control , 0 ) ,"& " 65 (AC_2 , PCIETX_P32 , output3 , X , 66 , 0 , Z ),"& " 64 (BC_2 , * , control , 0 ) ,"& " 63 (AC_2 , PCIETX_P33 , output3 , X , 64 , 0 , Z ),"& " 62 (BC_2 , * , control , 0 ) ,"& " 61 (AC_2 , PCIETX_P34 , output3 , X , 62 , 0 , Z ),"& " 60 (BC_2 , * , control , 0 ) ,"& " 59 (AC_2 , PCIETX_P35 , output3 , X , 60 , 0 , Z ),"& " 58 (BC_4 , PCIERX_N32 , observe_only , X ) ,"& " 57 (BC_4 , PCIERX_P32 , observe_only , X ) ,"& " 56 (BC_4 , PCIERX_N33 , observe_only , X ) ,"& " 55 (BC_4 , PCIERX_P33 , observe_only , X ) ,"& " 54 (BC_4 , PCIERX_N34 , observe_only , X ) ,"& " 53 (BC_4 , PCIERX_P34 , observe_only , X ) ,"& " 52 (BC_4 , PCIERX_N35 , observe_only , X ) ,"& " 51 (BC_4 , PCIERX_P35 , observe_only , X ) ,"& " 50 (BC_2 , * , control , 1 ) ,"& " 49 (LV_BC_7 , GPIO3_0 , bidir , X , 50 , 1 , Z ),"& " 48 (BC_2 , * , control , 1 ) ,"& " 47 (LV_BC_7 , QSPI_DQ2 , bidir , X , 48 , 1 , Z ),"& " 46 (BC_2 , * , control , 1 ) ,"& " 45 (LV_BC_7 , GPIO3_7 , bidir , X , 46 , 1 , Z ),"& " 44 (BC_2 , * , control , 1 ) ,"& " 43 (LV_BC_7 , GPIO3_6 , bidir , X , 44 , 1 , Z ),"& " 42 (BC_2 , * , control , 1 ) ,"& " 41 (LV_BC_7 , SMB_S_ADDR2 , bidir , X , 42 , 1 , Z ),"& " 40 (BC_4 , RESET_N , observe_only , X ) ,"& " 39 (BC_2 , * , control , 1 ) ,"& " 38 (LV_BC_7 , QSPI_DQ3 , bidir , X , 39 , 1 , Z ),"& " 37 (BC_2 , * , control , 1 ) ,"& " 36 (LV_BC_7 , STR_INIT_VP1 , bidir , X , 37 , 1 , Z ),"& " 35 (BC_4 , PCIERX_N36 , observe_only , X ) ,"& " 34 (BC_4 , PCIERX_P36 , observe_only , X ) ,"& " 33 (BC_4 , PCIERX_N37 , observe_only , X ) ,"& " 32 (BC_4 , PCIERX_P37 , observe_only , X ) ,"& " 31 (BC_4 , PCIERX_N38 , observe_only , X ) ,"& " 30 (BC_4 , PCIERX_P38 , observe_only , X ) ,"& " 29 (BC_4 , PCIERX_N39 , observe_only , X ) ,"& " 28 (BC_4 , PCIERX_P39 , observe_only , X ) ,"& " 27 (BC_2 , * , control , 0 ) ,"& " 26 (AC_2 , PCIETX_P36 , output3 , X , 27 , 0 , Z ),"& " 25 (BC_2 , * , control , 0 ) ,"& " 24 (AC_2 , PCIETX_P37 , output3 , X , 25 , 0 , Z ),"& " 23 (BC_2 , * , control , 0 ) ,"& " 22 (AC_2 , PCIETX_P38 , output3 , X , 23 , 0 , Z ),"& " 21 (BC_2 , * , control , 0 ) ,"& " 20 (AC_2 , PCIETX_P39 , output3 , X , 21 , 0 , Z ),"& " 19 (BC_2 , * , control , 1 ) ,"& " 18 (LV_BC_7 , SMB_S_CLK , bidir , X , 19 , 1 , Z ),"& " 17 (BC_2 , * , control , 1 ) ,"& " 16 (LV_BC_7 , INTA0_N , bidir , X , 17 , 1 , Z ),"& " 15 (BC_2 , * , control , 1 ) ,"& " 14 (LV_BC_7 , SMB_S_DATA , bidir , X , 15 , 1 , Z ),"& " 13 (BC_2 , * , control , 1 ) ,"& " 12 (LV_BC_7 , STR_BLK3_PORT_CNFG1 , bidir , X , 13 , 1 , Z ),"& " 11 (BC_2 , * , control , 1 ) ,"& " 10 (LV_BC_7 , STR_INIT_VP0 , bidir , X , 11 , 1 , Z ),"& " 9 (BC_2 , * , control , 1 ) ,"& " 8 (LV_BC_7 , GPIO3_8 , bidir , X , 9 , 1 , Z ),"& " 7 (BC_2 , * , control , 1 ) ,"& " 6 (LV_BC_7 , GPIO4_0 , bidir , X , 7 , 1 , Z ),"& " 5 (BC_2 , * , control , 1 ) ,"& " 4 (LV_BC_7 , IOEXTENDER_ATTN_N , bidir , X , 5 , 1 , Z ),"& " 3 (BC_2 , * , control , 1 ) ,"& " 2 (LV_BC_7 , STR_BLK3_PORT_CNFG0 , bidir , X , 3 , 1 , Z ),"& " 1 (BC_2 , * , control , 1 ) ,"& " 0 (LV_BC_7 , SMB_S_ADDR0 , bidir , X , 1 , 1 , Z ) "; attribute AIO_COMPONENT_CONFORMANCE of ATHENA_TOP: entity is "STD_1149_6_2003"; attribute AIO_EXTEST_Pulse_Execution of ATHENA_TOP: entity is "Wait_Duration 1e-06" ; attribute AIO_EXTEST_Train_Execution of ATHENA_TOP: entity is "train 10, maximum_time 1e-06" ; attribute AIO_Pin_Behavior of ATHENA_TOP: entity is "PCIERX_P40[411] : HP_Time=9.00e-09;"& "PCIERX_P41[409] : HP_Time=9.00e-09;"& "PCIERX_P42[407] : HP_Time=9.00e-09;"& "PCIERX_P43[405] : HP_Time=9.00e-09;"& "PCIETX_P40 ;"& "PCIETX_P41 ;"& "PCIETX_P42 ;"& "PCIETX_P43 ;"& "PCIERX_P44[395] : HP_Time=9.00e-09;"& "PCIERX_P45[393] : HP_Time=9.00e-09;"& "PCIERX_P46[391] : HP_Time=9.00e-09;"& "PCIERX_P47[389] : HP_Time=9.00e-09;"& "PCIETX_P44 ;"& "PCIETX_P45 ;"& "PCIETX_P46 ;"& "PCIETX_P47 ;"& "PCIETX_P60 ;"& "PCIETX_P61 ;"& "PCIETX_P62 ;"& "PCIETX_P63 ;"& "PCIERX_P60[371] : HP_Time=9.00e-09;"& "PCIERX_P61[369] : HP_Time=9.00e-09;"& "PCIERX_P62[367] : HP_Time=9.00e-09;"& "PCIERX_P63[365] : HP_Time=9.00e-09;"& "PCIETX_P56 ;"& "PCIETX_P57 ;"& "PCIETX_P58 ;"& "PCIETX_P59 ;"& "PCIERX_P56[355] : HP_Time=9.00e-09;"& "PCIERX_P57[353] : HP_Time=9.00e-09;"& "PCIERX_P58[351] : HP_Time=9.00e-09;"& "PCIERX_P59[349] : HP_Time=9.00e-09;"& "PCIETX_P52 ;"& "PCIETX_P53 ;"& "PCIETX_P54 ;"& "PCIETX_P55 ;"& "PCIERX_P52[309] : HP_Time=9.00e-09;"& "PCIERX_P53[307] : HP_Time=9.00e-09;"& "PCIERX_P54[305] : HP_Time=9.00e-09;"& "PCIERX_P55[303] : HP_Time=9.00e-09;"& "PCIERX_P48[285] : HP_Time=9.00e-09;"& "PCIERX_P49[283] : HP_Time=9.00e-09;"& "PCIERX_P50[281] : HP_Time=9.00e-09;"& "PCIERX_P51[279] : HP_Time=9.00e-09;"& "PCIETX_P48 ;"& "PCIETX_P49 ;"& "PCIETX_P50 ;"& "PCIETX_P51 ;"& "PCIERX_P15[195] : HP_Time=9.00e-09;"& "PCIERX_P14[193] : HP_Time=9.00e-09;"& "PCIERX_P13[191] : HP_Time=9.00e-09;"& "PCIERX_P12[189] : HP_Time=9.00e-09;"& "PCIETX_P15 ;"& "PCIETX_P14 ;"& "PCIETX_P13 ;"& "PCIETX_P12 ;"& "PCIERX_P11[179] : HP_Time=9.00e-09;"& "PCIERX_P10[177] : HP_Time=9.00e-09;"& "PCIERX_P9[175] : HP_Time=9.00e-09;"& "PCIERX_P8[173] : HP_Time=9.00e-09;"& "PCIETX_P11 ;"& "PCIETX_P10 ;"& "PCIETX_P9 ;"& "PCIETX_P8 ;"& "PCIETX_P4 ;"& "PCIETX_P5 ;"& "PCIETX_P6 ;"& "PCIETX_P7 ;"& "PCIERX_P4[155] : HP_Time=9.00e-09;"& "PCIERX_P5[153] : HP_Time=9.00e-09;"& "PCIERX_P6[151] : HP_Time=9.00e-09;"& "PCIERX_P7[149] : HP_Time=9.00e-09;"& "PCIETX_P0 ;"& "PCIETX_P1 ;"& "PCIETX_P2 ;"& "PCIETX_P3 ;"& "PCIERX_P0[139] : HP_Time=9.00e-09;"& "PCIERX_P1[137] : HP_Time=9.00e-09;"& "PCIERX_P2[135] : HP_Time=9.00e-09;"& "PCIERX_P3[133] : HP_Time=9.00e-09;"& "PCIETX_P32 ;"& "PCIETX_P33 ;"& "PCIETX_P34 ;"& "PCIETX_P35 ;"& "PCIERX_P32[57] : HP_Time=9.00e-09;"& "PCIERX_P33[55] : HP_Time=9.00e-09;"& "PCIERX_P34[53] : HP_Time=9.00e-09;"& "PCIERX_P35[51] : HP_Time=9.00e-09;"& "PCIERX_P36[34] : HP_Time=9.00e-09;"& "PCIERX_P37[32] : HP_Time=9.00e-09;"& "PCIERX_P38[30] : HP_Time=9.00e-09;"& "PCIERX_P39[28] : HP_Time=9.00e-09;"& "PCIETX_P36 ;"& "PCIETX_P37 ;"& "PCIETX_P38 ;"& "PCIETX_P39 "; end ATHENA_TOP;