-- ********************************************************************************************************************* -- BSDL file for design AT91SAM9RL64 -- Created by Synopsys Version Z-2007.03-SP3 (Jul 23, 2007) -- Designer: -- Company: -- Date: Thu Feb 28 11:01:59 2008 -- ********************************************************************************************************************* ---------------------------------------------------------------------------- -- File checked with http://www.asset-intertech.com/bsdl_service -- -- Job Status: Pass -- -- File Name: 59011C_LFBGA217.bsdl -- Timestamp: Thursday, February 28, 2008 4:07 AM -- -- Results: Entity name: AT91SAM9RL64 -- IEEE Std 1149.1-2001 (Version 2.0) -- Packaging option selected is R_LFBGA217_I_333X275. -- Inputs = 1 -- Outputs = 10 -- Bidirectionals = 156 -- Instruction Reg Length = 3 -- Boundary Reg Length = 462 -- -- BSDL compilation of 688 lines completed without errors. ---------------------------------------------------------------------------- entity AT91SAM9RL64 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "R_LFBGA217_I_333x275"); -- This section declares all the ports in the design. port ( bms : in bit; jtagsel : in bit; ntrst : in bit; tck : in bit; tdi : in bit; tms : in bit; cas : out bit; ncs0 : out bit; ncs1_sdcs : out bit; nrd_cfoe : out bit; nrst : inout bit; nwr0_nwe_cfwe : inout bit; nwr1_nbs1_cfior : inout bit; nwr3_nbs3_cfiow : inout bit; ras : out bit; sda10 : out bit; sdck : buffer bit; sdcke : out bit; sdwe : out bit; a : inout bit_vector (0 to 17); d : inout bit_vector (0 to 15); pa : inout bit_vector (0 to 31); pb : inout bit_vector (0 to 31); pc : inout bit_vector (0 to 31); pd : inout bit_vector (0 to 21); tdo : out bit; rtck : buffer bit; GNDANA : linkage bit; GNDBU : linkage bit; GNDPLLA : linkage bit; GNDPLLB : linkage bit; VDDANA : linkage bit; VDDBU : linkage bit; VDDPLLA : linkage bit; VDDPLLB : linkage bit; VDDUTMI : linkage bit; advref : linkage bit; dfsdm : linkage bit; dfsdp : linkage bit; dhsdm : linkage bit; dhsdp : linkage bit; lft_plla : linkage bit; osc12m_xin : linkage bit; osc12m_xout : linkage bit; osc32k_xin : linkage bit; osc32k_xout : linkage bit; shdn : linkage bit; tst : linkage bit; vbg : linkage bit; wkup : linkage bit; GND : linkage bit_vector (1 to 8); VDDCORE : linkage bit_vector (1 to 4); VDDIOM : linkage bit_vector (1 to 3); VDDIOP : linkage bit_vector (1 to 3) ); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of AT91SAM9RL64: entity is "STD_1149_1_2001"; attribute PIN_MAP of AT91SAM9RL64: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is extracted from the port-to-pin map file that -- was read in using the "read_pin_map" command. constant R_LFBGA217_I_333x275: PIN_MAP_STRING := "bms : D8," & "jtagsel : D6," & "ntrst : D7," & "tck : C8," & "tdi : C9," & "tms : B9," & "cas : P6," & "ncs0 : E3," & "ncs1_sdcs : E2," & "nrd_cfoe : F1," & "nrst : A9," & "nwr0_nwe_cfwe : F3," & "nwr1_nbs1_cfior : D2," & "nwr3_nbs3_cfiow : E4," & "ras : T6," & "sda10 : R6," & "sdck : U8," & "sdcke : P8," & "sdwe : U6," & "a : (R1, P3, R2, T1, U1, T2, U2, R3, T3, U3, R4, P4, T4, U4, R5, P5, T5, U5)," & "d : (R7, P7, T7, U7, T8, P9, R9, T9, P10, R10, T10, U9, U10, U11, T11, P11)," & "pa : (F15, F14, F16, F17, E17, E16, C17, C16, D15, B17, A15, C14, D14, B14, A14, D13, C13, " & "T13, U13, T14, U14, B13, A13, D12, C12, B12, A12, C11, B11, A11, D10, C10)," & "pb : (P13, R14, F2, F4, G4, G3, H4, H3, H1, H2, J4, J3, J1, J2, K1, K2, K4, K3, L1, L2, L4, " & "L3, M1, M2, M4, M3, N1, N2, N4, N3, P1, P2)," & "pc : (P12, R13, T15, T16, T17, R15, R16, R17, P14, P15, P16, P17, N15, N14, N16, N17, M15, " & "M14, M16, M17, L15, L14, L16, L17, K15, K14, K16, K17, K10, J10, J16, J17)," & "pd : (J15, J14, H16, H17, H10, H15, U15, U16, H14, G17, G16, G15, G14, D16, E15, E14, D17, " & "A17, C15, B16, A16, B15)," & "tdo : D9," & "rtck : A10," & "GNDANA : U17," & "GNDBU : C7," & "GNDPLLA : E1," & "GNDPLLB : A6," & "VDDANA : T12," & "VDDBU : C5," & "VDDPLLA : C1," & "VDDPLLB : A3," & "VDDUTMI : C2," & "advref : U12," & "dfsdm : A1," & "dfsdp : B1," & "dhsdm : B2," & "dhsdp : A2," & "lft_plla : D1," & "osc12m_xin : A4," & "osc12m_xout : A5," & "osc32k_xin : B6," & "osc32k_xout : A7," & "shdn : D5," & "tst : B7," & "vbg : B3," & "wkup : C6," & "GND : (G1, D4, D11, B8, A8, C3, C4, D3)," & "VDDCORE : (J8, B10, K8, H8)," & "VDDIOM : (R8, R12, G2)," & "VDDIOP : (J9, K9, H9)"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of tck : signal is (1.000000e+06, BOTH); attribute TAP_SCAN_IN of tdi : signal is true; attribute TAP_SCAN_MODE of tms : signal is true; attribute TAP_SCAN_OUT of tdo : signal is true; attribute TAP_SCAN_RESET of ntrst: signal is true; -- Specifies the compliance enable patterns for the design. It lists a set of design ports and the values that they -- should be set to, in order to enable compliance to IEEE Std 1149.1 attribute COMPLIANCE_PATTERNS of AT91SAM9RL64: entity is "(jtagsel) (1)"; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of AT91SAM9RL64: entity is 3; -- Specifies the boundary-scan instructions implemented in the design and their opcodes. attribute INSTRUCTION_OPCODE of AT91SAM9RL64: entity is "BYPASS (111, 100, 110)," & "EXTEST (000, 011)," & "SAMPLE (001)," & "PRELOAD (001)," & "IDCODE (010)"; -- Specifies the bit pattern that is loaded into the instruction register when the TAP controller passes through the -- Capture-IR state. The standard mandates that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of AT91SAM9RL64: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during the IDCODE instruction when the TAP -- controller passes through the Capture-DR state. attribute IDCODE_REGISTER of AT91SAM9RL64: entity is "0000" & -- 4-bit version number "0101101100100000" & -- 16-bit part number "00000011111" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI and TDO for each implemented instruction. attribute REGISTER_ACCESS of AT91SAM9RL64: entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of AT91SAM9RL64: entity is 462; -- The following list specifies the characteristics of each cell in the boundary scan register from TDI to TDO. The -- following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port name. -- function: Is the function of the cell as defined by the standard. Is one of input, output2, output3, bidir, -- control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with for safe operation when the software might -- otherwise choose a random value. -- ccell : The control cell number. Specifies the control cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to disable the output enable for the -- corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is disabled. attribute BOUNDARY_REGISTER of AT91SAM9RL64: entity is -- -- num cell port function safe [ccell disval rslt] -- "461 (BC_0, *, internal, X), " & "460 (BC_1, pd(0), input, X), " & "459 (BC_1, pd(0), output3, X, 458, 1, Z), " & "458 (BC_1, *, controlr, 1), " & "457 (BC_1, pd(1), input, X), " & "456 (BC_1, pd(1), output3, X, 455, 1, Z), " & "455 (BC_1, *, controlr, 1), " & "454 (BC_1, pd(2), input, X), " & "453 (BC_1, pd(2), output3, X, 452, 1, Z), " & "452 (BC_1, *, controlr, 1), " & "451 (BC_1, pd(3), input, X), " & "450 (BC_1, pd(3), output3, X, 449, 1, Z), " & "449 (BC_1, *, controlr, 1), " & "448 (BC_1, pd(4), input, X), " & "447 (BC_1, pd(4), output3, X, 446, 1, Z), " & "446 (BC_1, *, controlr, 1), " & "445 (BC_1, pd(5), input, X), " & "444 (BC_1, pd(5), output3, X, 443, 1, Z), " & "443 (BC_1, *, controlr, 1), " & "442 (BC_1, pd(6), input, X), " & "441 (BC_1, pd(6), output3, X, 440, 1, Z), " & "440 (BC_1, *, controlr, 1), " & "439 (BC_1, pd(7), input, X), " & "438 (BC_1, pd(7), output3, X, 437, 1, Z), " & "437 (BC_1, *, controlr, 1), " & "436 (BC_1, pd(8), input, X), " & "435 (BC_1, pd(8), output3, X, 434, 1, Z), " & "434 (BC_1, *, controlr, 1), " & "433 (BC_1, pd(9), input, X), " & "432 (BC_1, pd(9), output3, X, 431, 1, Z), " & "431 (BC_1, *, controlr, 1), " & "430 (BC_1, pd(10), input, X), " & "429 (BC_1, pd(10), output3, X, 428, 1, Z), " & "428 (BC_1, *, controlr, 1), " & "427 (BC_1, pd(11), input, X), " & "426 (BC_1, pd(11), output3, X, 425, 1, Z), " & "425 (BC_1, *, controlr, 1), " & "424 (BC_1, pd(12), input, X), " & "423 (BC_1, pd(12), output3, X, 422, 1, Z), " & "422 (BC_1, *, controlr, 1), " & "421 (BC_1, pd(13), input, X), " & "420 (BC_1, pd(13), output3, X, 419, 1, Z), " & "419 (BC_1, *, controlr, 1), " & "418 (BC_1, pd(14), input, X), " & "417 (BC_1, pd(14), output3, X, 416, 1, Z), " & "416 (BC_1, *, controlr, 1), " & "415 (BC_1, pd(15), input, X), " & "414 (BC_1, pd(15), output3, X, 413, 1, Z), " & "413 (BC_1, *, controlr, 1), " & "412 (BC_1, pd(16), input, X), " & "411 (BC_1, pd(16), output3, X, 410, 1, Z), " & "410 (BC_1, *, controlr, 1), " & "409 (BC_1, pd(17), input, X), " & "408 (BC_1, pd(17), output3, X, 407, 1, Z), " & "407 (BC_1, *, controlr, 1), " & "406 (BC_1, pd(18), input, X), " & "405 (BC_1, pd(18), output3, X, 404, 1, Z), " & "404 (BC_1, *, controlr, 1), " & "403 (BC_1, pd(19), input, X), " & "402 (BC_1, pd(19), output3, X, 401, 1, Z), " & "401 (BC_1, *, controlr, 1), " & "400 (BC_1, pd(20), input, X), " & "399 (BC_1, pd(20), output3, X, 398, 1, Z), " & "398 (BC_1, *, controlr, 1), " & "397 (BC_1, pd(21), input, X), " & "396 (BC_1, pd(21), output3, X, 395, 1, Z), " & "395 (BC_1, *, controlr, 1), " & "394 (BC_1, pc(0), input, X), " & "393 (BC_1, pc(0), output3, X, 392, 1, Z), " & "392 (BC_1, *, controlr, 1), " & "391 (BC_1, pc(1), input, X), " & "390 (BC_1, pc(1), output3, X, 389, 1, Z), " & "389 (BC_1, *, controlr, 1), " & "388 (BC_1, pc(2), input, X), " & "387 (BC_1, pc(2), output3, X, 386, 1, Z), " & "386 (BC_1, *, controlr, 1), " & "385 (BC_1, pc(3), input, X), " & "384 (BC_1, pc(3), output3, X, 383, 1, Z), " & "383 (BC_1, *, controlr, 1), " & "382 (BC_1, pc(4), input, X), " & "381 (BC_1, pc(4), output3, X, 380, 1, Z), " & "380 (BC_1, *, controlr, 1), " & "379 (BC_1, pc(5), input, X), " & "378 (BC_1, pc(5), output3, X, 377, 1, Z), " & "377 (BC_1, *, controlr, 1), " & "376 (BC_1, pc(6), input, X), " & "375 (BC_1, pc(6), output3, X, 374, 1, Z), " & "374 (BC_1, *, controlr, 1), " & "373 (BC_1, pc(7), input, X), " & "372 (BC_1, pc(7), output3, X, 371, 1, Z), " & "371 (BC_1, *, controlr, 1), " & "370 (BC_1, pc(8), input, X), " & "369 (BC_1, pc(8), output3, X, 368, 1, Z), " & "368 (BC_1, *, controlr, 1), " & "367 (BC_1, pc(9), input, X), " & "366 (BC_1, pc(9), output3, X, 365, 1, Z), " & "365 (BC_1, *, controlr, 1), " & "364 (BC_1, pc(10), input, X), " & "363 (BC_1, pc(10), output3, X, 362, 1, Z), " & "362 (BC_1, *, controlr, 1), " & "361 (BC_1, pc(11), input, X), " & "360 (BC_1, pc(11), output3, X, 359, 1, Z), " & "359 (BC_1, *, controlr, 1), " & "358 (BC_1, pc(12), input, X), " & "357 (BC_1, pc(12), output3, X, 356, 1, Z), " & "356 (BC_1, *, controlr, 1), " & "355 (BC_1, pc(13), input, X), " & "354 (BC_1, pc(13), output3, X, 353, 1, Z), " & "353 (BC_1, *, controlr, 1), " & "352 (BC_1, pc(14), input, X), " & "351 (BC_1, pc(14), output3, X, 350, 1, Z), " & "350 (BC_1, *, controlr, 1), " & "349 (BC_1, pc(15), input, X), " & "348 (BC_1, pc(15), output3, X, 347, 1, Z), " & "347 (BC_1, *, controlr, 1), " & "346 (BC_1, pc(16), input, X), " & "345 (BC_1, pc(16), output3, X, 344, 1, Z), " & "344 (BC_1, *, controlr, 1), " & "343 (BC_1, pc(17), input, X), " & "342 (BC_1, pc(17), output3, X, 341, 1, Z), " & "341 (BC_1, *, controlr, 1), " & "340 (BC_1, pc(18), input, X), " & "339 (BC_1, pc(18), output3, X, 338, 1, Z), " & "338 (BC_1, *, controlr, 1), " & "337 (BC_1, pc(19), input, X), " & "336 (BC_1, pc(19), output3, X, 335, 1, Z), " & "335 (BC_1, *, controlr, 1), " & "334 (BC_1, pc(20), input, X), " & "333 (BC_1, pc(20), output3, X, 332, 1, Z), " & "332 (BC_1, *, controlr, 1), " & "331 (BC_1, pc(21), input, X), " & "330 (BC_1, pc(21), output3, X, 329, 1, Z), " & "329 (BC_1, *, controlr, 1), " & "328 (BC_1, pc(22), input, X), " & "327 (BC_1, pc(22), output3, X, 326, 1, Z), " & "326 (BC_1, *, controlr, 1), " & "325 (BC_1, pc(23), input, X), " & "324 (BC_1, pc(23), output3, X, 323, 1, Z), " & "323 (BC_1, *, controlr, 1), " & "322 (BC_1, pc(24), input, X), " & "321 (BC_1, pc(24), output3, X, 320, 1, Z), " & "320 (BC_1, *, controlr, 1), " & "319 (BC_1, pc(25), input, X), " & "318 (BC_1, pc(25), output3, X, 317, 1, Z), " & "317 (BC_1, *, controlr, 1), " & "316 (BC_1, pc(26), input, X), " & "315 (BC_1, pc(26), output3, X, 314, 1, Z), " & "314 (BC_1, *, controlr, 1), " & "313 (BC_1, pc(27), input, X), " & "312 (BC_1, pc(27), output3, X, 311, 1, Z), " & "311 (BC_1, *, controlr, 1), " & "310 (BC_1, pc(28), input, X), " & "309 (BC_1, pc(28), output3, X, 308, 1, Z), " & "308 (BC_1, *, controlr, 1), " & "307 (BC_1, pc(29), input, X), " & "306 (BC_1, pc(29), output3, X, 305, 1, Z), " & "305 (BC_1, *, controlr, 1), " & "304 (BC_1, pc(30), input, X), " & "303 (BC_1, pc(30), output3, X, 302, 1, Z), " & "302 (BC_1, *, controlr, 1), " & "301 (BC_1, pc(31), input, X), " & "300 (BC_1, pc(31), output3, X, 299, 1, Z), " & "299 (BC_1, *, controlr, 1), " & "298 (BC_1, pa(0), input, X), " & "297 (BC_1, pa(0), output3, X, 296, 1, Z), " & "296 (BC_1, *, controlr, 1), " & "295 (BC_1, pa(1), input, X), " & "294 (BC_1, pa(1), output3, X, 293, 1, Z), " & "293 (BC_1, *, controlr, 1), " & "292 (BC_1, pa(2), input, X), " & "291 (BC_1, pa(2), output3, X, 290, 1, Z), " & "290 (BC_1, *, controlr, 1), " & "289 (BC_1, pa(3), input, X), " & "288 (BC_1, pa(3), output3, X, 287, 1, Z), " & "287 (BC_1, *, controlr, 1), " & "286 (BC_1, pa(4), input, X), " & "285 (BC_1, pa(4), output3, X, 284, 1, Z), " & "284 (BC_1, *, controlr, 1), " & "283 (BC_1, pa(5), input, X), " & "282 (BC_1, pa(5), output3, X, 281, 1, Z), " & "281 (BC_1, *, controlr, 1), " & "280 (BC_1, pa(6), input, X), " & "279 (BC_1, pa(6), output3, X, 278, 1, Z), " & "278 (BC_1, *, controlr, 1), " & "277 (BC_1, pa(7), input, X), " & "276 (BC_1, pa(7), output3, X, 275, 1, Z), " & "275 (BC_1, *, controlr, 1), " & "274 (BC_1, pa(8), input, X), " & "273 (BC_1, pa(8), output3, X, 272, 1, Z), " & "272 (BC_1, *, controlr, 1), " & "271 (BC_1, pa(9), input, X), " & "270 (BC_1, pa(9), output3, X, 269, 1, Z), " & "269 (BC_1, *, controlr, 1), " & "268 (BC_1, pa(10), input, X), " & "267 (BC_1, pa(10), output3, X, 266, 1, Z), " & "266 (BC_1, *, controlr, 1), " & "265 (BC_1, pa(11), input, X), " & "264 (BC_1, pa(11), output3, X, 263, 1, Z), " & "263 (BC_1, *, controlr, 1), " & "262 (BC_1, pa(12), input, X), " & "261 (BC_1, pa(12), output3, X, 260, 1, Z), " & "260 (BC_1, *, controlr, 1), " & "259 (BC_1, pa(13), input, X), " & "258 (BC_1, pa(13), output3, X, 257, 1, Z), " & "257 (BC_1, *, controlr, 1), " & "256 (BC_1, pa(14), input, X), " & "255 (BC_1, pa(14), output3, X, 254, 1, Z), " & "254 (BC_1, *, controlr, 1), " & "253 (BC_1, pa(15), input, X), " & "252 (BC_1, pa(15), output3, X, 251, 1, Z), " & "251 (BC_1, *, controlr, 1), " & "250 (BC_1, pa(16), input, X), " & "249 (BC_1, pa(16), output3, X, 248, 1, Z), " & "248 (BC_1, *, controlr, 1), " & "247 (BC_1, pa(17), input, X), " & "246 (BC_1, pa(17), output3, X, 245, 1, Z), " & "245 (BC_1, *, controlr, 1), " & "244 (BC_1, pa(18), input, X), " & "243 (BC_1, pa(18), output3, X, 242, 1, Z), " & "242 (BC_1, *, controlr, 1), " & "241 (BC_1, pa(19), input, X), " & "240 (BC_1, pa(19), output3, X, 239, 1, Z), " & "239 (BC_1, *, controlr, 1), " & "238 (BC_1, pa(20), input, X), " & "237 (BC_1, pa(20), output3, X, 236, 1, Z), " & "236 (BC_1, *, controlr, 1), " & "235 (BC_1, pa(21), input, X), " & "234 (BC_1, pa(21), output3, X, 233, 1, Z), " & "233 (BC_1, *, controlr, 1), " & "232 (BC_1, pa(22), input, X), " & "231 (BC_1, pa(22), output3, X, 230, 1, Z), " & "230 (BC_1, *, controlr, 1), " & "229 (BC_1, pa(23), input, X), " & "228 (BC_1, pa(23), output3, X, 227, 1, Z), " & "227 (BC_1, *, controlr, 1), " & "226 (BC_1, pa(24), input, X), " & "225 (BC_1, pa(24), output3, X, 224, 1, Z), " & "224 (BC_1, *, controlr, 1), " & "223 (BC_1, pa(25), input, X), " & "222 (BC_1, pa(25), output3, X, 221, 1, Z), " & "221 (BC_1, *, controlr, 1), " & "220 (BC_1, pa(26), input, X), " & "219 (BC_1, pa(26), output3, X, 218, 1, Z), " & "218 (BC_1, *, controlr, 1), " & "217 (BC_1, pa(27), input, X), " & "216 (BC_1, pa(27), output3, X, 215, 1, Z), " & "215 (BC_1, *, controlr, 1), " & "214 (BC_1, pa(28), input, X), " & "213 (BC_1, pa(28), output3, X, 212, 1, Z), " & "212 (BC_1, *, controlr, 1), " & "211 (BC_1, pa(29), input, X), " & "210 (BC_1, pa(29), output3, X, 209, 1, Z), " & "209 (BC_1, *, controlr, 1), " & "208 (BC_1, pa(30), input, X), " & "207 (BC_1, pa(30), output3, X, 206, 1, Z), " & "206 (BC_1, *, controlr, 1), " & "205 (BC_1, pa(31), input, X), " & "204 (BC_1, pa(31), output3, X, 203, 1, Z), " & "203 (BC_1, *, controlr, 1), " & "202 (BC_1, pb(0), input, X), " & "201 (BC_1, pb(0), output3, X, 200, 1, Z), " & "200 (BC_1, *, controlr, 1), " & "199 (BC_1, pb(1), input, X), " & "198 (BC_1, pb(1), output3, X, 197, 1, Z), " & "197 (BC_1, *, controlr, 1), " & "196 (BC_1, pb(2), input, X), " & "195 (BC_1, pb(2), output3, X, 194, 1, Z), " & "194 (BC_1, *, controlr, 1), " & "193 (BC_1, pb(3), input, X), " & "192 (BC_1, pb(3), output3, X, 191, 1, Z), " & "191 (BC_1, *, controlr, 1), " & "190 (BC_1, pb(4), input, X), " & "189 (BC_1, pb(4), output3, X, 188, 1, Z), " & "188 (BC_1, *, controlr, 1), " & "187 (BC_1, pb(5), input, X), " & "186 (BC_1, pb(5), output3, X, 185, 1, Z), " & "185 (BC_1, *, controlr, 1), " & "184 (BC_1, pb(6), input, X), " & "183 (BC_1, pb(6), output3, X, 182, 1, Z), " & "182 (BC_1, *, controlr, 1), " & "181 (BC_1, pb(7), input, X), " & "180 (BC_1, pb(7), output3, X, 179, 1, Z), " & "179 (BC_1, *, controlr, 1), " & "178 (BC_1, pb(8), input, X), " & "177 (BC_1, pb(8), output3, X, 176, 1, Z), " & "176 (BC_1, *, controlr, 1), " & "175 (BC_1, pb(9), input, X), " & "174 (BC_1, pb(9), output3, X, 173, 1, Z), " & "173 (BC_1, *, controlr, 1), " & "172 (BC_1, pb(10), input, X), " & "171 (BC_1, pb(10), output3, X, 170, 1, Z), " & "170 (BC_1, *, controlr, 1), " & "169 (BC_1, pb(11), input, X), " & "168 (BC_1, pb(11), output3, X, 167, 1, Z), " & "167 (BC_1, *, controlr, 1), " & "166 (BC_1, pb(12), input, X), " & "165 (BC_1, pb(12), output3, X, 164, 1, Z), " & "164 (BC_1, *, controlr, 1), " & "163 (BC_1, pb(13), input, X), " & "162 (BC_1, pb(13), output3, X, 161, 1, Z), " & "161 (BC_1, *, controlr, 1), " & "160 (BC_1, pb(14), input, X), " & "159 (BC_1, pb(14), output3, X, 158, 1, Z), " & "158 (BC_1, *, controlr, 1), " & "157 (BC_1, pb(15), input, X), " & "156 (BC_1, pb(15), output3, X, 155, 1, Z), " & "155 (BC_1, *, controlr, 1), " & "154 (BC_1, pb(16), input, X), " & "153 (BC_1, pb(16), output3, X, 152, 1, Z), " & "152 (BC_1, *, controlr, 1), " & "151 (BC_1, pb(17), input, X), " & "150 (BC_1, pb(17), output3, X, 149, 1, Z), " & "149 (BC_1, *, controlr, 1), " & "148 (BC_1, pb(18), input, X), " & "147 (BC_1, pb(18), output3, X, 146, 1, Z), " & "146 (BC_1, *, controlr, 1), " & "145 (BC_1, pb(19), input, X), " & "144 (BC_1, pb(19), output3, X, 143, 1, Z), " & "143 (BC_1, *, controlr, 1), " & "142 (BC_1, pb(20), input, X), " & "141 (BC_1, pb(20), output3, X, 140, 1, Z), " & "140 (BC_1, *, controlr, 1), " & "139 (BC_1, pb(21), input, X), " & "138 (BC_1, pb(21), output3, X, 137, 1, Z), " & "137 (BC_1, *, controlr, 1), " & "136 (BC_1, pb(22), input, X), " & "135 (BC_1, pb(22), output3, X, 134, 1, Z), " & "134 (BC_1, *, controlr, 1), " & "133 (BC_1, pb(23), input, X), " & "132 (BC_1, pb(23), output3, X, 131, 1, Z), " & "131 (BC_1, *, controlr, 1), " & "130 (BC_1, pb(24), input, X), " & "129 (BC_1, pb(24), output3, X, 128, 1, Z), " & "128 (BC_1, *, controlr, 1), " & "127 (BC_1, pb(25), input, X), " & "126 (BC_1, pb(25), output3, X, 125, 1, Z), " & "125 (BC_1, *, controlr, 1), " & "124 (BC_1, pb(26), input, X), " & "123 (BC_1, pb(26), output3, X, 122, 1, Z), " & "122 (BC_1, *, controlr, 1), " & "121 (BC_1, pb(27), input, X), " & "120 (BC_1, pb(27), output3, X, 119, 1, Z), " & "119 (BC_1, *, controlr, 1), " & "118 (BC_1, pb(28), input, X), " & "117 (BC_1, pb(28), output3, X, 116, 1, Z), " & "116 (BC_1, *, controlr, 1), " & "115 (BC_1, pb(29), input, X), " & "114 (BC_1, pb(29), output3, X, 113, 1, Z), " & "113 (BC_1, *, controlr, 1), " & "112 (BC_1, pb(30), input, X), " & "111 (BC_1, pb(30), output3, X, 110, 1, Z), " & "110 (BC_1, *, controlr, 1), " & "109 (BC_1, pb(31), input, X), " & "108 (BC_1, pb(31), output3, X, 107, 1, Z), " & "107 (BC_1, *, controlr, 1), " & "106 (BC_1, bms, input, X), " & "105 (BC_1, rtck, output2, X), " & "104 (BC_1, ncs0, output3, X, 1, 1, Z), " & "103 (BC_1, nrd_cfoe, output3, X, 1, 1, Z), " & "102 (BC_1, sda10, output3, X, 1, 1, Z), " & "101 (BC_1, ncs1_sdcs, output3, X, 1, 1, Z), " & "100 (BC_1, sdwe, output3, X, 1, 1, Z), " & "99 (BC_1, cas, output3, X, 1, 1, Z), " & "98 (BC_1, ras, output3, X, 1, 1, Z), " & "97 (BC_1, sdcke, output3, X, 1, 1, Z), " & "96 (BC_1, nwr3_nbs3_cfiow, input, X), " & "95 (BC_1, nwr3_nbs3_cfiow, output3, X, 1, 1, Z), " & "94 (BC_1, nwr1_nbs1_cfior, input, X), " & "93 (BC_1, nwr1_nbs1_cfior, output3, X, 1, 1, Z), " & "92 (BC_0, *, internal, X), " & "91 (BC_1, sdck, output2, X), " & "90 (BC_1, nwr0_nwe_cfwe, input, X), " & "89 (BC_1, nwr0_nwe_cfwe, output3, X, 1, 1, Z), " & "88 (BC_1, a(17), input, X), " & "87 (BC_1, a(17), output3, X, 1, 1, Z), " & "86 (BC_1, a(16), input, X), " & "85 (BC_1, a(16), output3, X, 1, 1, Z), " & "84 (BC_1, a(15), input, X), " & "83 (BC_1, a(15), output3, X, 1, 1, Z), " & "82 (BC_1, a(14), input, X), " & "81 (BC_1, a(14), output3, X, 1, 1, Z), " & "80 (BC_1, a(13), input, X), " & "79 (BC_1, a(13), output3, X, 1, 1, Z), " & "78 (BC_1, a(12), input, X), " & "77 (BC_1, a(12), output3, X, 1, 1, Z), " & "76 (BC_1, a(11), input, X), " & "75 (BC_1, a(11), output3, X, 1, 1, Z), " & "74 (BC_1, a(10), input, X), " & "73 (BC_1, a(10), output3, X, 1, 1, Z), " & "72 (BC_1, a(9), input, X), " & "71 (BC_1, a(9), output3, X, 1, 1, Z), " & "70 (BC_1, a(8), input, X), " & "69 (BC_1, a(8), output3, X, 1, 1, Z), " & "68 (BC_1, a(7), input, X), " & "67 (BC_1, a(7), output3, X, 1, 1, Z), " & "66 (BC_1, a(6), input, X), " & "65 (BC_1, a(6), output3, X, 1, 1, Z), " & "64 (BC_1, a(5), input, X), " & "63 (BC_1, a(5), output3, X, 1, 1, Z), " & "62 (BC_1, a(4), input, X), " & "61 (BC_1, a(4), output3, X, 1, 1, Z), " & "60 (BC_1, a(3), input, X), " & "59 (BC_1, a(3), output3, X, 1, 1, Z), " & "58 (BC_1, a(2), input, X), " & "57 (BC_1, a(2), output3, X, 1, 1, Z), " & "56 (BC_1, a(1), input, X), " & "55 (BC_1, a(1), output3, X, 1, 1, Z), " & "54 (BC_1, a(0), input, X), " & "53 (BC_1, a(0), output3, X, 1, 1, Z), " & "52 (BC_1, d(0), input, X), " & "51 (BC_1, d(0), output3, X, 50, 1, Z), " & "50 (BC_1, *, controlr, 1), " & "49 (BC_1, d(1), input, X), " & "48 (BC_1, d(1), output3, X, 47, 1, Z), " & "47 (BC_1, *, controlr, 1), " & "46 (BC_1, d(2), input, X), " & "45 (BC_1, d(2), output3, X, 44, 1, Z), " & "44 (BC_1, *, controlr, 1), " & "43 (BC_1, d(3), input, X), " & "42 (BC_1, d(3), output3, X, 41, 1, Z), " & "41 (BC_1, *, controlr, 1), " & "40 (BC_1, d(4), input, X), " & "39 (BC_1, d(4), output3, X, 38, 1, Z), " & "38 (BC_1, *, controlr, 1), " & "37 (BC_1, d(5), input, X), " & "36 (BC_1, d(5), output3, X, 35, 1, Z), " & "35 (BC_1, *, controlr, 1), " & "34 (BC_1, d(6), input, X), " & "33 (BC_1, d(6), output3, X, 32, 1, Z), " & "32 (BC_1, *, controlr, 1), " & "31 (BC_1, d(7), input, X), " & "30 (BC_1, d(7), output3, X, 29, 1, Z), " & "29 (BC_1, *, controlr, 1), " & "28 (BC_1, d(8), input, X), " & "27 (BC_1, d(8), output3, X, 26, 1, Z), " & "26 (BC_1, *, controlr, 1), " & "25 (BC_1, d(9), input, X), " & "24 (BC_1, d(9), output3, X, 23, 1, Z), " & "23 (BC_1, *, controlr, 1), " & "22 (BC_1, d(10), input, X), " & "21 (BC_1, d(10), output3, X, 20, 1, Z), " & "20 (BC_1, *, controlr, 1), " & "19 (BC_1, d(11), input, X), " & "18 (BC_1, d(11), output3, X, 17, 1, Z), " & "17 (BC_1, *, controlr, 1), " & "16 (BC_1, d(12), input, X), " & "15 (BC_1, d(12), output3, X, 14, 1, Z), " & "14 (BC_1, *, controlr, 1), " & "13 (BC_1, d(13), input, X), " & "12 (BC_1, d(13), output3, X, 11, 1, Z), " & "11 (BC_1, *, controlr, 1), " & "10 (BC_1, d(14), input, X), " & "9 (BC_1, d(14), output3, X, 8, 1, Z), " & "8 (BC_1, *, controlr, 1), " & "7 (BC_1, d(15), input, X), " & "6 (BC_1, d(15), output3, X, 5, 1, Z), " & "5 (BC_1, *, controlr, 1), " & "4 (BC_1, nrst, input, X), " & "3 (BC_1, nrst, output3, X, 2, 1, Z), " & "2 (BC_1, *, controlr, 1), " & "1 (BC_1, *, controlr, 1), " & "0 (BC_0, *, internal, X) "; end AT91SAM9RL64;