-- Information relating to Products and circuits ('Product') furnished -- herein by Zarlink Semiconductor or its subsidiaries ('Zarlink') is -- believed to be reliable. However,Zarlink assumes no liability for -- errors that may appear in this document,or for liability otherwise -- arising from the application or use of any such information or -- product or any infringement of patients or other intellectual -- property rights owned by third parties which may result from such -- applications or use. Neither the supply of such information or the -- purchase of product conveys any license,either expressed or implied, -- under patents or other intellectual property rights owned by Zarlink -- or licensed from third parties by Zarlink,whatsoever. Purchaser -- of Product are also hereby notified that the use of Products in -- certain ways or in combination with Zarlink or non-Zarlink furnished -- goods or services may infringe patents or other intellectual property -- rights owned by Zarlink. The Products,their specifications and the -- information appearing in the document are subject to change by -- Zarlink without notice. -- Zarlink Semiconductor (c) 2001 -- The Boundary Scan patterns are for use at nominal supply conditions -- and an ambient temperature of 15-30 degrees Celsius. -- Generated by boundaryScanGenerate 3.3c-Build20010123.006 on -- 05/10/02 08:25:52 -- BSDL Version 1994 entity mt90881 is generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME"); port ( -- Port List jtagdin : in bit; jtagclk : in bit; pci_inta_n : out bit; pci_rst_n : in bit; pci_clk : inout bit; pci_gnt_n : inout bit; pci_req_n : out bit; pci_ad : inout bit_vector( 31 downto 0 ); pci_cbe_n : inout bit_vector( 3 downto 0 ); pci_idsel : inout bit; pclk_at1 : linkage bit; iddq : in bit; pci_frame_n : inout bit; pci_irdy_n : inout bit; pci_trdy_n : inout bit; pci_devsel_n : inout bit; pci_stop_n : inout bit; pci_lock_n : inout bit; pci_perr_n : inout bit; pci_serr_n : out bit; pci_par : inout bit; wan_clko : out bit; wan_frmo : out bit; pci_m66en : inout bit; wan_clki : in bit_vector( 31 downto 0 ); wan_frmi : in bit_vector( 31 downto 0 ); wan_sti : in bit_vector( 31 downto 0 ); wan_sto : out bit_vector( 31 downto 0 ); s_rst_b : in bit; rstout_b : out bit; sclk_at1 : linkage bit; s_clk : in bit; ode : in bit; c4ob : out bit; c8ob : out bit; c16ob : out bit; fp4ob : out bit; fp8ob : out bit; fp16ob : out bit; ram_d : inout bit_vector( 31 downto 0 ); ram_a : out bit_vector( 22 downto 2 ); ram_clk : out bit; ram_rw3_b : out bit; ram_rw2_b : out bit; ram_rw1_b : out bit; ram_rw0_b : out bit; ram_oe3_b : out bit; ram_oe2_b : out bit; ram_oe1_b : out bit; ram_oe0_b : out bit; ram_adsc_b : out bit; m0_txen : out bit; m0_txd : out bit_vector( 3 downto 0 ); m_mint0 : in bit; m0_txclk : in bit; m0_col : in bit; m0_crs : in bit; m0_rxer : in bit; m0_rxclk : in bit; m0_rxdv : in bit; m0_rxd : in bit_vector( 3 downto 0 ); m_mdio : inout bit; m_mdc : inout bit; refclk : in bit; m1_txen : out bit; m1_txd : out bit_vector( 3 downto 0 ); m_mint1 : in bit; m1_txclk : in bit; m1_col : in bit; m1_crs : in bit; m1_rxer : in bit; m1_rxclk : in bit; m1_rxdv : in bit; m1_rxd : in bit_vector( 3 downto 0 ); t_mode0 : in bit; t_mode1 : in bit; t_d : inout bit_vector( 15 downto 0 ); jtagrst_b : in bit; jtagdout : out bit; jtagmode : in bit; NC : linkage bit_vector (1 to 66); -- No Connects A1VDD: linkage bit; -- PLL Supply A2VDD: linkage bit; -- PLL Supply VDD18: linkage bit_vector (1 to 12); -- Core Supply VDD33: linkage bit_vector (1 to 22); -- Periphery Supply GND: linkage bit_vector (1 to 38) -- Ground ); use STD_1149_1_1994.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of mt90881: entity is "STD_1149_1_1993"; --Pin mappings attribute PIN_MAP of mt90881: entity is PHYSICAL_PIN_MAP; constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := "jtagdin : AD18 ," & "jtagclk : AB18 ," & "pci_inta_n : AF19 ," & "pci_rst_n : AE19 ," & "pci_clk : AF20 ," & "pci_gnt_n : AD19 ," & "pci_req_n : AC19 ," & "pci_ad :(AE20 ," & -- pci_ad[31] "AB19 ," & -- pci_ad[30] "AF21 ," & -- pci_ad[29] "AC20 ," & -- pci_ad[28] "AD20 ," & -- pci_ad[27] "AE21 ," & -- pci_ad[26] "AF22 ," & -- pci_ad[25] "AD21 ," & -- pci_ad[24] "AF23 ," & -- pci_ad[23] "AD22 ," & -- pci_ad[22] "AE23 ," & -- pci_ad[21] "AC21 ," & -- pci_ad[20] "AE24 ," & -- pci_ad[19] "AC22 ," & -- pci_ad[18] "AD24 ," & -- pci_ad[17] "AC23 ," & -- pci_ad[16] "AC26 ," & -- pci_ad[15] "AB25 ," & -- pci_ad[14] "W23 ," & -- pci_ad[13] "AA24 ," & -- pci_ad[12] "AB26 ," & -- pci_ad[11] "AA25 ," & -- pci_ad[10] "Y24 ," & -- pci_ad[9] "AA26 ," & -- pci_ad[8] "V24 ," & -- pci_ad[7] "U23 ," & -- pci_ad[6] "V25 ," & -- pci_ad[5] "T23 ," & -- pci_ad[4] "T24 ," & -- pci_ad[3] "R23 ," & -- pci_ad[2] "T25 ," & -- pci_ad[1] "T26)," & -- pci_ad[0] "pci_cbe_n :(AE22 ," & -- pci_cbe_n[3] "AB23 ," & -- pci_cbe_n[2] "Y23 ," & -- pci_cbe_n[1] "W24)," & -- pci_cbe_n[0] "pci_idsel : AB20 ," & "pclk_at1 : AF24 ," & "iddq : AD23 ," & "pci_frame_n : AE25 ," & "pci_irdy_n : AF26 ," & "pci_trdy_n : AA23 ," & "pci_devsel_n : AE26 ," & "pci_stop_n : AC24 ," & "pci_lock_n : Y22 ," & "pci_perr_n : AD26 ," & "pci_serr_n : AB24 ," & "pci_par : AC25 ," & "wan_clko : V22 ," & "wan_frmo : V23 ," & "pci_m66en : Y25 ," & "wan_clki :(U22 ," & -- wan_clki[31] "V26 ," & -- wan_clki[30] "N23 ," & -- wan_clki[29] "P24 ," & -- wan_clki[28] "M22 ," & -- wan_clki[27] "N24 ," & -- wan_clki[26] "K23 ," & -- wan_clki[25] "L24 ," & -- wan_clki[24] "J23 ," & -- wan_clki[23] "J24 ," & -- wan_clki[22] "H22 ," & -- wan_clki[21] "G22 ," & -- wan_clki[20] "E26 ," & -- wan_clki[19] "E24 ," & -- wan_clki[18] "A26 ," & -- wan_clki[17] "A24 ," & -- wan_clki[16] "A23 ," & -- wan_clki[15] "E19 ," & -- wan_clki[14] "B21 ," & -- wan_clki[13] "B20 ," & -- wan_clki[12] "A20 ," & -- wan_clki[11] "B18 ," & -- wan_clki[10] "C17 ," & -- wan_clki[9] "C16 ," & -- wan_clki[8] "D15 ," & -- wan_clki[7] "A15 ," & -- wan_clki[6] "D13 ," & -- wan_clki[5] "E12 ," & -- wan_clki[4] "C12 ," & -- wan_clki[3] "B11 ," & -- wan_clki[2] "B10 ," & -- wan_clki[1] "B9)," & -- wan_clki[0] "wan_frmi :(W25 ," & -- wan_frmi[31] "U24 ," & -- wan_frmi[30] "R24 ," & -- wan_frmi[29] "P25 ," & -- wan_frmi[28] "N26 ," & -- wan_frmi[27] "M25 ," & -- wan_frmi[26] "L26 ," & -- wan_frmi[25] "K26 ," & -- wan_frmi[24] "J26 ," & -- wan_frmi[23] "H26 ," & -- wan_frmi[22] "H24 ," & -- wan_frmi[21] "F26 ," & -- wan_frmi[20] "F23 ," & -- wan_frmi[19] "C26 ," & -- wan_frmi[18] "A25 ," & -- wan_frmi[17] "C23 ," & -- wan_frmi[16] "C22 ," & -- wan_frmi[15] "C21 ," & -- wan_frmi[14] "C20 ," & -- wan_frmi[13] "D18 ," & -- wan_frmi[12] "B19 ," & -- wan_frmi[11] "D17 ," & -- wan_frmi[10] "D16 ," & -- wan_frmi[9] "B16 ," & -- wan_frmi[8] "C15 ," & -- wan_frmi[7] "C14 ," & -- wan_frmi[6] "A13 ," & -- wan_frmi[5] "C13 ," & -- wan_frmi[4] "D11 ," & -- wan_frmi[3] "D10 ," & -- wan_frmi[2] "C10 ," & -- wan_frmi[1] "D9)," & -- wan_frmi[0] "wan_sti :(W26 ," & -- wan_sti[31] "U25 ," & -- wan_sti[30] "R25 ," & -- wan_sti[29] "M23 ," & -- wan_sti[28] "L23 ," & -- wan_sti[27] "L22 ," & -- wan_sti[26] "K22 ," & -- wan_sti[25] "K25 ," & -- wan_sti[24] "J22 ," & -- wan_sti[23] "H25 ," & -- wan_sti[22] "G23 ," & -- wan_sti[21] "F25 ," & -- wan_sti[20] "E25 ," & -- wan_sti[19] "C24 ," & -- wan_sti[18] "D21 ," & -- wan_sti[17] "E20 ," & -- wan_sti[16] "D20 ," & -- wan_sti[15] "D19 ," & -- wan_sti[14] "A21 ," & -- wan_sti[13] "C19 ," & -- wan_sti[12] "A19 ," & -- wan_sti[11] "A18 ," & -- wan_sti[10] "B17 ," & -- wan_sti[9] "E15 ," & -- wan_sti[8] "D14 ," & -- wan_sti[7] "B14 ," & -- wan_sti[6] "D12 ," & -- wan_sti[5] "A12 ," & -- wan_sti[4] "A11 ," & -- wan_sti[3] "C11 ," & -- wan_sti[2] "A9 ," & -- wan_sti[1] "C9)," & -- wan_sti[0] "wan_sto :(T22 ," & -- wan_sto[31] "U26 ," & -- wan_sto[30] "R26 ," & -- wan_sto[29] "P26 ," & -- wan_sto[28] "N25 ," & -- wan_sto[27] "M24 ," & -- wan_sto[26] "L25 ," & -- wan_sto[25] "K24 ," & -- wan_sto[24] "J25 ," & -- wan_sto[23] "G26 ," & -- wan_sto[22] "G25 ," & -- wan_sto[21] "G24 ," & -- wan_sto[20] "D26 ," & -- wan_sto[19] "D22 ," & -- wan_sto[18] "B24 ," & -- wan_sto[17] "B23 ," & -- wan_sto[16] "B22 ," & -- wan_sto[15] "A22 ," & -- wan_sto[14] "E18 ," & -- wan_sto[13] "E17 ," & -- wan_sto[12] "C18 ," & -- wan_sto[11] "E16 ," & -- wan_sto[10] "A17 ," & -- wan_sto[9] "A16 ," & -- wan_sto[8] "B15 ," & -- wan_sto[7] "A14 ," & -- wan_sto[6] "B13 ," & -- wan_sto[5] "B12 ," & -- wan_sto[4] "E11 ," & -- wan_sto[3] "A10 ," & -- wan_sto[2] "E10 ," & -- wan_sto[1] "E9 )," & -- wan_sto[0] "s_rst_b : D24 ," & "rstout_b : C25 ," & "sclk_at1 : B26 ," & "s_clk : B25 ," & "ode : A8 ," & "c4ob : B8 ," & "c8ob : A7 ," & "c16ob : B7 ," & "fp4ob : C8 ," & "fp8ob : A6 ," & "fp16ob : D8 ," & "ram_d :(N2 ," & -- ram_d[31] "R4 ," & -- ram_d[30] "N1 ," & -- ram_d[29] "R5 ," & -- ram_d[28] "P1 ," & -- ram_d[27] "T4 ," & -- ram_d[26] "P2 ," & -- ram_d[25] "P3 ," & -- ram_d[24] "R1 ," & -- ram_d[23] "AB4 ," & -- ram_d[22] "AC2 ," & -- ram_d[21] "AD1 ," & -- ram_d[20] "AC3 ," & -- ram_d[19] "AD2 ," & -- ram_d[18] "AC4 ," & -- ram_d[17] "AE1 ," & -- ram_d[16] "AE2 ," & -- ram_d[15] "AD3 ," & -- ram_d[14] "AC5 ," & -- ram_d[13] "AF1 ," & -- ram_d[12] "AF2 ," & -- ram_d[11] "AC6 ," & -- ram_d[10] "AE3 ," & -- ram_d[9] "AF3 ," & -- ram_d[8] "AD4 ," & -- ram_d[7] "AB7 ," & -- ram_d[6] "AE4 ," & -- ram_d[5] "AF4 ," & -- ram_d[4] "AD5 ," & -- ram_d[3] "AC7 ," & -- ram_d[2] "AE5 ," & -- ram_d[1] "AB8)," & -- ram_d[0] "ram_a :(T5 ," & -- ram_a[22] "R3 ," & -- ram_a[21] "U4 ," & -- ram_a[20] "T1 ," & -- ram_a[19] "U5 ," & -- ram_a[18] "T2 ," & -- ram_a[17] "T3 ," & -- ram_a[16] "U1 ," & -- ram_a[15] "U2 ," & -- ram_a[14] "U3 ," & -- ram_a[13] "V4 ," & -- ram_a[12] "V1 ," & -- ram_a[11] "V5 ," & -- ram_a[10] "V2 ," & -- ram_a[9] "W4 ," & -- ram_a[8] "W1 ," & -- ram_a[7] "W2 ," & -- ram_a[6] "Y1 ," & -- ram_a[5] "W5 ," & -- ram_a[4] "W3 ," & -- ram_a[3] "Y4 )," & -- ram_a[2] "ram_clk : Y2 ," & "ram_rw3_b : Y5 ," & "ram_rw2_b : AA1 ," & "ram_rw1_b : Y3 ," & "ram_rw0_b : AA2 ," & "ram_oe3_b : AB1 ," & "ram_oe2_b : AA4 ," & "ram_oe1_b : AB2 ," & "ram_oe0_b : AC1 ," & "ram_adsc_b : AB3 ," & "m0_txen : AD6 ," & "m0_txd :(AC8 ," & -- m0_txd[3] "AF5 ," & -- m0_txd[2] "AE6 ," & -- m0_txd[1] "AD7)," & -- m0_txd[0] "m_mint0 : AF6 ," & "m0_txclk : AB9 ," & "m0_col : AE7 ," & "m0_crs : AC9 ," & "m0_rxer : AD8 ," & "m0_rxclk : AB10 ," & "m0_rxdv : AF7 ," & "m0_rxd :(AF8 ," & -- m0_rxd[3] "AE8 ," & -- m0_rxd[2] "AE9 ," & -- m0_rxd[1] "AD9)," & -- m0_rxd[0] "m_mdio : AC10 ," & "m_mdc : AF9 ," & "refclk : AB11 ," & "m1_txen : AD10 ," & "m1_txd :(AC11 ," & -- m1_txd[3] "AE10 ," & -- m1_txd[2] "AF10 ," & -- m1_txd[1] "AD11)," & -- m1_txd[0] "m_mint1 : AE11 ," & "m1_txclk : AB12 ," & "m1_col : AF11 ," & "m1_crs : AC12 ," & "m1_rxer : AD12 ," & "m1_rxclk : AC13 ," & "m1_rxdv : AE12 ," & "m1_rxd :(AF12 ," & -- m1_rxd[3] "AD13 ," & -- m1_rxd[2] "AE13 ," & -- m1_rxd[1] "AF13)," & -- m1_rxd[0] "t_mode0 : AC14 ," & "t_mode1 : AF14 ," & "t_d :(AC15 ," & -- t_d[15] "AE14 ," & -- t_d[14] "AB15 ," & -- t_d[13] "AD14 ," & -- t_d[12] "AF15 ," & -- t_d[11] "AE15 ," & -- t_d[10] "AD15 ," & -- t_d[9] "AF16 ," & -- t_d[8] "AB16 ," & -- t_d[7] "AE16 ," & -- t_d[6] "AC17 ," & -- t_d[5] "AD16 ," & -- t_d[4] "AF17 ," & -- t_d[3] "AE17 ," & -- t_d[2] "AD17 ," & -- t_d[1] "AF18)," & -- t_d[0] "jtagrst_b : AB17 ," & "jtagdout : AE18 ," & "jtagmode : AC18 ," & -- No Connects " NC : (D23,AC16,B6,C7,A5,C5,A4,B4,A3,B3, " & " D5,D4,B2,F4,D3,G5,E3,G4, " & " H5,F3,F2,J5,J4,K5,H2,H1, " & " J2,J1,K3,K1,M4,N4,M3,M1, " & " E8,D7,C6,B5,E7,D6,C4,A2, " & " C3,E4,A1,B1,C2,C1,D2,D1, " & " H4,E1,G3,F1,G2,H3,G1,K4, " & " L5,L4,K2,L3,L2,P4,M2,N3)," & -- PLL1 SUPPLY " A1VDD : D25," & -- PLL2 SUPPLY " A2VDD : AF25," & -- Periphery Supply " VDD33 : (AA5,AA22,AB5,AB6,AB13,AB14,AB21,AB22,E5,E6," & " E13,E14,E21,E22,F5,F22,M5,N5,N22,P5,P22,R22)," & -- Core Supply " VDD18 : (AA3,E2,F24,H23,J3,L1,M26,P23,R2,V3,W22,Y26)," & -- Ground " GND : (L11,L12,L13,L14,L15,L16," & " M11,M12,M13,M14,M15,M16," & " N11,N12,N13,N14,N15,N16," & " P11,P12,P13,P14,P15,P16," & " R11,R12,R13,R14,R15,R16," & " T11,T12,T13,T14,T15,T16,AD25,E23) " ; attribute TAP_SCAN_RESET of jtagrst_b: signal is true; attribute TAP_SCAN_IN of jtagdin : signal is true; attribute TAP_SCAN_MODE of jtagmode: signal is true; attribute TAP_SCAN_OUT of jtagdout: signal is true; attribute TAP_SCAN_CLOCK of jtagclk : signal is (1.00e+07, BOTH); attribute COMPLIANCE_PATTERNS of mt90881 : entity is "(pci_rst_n,iddq,s_rst_b,t_mode0,t_mode1) (10111)"; attribute INSTRUCTION_LENGTH of mt90881: entity is 16; attribute INSTRUCTION_OPCODE of mt90881: entity is "IDCODE (1111111111111110)," & "BYPASS (1111111111111111)," & "EXTEST (0000000000000000, 1111111111101000)," & "SAMPLE (1111111111111000)," & "HIGHZ (1111111111001111)," & "CLAMP (1111111111101111) " ; attribute INSTRUCTION_CAPTURE of mt90881: entity is "XXXXXXXXXXXXXX01"; attribute IDCODE_REGISTER of mt90881: entity is "0001" & -- version "0000100010000001" & -- part number "00010100101" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of mt90881: entity is "BYPASS (HIGHZ, CLAMP) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of mt90881: entity is 487; attribute BOUNDARY_REGISTER of mt90881: entity is -- num cell port function safe [ccell disval rslt] " 486 (BC_2, *, control , 1 ) ,"& " 485 (BC_2, pci_inta_n, output3 , X, 486, 1 , Z ),"& " 484 (BC_2, *, control , 1 ) ,"& " 483 (LV_BC_7, pci_clk , bidir , X, 484, 1 , Z ),"& " 482 (BC_2, *, control , 1 ) ,"& " 481 (LV_BC_7, pci_gnt_n , bidir , X, 482, 1 , Z ),"& " 480 (BC_2, *, control , 1 ) ,"& " 479 (BC_2, pci_req_n , output3 , X, 480, 1 , Z ),"& " 478 (BC_2, *, control , 1 ) ,"& " 477 (LV_BC_7, pci_ad(31), bidir , X, 478, 1 , Z ),"& " 476 (BC_2, *, control , 1 ) ,"& " 475 (LV_BC_7, pci_ad(30), bidir , X, 476, 1 , Z ),"& " 474 (BC_2, *, control , 1 ) ,"& " 473 (LV_BC_7, pci_ad(29), bidir , X, 474, 1 , Z ),"& " 472 (BC_2, *, control , 1 ) ,"& " 471 (LV_BC_7, pci_ad(28), bidir , X, 472, 1 , Z ),"& " 470 (BC_2, *, control , 1 ) ,"& " 469 (LV_BC_7, pci_ad(27), bidir , X, 470, 1 , Z ),"& " 468 (BC_2, *, control , 1 ) ,"& " 467 (LV_BC_7, pci_ad(26), bidir , X, 468, 1 , Z ),"& " 466 (BC_2, *, control , 1 ) ,"& " 465 (LV_BC_7, pci_ad(25), bidir , X, 466, 1 , Z ),"& " 464 (BC_2, *, control , 1 ) ,"& " 463 (LV_BC_7, pci_ad(24), bidir , X, 464, 1 , Z ),"& " 462 (BC_2, *, control , 1 ) ,"& " 461 (LV_BC_7, pci_cbe_n(3) , bidir , X, 462, 1 , Z ),"& " 460 (BC_2, *, control , 1 ) ,"& " 459 (LV_BC_7, pci_idsel , bidir , X, 460, 1 , Z ),"& " 458 (BC_2, *, control , 1 ) ,"& " 457 (LV_BC_7, pci_ad(23), bidir , X, 458, 1 , Z ),"& " 456 (BC_2, *, control , 1 ) ,"& " 455 (LV_BC_7, pci_ad(22), bidir , X, 456, 1 , Z ),"& " 454 (BC_2, *, control , 1 ) ,"& " 453 (LV_BC_7, pci_ad(21), bidir , X, 454, 1 , Z ),"& " 452 (BC_2, *, control , 1 ) ,"& " 451 (LV_BC_7, pci_ad(20), bidir , X, 452, 1 , Z ),"& " 450 (BC_2, *, control , 1 ) ,"& " 449 (LV_BC_7, pci_ad(19), bidir , X, 450, 1 , Z ),"& " 448 (BC_2, *, control , 1 ) ,"& " 447 (LV_BC_7, pci_ad(18), bidir , X, 448, 1 , Z ),"& " 446 (BC_2, *, control , 1 ) ,"& " 445 (LV_BC_7, pci_ad(17), bidir , X, 446, 1 , Z ),"& " 444 (BC_2, *, control , 1 ) ,"& " 443 (LV_BC_7, pci_ad(16), bidir , X, 444, 1 , Z ),"& " 442 (BC_2, *, control , 1 ) ,"& " 441 (LV_BC_7, pci_cbe_n(2) , bidir , X, 442, 1 , Z ),"& " 440 (BC_2, *, control , 1 ) ,"& " 439 (LV_BC_7, pci_frame_n , bidir , X, 440, 1 , Z ),"& " 438 (BC_2, *, control , 1 ) ,"& " 437 (LV_BC_7, pci_irdy_n, bidir , X, 438, 1 , Z ),"& " 436 (BC_2, *, control , 1 ) ,"& " 435 (LV_BC_7, pci_trdy_n, bidir , X, 436, 1 , Z ),"& " 434 (BC_2, *, control , 1 ) ,"& " 433 (LV_BC_7, pci_devsel_n , bidir , X, 434, 1 , Z ),"& " 432 (BC_2, *, control , 1 ) ,"& " 431 (LV_BC_7, pci_stop_n, bidir , X, 432, 1 , Z ),"& " 430 (BC_2, *, control , 1 ) ,"& " 429 (LV_BC_7, pci_lock_n, bidir , X, 430, 1 , Z ),"& " 428 (BC_2, *, control , 1 ) ,"& " 427 (LV_BC_7, pci_perr_n, bidir , X, 428, 1 , Z ),"& " 426 (BC_2, *, control , 1 ) ,"& " 425 (BC_2, pci_serr_n, output3 , X, 426, 1 , Z ),"& " 424 (BC_2, *, control , 1 ) ,"& " 423 (LV_BC_7, pci_par , bidir , X, 424, 1 , Z ),"& " 422 (BC_2, *, control , 1 ) ,"& " 421 (LV_BC_7, pci_cbe_n(1) , bidir , X, 422, 1 , Z ),"& " 420 (BC_2, *, control , 1 ) ,"& " 419 (LV_BC_7, pci_ad(15), bidir , X, 420, 1 , Z ),"& " 418 (BC_2, *, control , 1 ) ,"& " 417 (LV_BC_7, pci_ad(14), bidir , X, 418, 1 , Z ),"& " 416 (BC_2, *, control , 1 ) ,"& " 415 (LV_BC_7, pci_ad(13), bidir , X, 416, 1 , Z ),"& " 414 (BC_2, *, control , 1 ) ,"& " 413 (LV_BC_7, pci_ad(12), bidir , X, 414, 1 , Z ),"& " 412 (BC_2, *, control , 1 ) ,"& " 411 (LV_BC_7, pci_ad(11), bidir , X, 412, 1 , Z ),"& " 410 (BC_2, *, control , 1 ) ,"& " 409 (LV_BC_7, pci_ad(10), bidir , X, 410, 1 , Z ),"& " 408 (BC_2, *, control , 1 ) ,"& " 407 (LV_BC_7, pci_ad(9) , bidir , X, 408, 1 , Z ),"& " 406 (BC_2, *, control , 1 ) ,"& " 405 (BC_2, wan_clko , output3 , X, 406, 1 , Z ),"& " 404 (BC_2, *, control , 1 ) ,"& " 403 (LV_BC_7, pci_ad(8) , bidir , X, 404, 1 , Z ),"& " 402 (BC_2, *, control , 1 ) ,"& " 401 (BC_2, wan_frmo , output3 , X, 402, 1 , Z ),"& " 400 (BC_2, *, control , 1 ) ,"& " 399 (LV_BC_7, pci_m66en , bidir , X, 400, 1 , Z ),"& " 398 (BC_2, wan_clki(31) , input , X ) ,"& " 397 (BC_2, *, control , 1 ) ,"& " 396 (LV_BC_7, pci_cbe_n(0) , bidir , X, 397, 1 , Z ),"& " 395 (BC_2, wan_frmi(31) , input , X ) ,"& " 394 (BC_2, *, control , 1 ) ,"& " 393 (LV_BC_7, pci_ad(7) , bidir , X, 394, 1 , Z ),"& " 392 (BC_2, wan_sti(31) , input , X ) ,"& " 391 (BC_2, *, control , 1 ) ,"& " 390 (LV_BC_7, pci_ad(6) , bidir , X, 391, 1 , Z ),"& " 389 (BC_2, *, control , 1 ) ,"& " 388 (LV_BC_7, pci_ad(5) , bidir , X, 389, 1 , Z ),"& " 387 (BC_2, *, control , 1 ) ,"& " 386 (BC_2, wan_sto(31) , output3 , X, 387, 1 , Z ),"& " 385 (BC_2, wan_clki(30) , input , X ) ,"& " 384 (BC_2, *, control , 1 ) ,"& " 383 (LV_BC_7, pci_ad(4) , bidir , X, 384, 1 , Z ),"& " 382 (BC_2, wan_frmi(30) , input , X ) ,"& " 381 (BC_2, wan_sti(30) , input , X ) ,"& " 380 (BC_2, *, control , 1 ) ,"& " 379 (BC_2, wan_sto(30) , output3 , X, 380, 1 , Z ),"& " 378 (BC_2, *, control , 1 ) ,"& " 377 (LV_BC_7, pci_ad(3) , bidir , X, 378, 1 , Z ),"& " 376 (BC_2, *, control , 1 ) ,"& " 375 (LV_BC_7, pci_ad(2) , bidir , X, 376, 1 , Z ),"& " 374 (BC_2, *, control , 1 ) ,"& " 373 (LV_BC_7, pci_ad(1) , bidir , X, 374, 1 , Z ),"& " 372 (BC_2, *, control , 1 ) ,"& " 371 (LV_BC_7, pci_ad(0) , bidir , X, 372, 1 , Z ),"& " 370 (BC_2, wan_clki(29) , input , X ) ,"& " 369 (BC_2, wan_frmi(29) , input , X ) ,"& " 368 (BC_2, wan_sti(29) , input , X ) ,"& " 367 (BC_2, *, control , 1 ) ,"& " 366 (BC_2, wan_sto(29) , output3 , X, 367, 1 , Z ),"& " 365 (BC_2, wan_clki(28) , input , X ) ,"& " 364 (BC_2, wan_frmi(28) , input , X ) ,"& " 363 (BC_2, wan_sti(28) , input , X ) ,"& " 362 (BC_2, *, control , 1 ) ,"& " 361 (BC_2, wan_sto(28) , output3 , X, 362, 1 , Z ),"& " 360 (BC_2, wan_clki(27) , input , X ) ,"& " 359 (BC_2, wan_frmi(27) , input , X ) ,"& " 358 (BC_2, wan_sti(27) , input , X ) ,"& " 357 (BC_2, *, control , 1 ) ,"& " 356 (BC_2, wan_sto(27) , output3 , X, 357, 1 , Z ),"& " 355 (BC_2, wan_clki(26) , input , X ) ,"& " 354 (BC_2, wan_frmi(26) , input , X ) ,"& " 353 (BC_2, wan_sti(26) , input , X ) ,"& " 352 (BC_2, *, control , 1 ) ,"& " 351 (BC_2, wan_sto(26) , output3 , X, 352, 1 , Z ),"& " 350 (BC_2, wan_clki(25) , input , X ) ,"& " 349 (BC_2, wan_frmi(25) , input , X ) ,"& " 348 (BC_2, wan_sti(25) , input , X ) ,"& " 347 (BC_2, *, control , 1 ) ,"& " 346 (BC_2, wan_sto(25) , output3 , X, 347, 1 , Z ),"& " 345 (BC_2, wan_clki(24) , input , X ) ,"& " 344 (BC_2, wan_frmi(24) , input , X ) ,"& " 343 (BC_2, wan_sti(24) , input , X ) ,"& " 342 (BC_2, *, control , 1 ) ,"& " 341 (BC_2, wan_sto(24) , output3 , X, 342, 1 , Z ),"& " 340 (BC_2, wan_clki(23) , input , X ) ,"& " 339 (BC_2, wan_frmi(23) , input , X ) ,"& " 338 (BC_2, wan_sti(23) , input , X ) ,"& " 337 (BC_2, *, control , 1 ) ,"& " 336 (BC_2, wan_sto(23) , output3 , X, 337, 1 , Z ),"& " 335 (BC_2, wan_clki(22) , input , X ) ,"& " 334 (BC_2, wan_frmi(22) , input , X ) ,"& " 333 (BC_2, wan_sti(22) , input , X ) ,"& " 332 (BC_2, *, control , 1 ) ,"& " 331 (BC_2, wan_sto(22) , output3 , X, 332, 1 , Z ),"& " 330 (BC_2, wan_clki(21) , input , X ) ,"& " 329 (BC_2, wan_frmi(21) , input , X ) ,"& " 328 (BC_2, wan_sti(21) , input , X ) ,"& " 327 (BC_2, *, control , 1 ) ,"& " 326 (BC_2, wan_sto(21) , output3 , X, 327, 1 , Z ),"& " 325 (BC_2, wan_clki(20) , input , X ) ,"& " 324 (BC_2, wan_frmi(20) , input , X ) ,"& " 323 (BC_2, *, control , 1 ) ,"& " 322 (BC_2, wan_sto(20) , output3 , X, 323, 1 , Z ),"& " 321 (BC_2, wan_sti(20) , input , X ) ,"& " 320 (BC_2, wan_clki(19) , input , X ) ,"& " 319 (BC_2, wan_frmi(19) , input , X ) ,"& " 318 (BC_2, wan_sti(19) , input , X ) ,"& " 317 (BC_2, *, control , 1 ) ,"& " 316 (BC_2, wan_sto(19) , output3 , X, 317, 1 , Z ),"& " 315 (BC_2, wan_clki(18) , input , X ) ,"& " 314 (BC_2, wan_frmi(18) , input , X ) ,"& " 313 (BC_2, *, control , 1 ) ,"& " 312 (BC_2, rstout_b , output3 , X, 313, 1 , Z ),"& " 311 (BC_4, s_clk , clock , X ) ,"& " 310 (BC_2, wan_sti(18) , input , X ) ,"& " 309 (BC_2, *, control , 1 ) ,"& " 308 (BC_2, wan_sto(18) , output3 , X, 309, 1 , Z ),"& " 307 (BC_2, wan_clki(17) , input , X ) ,"& " 306 (BC_2, wan_frmi(17) , input , X ) ,"& " 305 (BC_2, wan_sti(17) , input , X ) ,"& " 304 (BC_2, *, control , 1 ) ,"& " 303 (BC_2, wan_sto(17) , output3 , X, 304, 1 , Z ),"& " 302 (BC_2, wan_clki(16) , input , X ) ,"& " 301 (BC_2, wan_frmi(16) , input , X ) ,"& " 300 (BC_2, wan_sti(16) , input , X ) ,"& " 299 (BC_2, *, control , 1 ) ,"& " 298 (BC_2, wan_sto(16) , output3 , X, 299, 1 , Z ),"& " 297 (BC_2, wan_clki(15) , input , X ) ,"& " 296 (BC_2, wan_frmi(15) , input , X ) ,"& " 295 (BC_2, wan_sti(15) , input , X ) ,"& " 294 (BC_2, *, control , 1 ) ,"& " 293 (BC_2, wan_sto(15) , output3 , X, 294, 1 , Z ),"& " 292 (BC_2, wan_clki(14) , input , X ) ,"& " 291 (BC_2, wan_frmi(14) , input , X ) ,"& " 290 (BC_2, wan_sti(14) , input , X ) ,"& " 289 (BC_2, *, control , 1 ) ,"& " 288 (BC_2, wan_sto(14) , output3 , X, 289, 1 , Z ),"& " 287 (BC_2, wan_clki(13) , input , X ) ,"& " 286 (BC_2, wan_frmi(13) , input , X ) ,"& " 285 (BC_2, wan_sti(13) , input , X ) ,"& " 284 (BC_2, *, control , 1 ) ,"& " 283 (BC_2, wan_sto(13) , output3 , X, 284, 1 , Z ),"& " 282 (BC_2, wan_clki(12) , input , X ) ,"& " 281 (BC_2, wan_frmi(12) , input , X ) ,"& " 280 (BC_2, wan_sti(12) , input , X ) ,"& " 279 (BC_2, *, control , 1 ) ,"& " 278 (BC_2, wan_sto(12) , output3 , X, 279, 1 , Z ),"& " 277 (BC_2, wan_clki(11) , input , X ) ,"& " 276 (BC_2, wan_frmi(11) , input , X ) ,"& " 275 (BC_2, wan_sti(11) , input , X ) ,"& " 274 (BC_2, *, control , 1 ) ,"& " 273 (BC_2, wan_sto(11) , output3 , X, 274, 1 , Z ),"& " 272 (BC_2, wan_clki(10) , input , X ) ,"& " 271 (BC_2, wan_frmi(10) , input , X ) ,"& " 270 (BC_2, wan_sti(10) , input , X ) ,"& " 269 (BC_2, *, control , 1 ) ,"& " 268 (BC_2, wan_sto(10) , output3 , X, 269, 1 , Z ),"& " 267 (BC_2, wan_clki(9) , input , X ) ,"& " 266 (BC_2, wan_frmi(9) , input , X ) ,"& " 265 (BC_2, wan_sti(9), input , X ) ,"& " 264 (BC_2, *, control , 1 ) ,"& " 263 (BC_2, wan_sto(9), output3 , X, 264, 1 , Z ),"& " 262 (BC_2, wan_clki(8) , input , X ) ,"& " 261 (BC_2, wan_frmi(8) , input , X ) ,"& " 260 (BC_2, wan_sti(8), input , X ) ,"& " 259 (BC_2, *, control , 1 ) ,"& " 258 (BC_2, wan_sto(8), output3 , X, 259, 1 , Z ),"& " 257 (BC_2, wan_clki(7) , input , X ) ,"& " 256 (BC_2, wan_frmi(7) , input , X ) ,"& " 255 (BC_2, wan_sti(7), input , X ) ,"& " 254 (BC_2, *, control , 1 ) ,"& " 253 (BC_2, wan_sto(7), output3 , X, 254, 1 , Z ),"& " 252 (BC_2, wan_clki(6) , input , X ) ,"& " 251 (BC_2, wan_frmi(6) , input , X ) ,"& " 250 (BC_2, wan_sti(6), input , X ) ,"& " 249 (BC_2, *, control , 1 ) ,"& " 248 (BC_2, wan_sto(6), output3 , X, 249, 1 , Z ),"& " 247 (BC_2, wan_clki(5) , input , X ) ,"& " 246 (BC_2, wan_frmi(5) , input , X ) ,"& " 245 (BC_2, wan_sti(5), input , X ) ,"& " 244 (BC_2, *, control , 1 ) ,"& " 243 (BC_2, wan_sto(5), output3 , X, 244, 1 , Z ),"& " 242 (BC_2, wan_clki(4) , input , X ) ,"& " 241 (BC_2, wan_frmi(4) , input , X ) ,"& " 240 (BC_2, wan_sti(4), input , X ) ,"& " 239 (BC_2, *, control , 1 ) ,"& " 238 (BC_2, wan_sto(4), output3 , X, 239, 1 , Z ),"& " 237 (BC_2, wan_clki(3) , input , X ) ,"& " 236 (BC_2, wan_frmi(3) , input , X ) ,"& " 235 (BC_2, wan_sti(3), input , X ) ,"& " 234 (BC_2, *, control , 1 ) ,"& " 233 (BC_2, wan_sto(3), output3 , X, 234, 1 , Z ),"& " 232 (BC_2, wan_clki(2) , input , X ) ,"& " 231 (BC_2, wan_frmi(2) , input , X ) ,"& " 230 (BC_2, wan_sti(2), input , X ) ,"& " 229 (BC_2, *, control , 1 ) ,"& " 228 (BC_2, wan_sto(2), output3 , X, 229, 1 , Z ),"& " 227 (BC_2, wan_clki(1) , input , X ) ,"& " 226 (BC_2, wan_frmi(1) , input , X ) ,"& " 225 (BC_2, wan_sti(1), input , X ) ,"& " 224 (BC_2, *, control , 1 ) ,"& " 223 (BC_2, wan_sto(1), output3 , X, 224, 1 , Z ),"& " 222 (BC_2, wan_clki(0) , input , X ) ,"& " 221 (BC_2, wan_frmi(0) , input , X ) ,"& " 220 (BC_2, wan_sti(0), input , X ) ,"& " 219 (BC_2, *, control , 1 ) ,"& " 218 (BC_2, wan_sto(0), output3 , X, 219, 1 , Z ),"& " 217 (BC_2, ode , input , X ) ,"& " 216 (BC_2, *, control , 1 ) ,"& " 215 (BC_2, c4ob , output3 , X, 216, 1 , Z ),"& " 214 (BC_2, *, control , 1 ) ,"& " 213 (BC_2, c8ob , output3 , X, 214, 1 , Z ),"& " 212 (BC_2, *, control , 1 ) ,"& " 211 (BC_2, c16ob , output3 , X, 212, 1 , Z ),"& " 210 (BC_2, *, control , 1 ) ,"& " 209 (BC_2, fp4ob , output3 , X, 210, 1 , Z ),"& " 208 (BC_2, *, control , 1 ) ,"& " 207 (BC_2, fp8ob , output3 , X, 208, 1 , Z ),"& " 206 (BC_2, *, control , 1 ) ,"& " 205 (BC_2, fp16ob, output3 , X, 206, 1 , Z ),"& " 204 (BC_2, *, control , 1 ) ,"& " 203 (LV_BC_7, ram_d(31) , bidir , X, 204, 1 , Z ),"& " 202 (BC_2, *, control , 1 ) ,"& " 201 (LV_BC_7, ram_d(30) , bidir , X, 202, 1 , Z ),"& " 200 (BC_2, *, control , 1 ) ,"& " 199 (LV_BC_7, ram_d(29) , bidir , X, 200, 1 , Z ),"& " 198 (BC_2, *, control , 1 ) ,"& " 197 (LV_BC_7, ram_d(28) , bidir , X, 198, 1 , Z ),"& " 196 (BC_2, *, control , 1 ) ,"& " 195 (LV_BC_7, ram_d(27) , bidir , X, 196, 1 , Z ),"& " 194 (BC_2, *, control , 1 ) ,"& " 193 (LV_BC_7, ram_d(26) , bidir , X, 194, 1 , Z ),"& " 192 (BC_2, *, control , 1 ) ,"& " 191 (LV_BC_7, ram_d(25) , bidir , X, 192, 1 , Z ),"& " 190 (BC_2, *, control , 1 ) ,"& " 189 (LV_BC_7, ram_d(24) , bidir , X, 190, 1 , Z ),"& " 188 (BC_2, *, control , 1 ) ,"& " 187 (LV_BC_7, ram_d(23) , bidir , X, 188, 1 , Z ),"& " 186 (BC_2, *, control , 1 ) ,"& " 185 (BC_2, ram_a(22) , output3 , X, 186, 1 , Z ),"& " 184 (BC_2, *, control , 1 ) ,"& " 183 (BC_2, ram_a(21) , output3 , X, 184, 1 , Z ),"& " 182 (BC_2, *, control , 1 ) ,"& " 181 (BC_2, ram_a(20) , output3 , X, 182, 1 , Z ),"& " 180 (BC_2, *, control , 1 ) ,"& " 179 (BC_2, ram_a(19) , output3 , X, 180, 1 , Z ),"& " 178 (BC_2, *, control , 1 ) ,"& " 177 (BC_2, ram_a(18) , output3 , X, 178, 1 , Z ),"& " 176 (BC_2, *, control , 1 ) ,"& " 175 (BC_2, ram_a(17) , output3 , X, 176, 1 , Z ),"& " 174 (BC_2, *, control , 1 ) ,"& " 173 (BC_2, ram_a(16) , output3 , X, 174, 1 , Z ),"& " 172 (BC_2, *, control , 1 ) ,"& " 171 (BC_2, ram_a(15) , output3 , X, 172, 1 , Z ),"& " 170 (BC_2, *, control , 1 ) ,"& " 169 (BC_2, ram_a(14) , output3 , X, 170, 1 , Z ),"& " 168 (BC_2, *, control , 1 ) ,"& " 167 (BC_2, ram_a(13) , output3 , X, 168, 1 , Z ),"& " 166 (BC_2, *, control , 1 ) ,"& " 165 (BC_2, ram_a(12) , output3 , X, 166, 1 , Z ),"& " 164 (BC_2, *, control , 1 ) ,"& " 163 (BC_2, ram_a(11) , output3 , X, 164, 1 , Z ),"& " 162 (BC_2, *, control , 1 ) ,"& " 161 (BC_2, ram_a(10) , output3 , X, 162, 1 , Z ),"& " 160 (BC_2, *, control , 1 ) ,"& " 159 (BC_2, ram_a(9) , output3 , X, 160, 1 , Z ),"& " 158 (BC_2, *, control , 1 ) ,"& " 157 (BC_2, ram_a(8) , output3 , X, 158, 1 , Z ),"& " 156 (BC_2, *, control , 1 ) ,"& " 155 (BC_2, ram_a(7) , output3 , X, 156, 1 , Z ),"& " 154 (BC_2, *, control , 1 ) ,"& " 153 (BC_2, ram_a(6) , output3 , X, 154, 1 , Z ),"& " 152 (BC_2, *, control , 1 ) ,"& " 151 (BC_2, ram_a(5) , output3 , X, 152, 1 , Z ),"& " 150 (BC_2, *, control , 1 ) ,"& " 149 (BC_2, ram_a(4) , output3 , X, 150, 1 , Z ),"& " 148 (BC_2, *, control , 1 ) ,"& " 147 (BC_2, ram_a(3) , output3 , X, 148, 1 , Z ),"& " 146 (BC_2, *, control , 1 ) ,"& " 145 (BC_2, ram_a(2) , output3 , X, 146, 1 , Z ),"& " 144 (BC_2, *, control , 1 ) ,"& " 143 (BC_2, ram_clk , output3 , X, 144, 1 , Z ),"& " 142 (BC_2, *, control , 1 ) ,"& " 141 (BC_2, ram_rw3_b , output3 , X, 142, 1 , Z ),"& " 140 (BC_2, *, control , 1 ) ,"& " 139 (BC_2, ram_rw2_b , output3 , X, 140, 1 , Z ),"& " 138 (BC_2, *, control , 1 ) ,"& " 137 (BC_2, ram_rw1_b , output3 , X, 138, 1 , Z ),"& " 136 (BC_2, *, control , 1 ) ,"& " 135 (BC_2, ram_rw0_b , output3 , X, 136, 1 , Z ),"& " 134 (BC_2, *, control , 1 ) ,"& " 133 (BC_2, ram_oe3_b , output3 , X, 134, 1 , Z ),"& " 132 (BC_2, *, control , 1 ) ,"& " 131 (BC_2, ram_oe2_b , output3 , X, 132, 1 , Z ),"& " 130 (BC_2, *, control , 1 ) ,"& " 129 (BC_2, ram_oe1_b , output3 , X, 130, 1 , Z ),"& " 128 (BC_2, *, control , 1 ) ,"& " 127 (BC_2, ram_oe0_b , output3 , X, 128, 1 , Z ),"& " 126 (BC_2, *, control , 1 ) ,"& " 125 (BC_2, ram_adsc_b, output3 , X, 126, 1 , Z ),"& " 124 (BC_2, *, control , 1 ) ,"& " 123 (LV_BC_7, ram_d(22) , bidir , X, 124, 1 , Z ),"& " 122 (BC_2, *, control , 1 ) ,"& " 121 (LV_BC_7, ram_d(21) , bidir , X, 122, 1 , Z ),"& " 120 (BC_2, *, control , 1 ) ,"& " 119 (LV_BC_7, ram_d(20) , bidir , X, 120, 1 , Z ),"& " 118 (BC_2, *, control , 1 ) ,"& " 117 (LV_BC_7, ram_d(19) , bidir , X, 118, 1 , Z ),"& " 116 (BC_2, *, control , 1 ) ,"& " 115 (LV_BC_7, ram_d(18) , bidir , X, 116, 1 , Z ),"& " 114 (BC_2, *, control , 1 ) ,"& " 113 (LV_BC_7, ram_d(17) , bidir , X, 114, 1 , Z ),"& " 112 (BC_2, *, control , 1 ) ,"& " 111 (LV_BC_7, ram_d(16) , bidir , X, 112, 1 , Z ),"& " 110 (BC_2, *, control , 1 ) ,"& " 109 (LV_BC_7, ram_d(15) , bidir , X, 110, 1 , Z ),"& " 108 (BC_2, *, control , 1 ) ,"& " 107 (LV_BC_7, ram_d(14) , bidir , X, 108, 1 , Z ),"& " 106 (BC_2, *, control , 1 ) ,"& " 105 (LV_BC_7, ram_d(13) , bidir , X, 106, 1 , Z ),"& " 104 (BC_2, *, control , 1 ) ,"& " 103 (LV_BC_7, ram_d(12) , bidir , X, 104, 1 , Z ),"& " 102 (BC_2, *, control , 1 ) ,"& " 101 (LV_BC_7, ram_d(11) , bidir , X, 102, 1 , Z ),"& " 100 (BC_2, *, control , 1 ) ,"& " 99 (LV_BC_7, ram_d(10) , bidir , X, 100, 1 , Z ),"& " 98 (BC_2, *, control , 1 ) ,"& " 97 (LV_BC_7, ram_d(9) , bidir , X, 98 , 1 , Z ),"& " 96 (BC_2, *, control , 1 ) ,"& " 95 (LV_BC_7, ram_d(8) , bidir , X, 96 , 1 , Z ),"& " 94 (BC_2, *, control , 1 ) ,"& " 93 (LV_BC_7, ram_d(7) , bidir , X, 94 , 1 , Z ),"& " 92 (BC_2, *, control , 1 ) ,"& " 91 (LV_BC_7, ram_d(6) , bidir , X, 92 , 1 , Z ),"& " 90 (BC_2, *, control , 1 ) ,"& " 89 (LV_BC_7, ram_d(5) , bidir , X, 90 , 1 , Z ),"& " 88 (BC_2, *, control , 1 ) ,"& " 87 (LV_BC_7, ram_d(4) , bidir , X, 88 , 1 , Z ),"& " 86 (BC_2, *, control , 1 ) ,"& " 85 (LV_BC_7, ram_d(3) , bidir , X, 86 , 1 , Z ),"& " 84 (BC_2, *, control , 1 ) ,"& " 83 (LV_BC_7, ram_d(2) , bidir , X, 84 , 1 , Z ),"& " 82 (BC_2, *, control , 1 ) ,"& " 81 (LV_BC_7, ram_d(1) , bidir , X, 82 , 1 , Z ),"& " 80 (BC_2, *, control , 1 ) ,"& " 79 (LV_BC_7, ram_d(0) , bidir , X, 80 , 1 , Z ),"& " 78 (BC_2, *, control , 1 ) ,"& " 77 (BC_2, m0_txen , output3 , X, 78 , 1 , Z ),"& " 76 (BC_2, *, control , 1 ) ,"& " 75 (BC_2, m0_txd(3) , output3 , X, 76 , 1 , Z ),"& " 74 (BC_2, *, control , 1 ) ,"& " 73 (BC_2, m0_txd(2) , output3 , X, 74 , 1 , Z ),"& " 72 (BC_2, *, control , 1 ) ,"& " 71 (BC_2, m0_txd(1) , output3 , X, 72 , 1 , Z ),"& " 70 (BC_2, *, control , 1 ) ,"& " 69 (BC_2, m0_txd(0) , output3 , X, 70 , 1 , Z ),"& " 68 (BC_2, m_mint0 , input , X ) ,"& " 67 (BC_4, m0_txclk , clock , X ) ,"& " 66 (BC_2, m0_col, input , X ) ,"& " 65 (BC_2, m0_crs, input , X ) ,"& " 64 (BC_2, m0_rxer , input , X ) ,"& " 63 (BC_4, m0_rxclk , clock , X ) ,"& " 62 (BC_2, m0_rxdv , input , X ) ,"& " 61 (BC_2, m0_rxd(3) , input , X ) ,"& " 60 (BC_2, m0_rxd(2) , input , X ) ,"& " 59 (BC_2, m0_rxd(1) , input , X ) ,"& " 58 (BC_2, m0_rxd(0) , input , X ) ,"& " 57 (BC_2, *, control , 1 ) ,"& " 56 (LV_BC_7, m_mdio, bidir , X, 57 , 1 , Z ),"& " 55 (BC_2, *, control , 1 ) ,"& " 54 (LV_BC_7, m_mdc , bidir , X, 55 , 1 , Z ),"& " 53 (BC_4, refclk, clock , X ) ,"& " 52 (BC_2, *, control , 1 ) ,"& " 51 (BC_2, m1_txen , output3 , X, 52 , 1 , Z ),"& " 50 (BC_2, *, control , 1 ) ,"& " 49 (BC_2, m1_txd(3) , output3 , X, 50 , 1 , Z ),"& " 48 (BC_2, *, control , 1 ) ,"& " 47 (BC_2, m1_txd(2) , output3 , X, 48 , 1 , Z ),"& " 46 (BC_2, *, control , 1 ) ,"& " 45 (BC_2, m1_txd(1) , output3 , X, 46 , 1 , Z ),"& " 44 (BC_2, *, control , 1 ) ,"& " 43 (BC_2, m1_txd(0) , output3 , X, 44 , 1 , Z ),"& " 42 (BC_2, m_mint1 , input , X ) ,"& " 41 (BC_4, m1_txclk , clock , X ) ,"& " 40 (BC_2, m1_col, input , X ) ,"& " 39 (BC_2, m1_crs, input , X ) ,"& " 38 (BC_2, m1_rxer , input , X ) ,"& " 37 (BC_4, m1_rxclk , clock , X ) ,"& " 36 (BC_2, m1_rxdv , input , X ) ,"& " 35 (BC_2, m1_rxd(3) , input , X ) ,"& " 34 (BC_2, m1_rxd(2) , input , X ) ,"& " 33 (BC_2, m1_rxd(1) , input , X ) ,"& " 32 (BC_2, m1_rxd(0) , input , X ) ,"& " 31 (BC_2, *, control , 1 ) ,"& " 30 (LV_BC_7, t_d(15) , bidir , X, 31 , 1 , Z ),"& " 29 (BC_2, *, control , 1 ) ,"& " 28 (LV_BC_7, t_d(14) , bidir , X, 29 , 1 , Z ),"& " 27 (BC_2, *, control , 1 ) ,"& " 26 (LV_BC_7, t_d(13) , bidir , X, 27 , 1 , Z ),"& " 25 (BC_2, *, control , 1 ) ,"& " 24 (LV_BC_7, t_d(12) , bidir , X, 25 , 1 , Z ),"& " 23 (BC_2, *, control , 1 ) ,"& " 22 (LV_BC_7, t_d(11) , bidir , X, 23 , 1 , Z ),"& " 21 (BC_2, *, control , 1 ) ,"& " 20 (LV_BC_7, t_d(10) , bidir , X, 21 , 1 , Z ),"& " 19 (BC_2, *, control , 1 ) ,"& " 18 (LV_BC_7, t_d(9), bidir , X, 19 , 1 , Z ),"& " 17 (BC_2, *, control , 1 ) ,"& " 16 (LV_BC_7, t_d(8), bidir , X, 17 , 1 , Z ),"& " 15 (BC_2, *, control , 1 ) ,"& " 14 (LV_BC_7, t_d(7), bidir , X, 15 , 1 , Z ),"& " 13 (BC_2, *, control , 1 ) ,"& " 12 (LV_BC_7, t_d(6), bidir , X, 13 , 1 , Z ),"& " 11 (BC_2, *, control , 1 ) ,"& " 10 (LV_BC_7, t_d(5), bidir , X, 11 , 1 , Z ),"& " 9 (BC_2, *, control , 1 ) ,"& " 8 (LV_BC_7, t_d(4), bidir , X, 9 , 1 , Z ),"& " 7 (BC_2, *, control , 1 ) ,"& " 6 (LV_BC_7, t_d(3), bidir , X, 7 , 1 , Z ),"& " 5 (BC_2, *, control , 1 ) ,"& " 4 (LV_BC_7, t_d(2), bidir , X, 5 , 1 , Z ),"& " 3 (BC_2, *, control , 1 ) ,"& " 2 (LV_BC_7, t_d(1), bidir , X, 3 , 1 , Z ),"& " 1 (BC_2, *, control , 1 ) ,"& " 0 (LV_BC_7, t_d(0), bidir , X, 1 , 1 , Z ) "; end mt90881;