--------------------------------------------------------------------------- -- Boundary Scan Description Language (IEEE 1149.1b) -- BSDL for Device CX28229 -- BSDL File Created by 'topgen' revision 3.18 -- (c) 2001 Mindspeed Technologies Inc. --------------------------------------------------------------------------- -- -- Mindspeed Technologies Inc. hereby grants the user of this source code a -- non-exclusive, nontransferable license to use this source code under the -- following terms. Before using this source code, the user should read this -- license. If the user does not accept these terms, the source code should be -- returned to Mindspeed Technologies Inc. within 30 days. -- -- The user is granted this license only to use the source code and is not -- granted rights to sell, load, rent, lease or license the source code in whole -- or in part, or in modified form to anyone other than user. User may modify -- the source code to suit its specific applications but rights to derivative -- works and such modifications shall belong to Mindspeed Technologies Inc. -- -- This source code is provided on an "AS IS" basis and -- Mindspeed Technologies Inc. makes absolutely no warranty with respect to the -- information contained herein. Mindspeed Technologies Inc. DISCLAIMS AND -- CUSTOMER WAIVES ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. The entire risk as to -- quality and performance is with the Customer. ACCORDINGLY, IN NO EVENT SHALL -- Mindspeed Technologies Inc. BE LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR -- TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, -- EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE -- SOURCE CODE PROVIDED IN THIS PACKAGE. -- -- Further, Mindspeed Technologies Inc. reserves the right to make -- changes without notice to any product herein to improve reliability, -- function, or design. Mindspeed Technologies Inc. does not convey any -- license under patent rights or any other intellectual property rights, -- including those of third parties. -- -- Mindspeed Technologies Inc. is not obligated to provide maintenance or -- support for the licensed source code. --------------------------------------------------------------------------- entity CX28229 is generic ( PHYSICAL_PIN_MAP : string := "BGA_256" ); port ( MICRO_W_N : in bit; MICRO_CS : in bit; MICRO_AS : in bit; MICRO_ADDR0 : in bit; MICRO_ADDR1 : in bit; MICRO_ADDR2 : in bit; MICRO_ADDR3 : in bit; MICRO_ADDR4 : in bit; MICRO_ADDR5 : in bit; MICRO_ADDR6 : in bit; MICRO_ADDR7 : in bit; MICRO_ADDR8 : in bit; MICRO_ADDR9 : in bit; MEM_ADDR0 : out bit; MEM_ADDR1 : out bit; MEM_ADDR2 : out bit; MEM_ADDR3 : out bit; MEM_ADDR4 : out bit; MEM_ADDR5 : out bit; MEM_ADDR6 : out bit; MEM_ADDR7 : out bit; MEM_ADDR8 : out bit; MEM_ADDR9 : out bit; MEM_ADDR10 : out bit; MEM_ADDR11 : out bit; MEM_ADDR12 : out bit; MEM_ADDR13 : out bit; MEM_ADDR14 : out bit; MEM_ADDR15 : out bit; BONDOUT0 : in bit; MEM_ADDR16 : out bit; MEM_ADDR17 : out bit; MEM_ADDR18 : out bit; MEM_CE : out bit; MEM_OE : out bit; MEM_WE : out bit; MEM_CLK : out bit; MEM_ADSC : out bit; MICRO_ADDR10 : in bit; STATOUT0 : out bit; STATOUT1 : out bit; MICRO_DATA0 : inout bit; MICRO_DATA1 : inout bit; MICRO_DATA2 : inout bit; MICRO_DATA3 : inout bit; MEM_ADDR19 : out bit; TXTRL0 : out bit; MICRO_DATA4 : inout bit; MICRO_DATA5 : inout bit; MICRO_DATA6 : inout bit; MICRO_DATA7 : inout bit; MICRO_INT : out bit; MICRO_RDY : out bit; MICRO_CLK : in bit; MICRO_SYNCMODE : in bit; PHY_MUX_SELECT : in bit; TEST_ENABLE : in bit; TEST_MODE : in bit; RESET_N : in bit; ONESEC_CLK : in bit; ONESEC_IO : inout bit; MEM_DATA0 : inout bit; MEM_DATA1 : inout bit; MEM_DATA2 : inout bit; MEM_DATA3 : inout bit; MEM_DATA4 : inout bit; PHY_RX_ADDR0 : out bit; PHY_RX_CLK : inout bit; PHY_RX_ENB0_N : out bit; PHY_RX_ADDR1 : out bit; PHY_RX_ADDR2 : out bit; PHY_RX_ADDR3 : out bit; PHY_RX_ADDR4 : out bit; PHY_RX_CLAV0 : in bit; PHY_RX_DATA0 : in bit; PHY_RX_DATA1 : in bit; PHY_RX_DATA2 : in bit; PHY_RX_DATA3 : in bit; MEM_DATA5 : inout bit; MEM_DATA6 : inout bit; MEM_DATA7 : inout bit; MEM_DATA8 : inout bit; MEM_DATA9 : inout bit; MEM_DATA10 : inout bit; MEM_DATA11 : inout bit; MEM_DATA12 : inout bit; MEM_DATA13 : inout bit; PHY_RX_DATA4 : in bit; PHY_RX_DATA5 : in bit; PHY_RX_DATA6 : in bit; PHY_RX_DATA7 : in bit; PHY_TX_ADDR1 : out bit; PHY_TX_ADDR2 : out bit; PHY_RX_ENB1_N : out bit; PHY_RX_SOC : in bit; PHY_TX_ADDR0 : out bit; PHY_TX_CLAV0 : in bit; PHY_TX_CLK : inout bit; PHY_TX_CLAV1 : in bit; PHY_RX_CLAV1 : in bit; PHY_TX_DATA0 : inout bit; PHY_TX_DATA1 : inout bit; PHY_TX_DATA2 : inout bit; PHY_TX_DATA3 : inout bit; PHY_TX_DATA4 : inout bit; PHY_TX_DATA5 : inout bit; PHY_TX_DATA6 : inout bit; PHY_TX_DATA7 : inout bit; PHY_TX_ENB0_N : out bit; IMA_SYSCLK : in bit; IMA_REFCLK : in bit; PHY_TX_ADDR3 : out bit; PHY_TX_ADDR4 : out bit; BONDOUT1 : in bit; TC_RX_CLK2 : in bit; TC_RX_CLK3 : in bit; TC_RX_CLK4 : in bit; TC_RX_CLK5 : in bit; TC_RX_CLK6 : in bit; TC_RX_CLK7 : in bit; TC_RX_DATA3 : in bit; TC_RX_DATA4 : in bit; TC_RX_DATA5 : in bit; TC_RX_DATA6 : in bit; TC_RX_DATA7 : in bit; ATM_TX_DATA8 : in bit; ATM_TX_DATA9 : in bit; ATM_TX_DATA10 : in bit; ATM_TX_DATA11 : in bit; ATM_TX_DATA12 : in bit; ATM_TX_DATA13 : in bit; TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TRST_N : in bit; PHY_TX_SOC : inout bit; ATM_TX_ADDR0 : in bit; ATM_TX_ADDR1 : in bit; ATM_TX_ADDR2 : in bit; ATM_TX_ADDR3 : in bit; ATM_TX_ADDR4 : in bit; PHY_TX_ENB1_N : out bit; EXTMEMSEL : in bit; ATM_TX_DATA0 : in bit; ATM_TX_DATA1 : in bit; ATM_TX_DATA2 : in bit; ATM_TX_DATA3 : in bit; ATM_TX_DATA14 : in bit; ATM_TX_DATA15 : in bit; ATM_TX_DATA4 : in bit; ATM_TX_DATA5 : in bit; ATM_TX_DATA6 : in bit; ATM_TX_DATA7 : in bit; ATM_TX_PRTY : in bit; ATM_TX_CLAV : out bit; ATM_TX_SOC : in bit; ATM_TX_ENB_N : in bit; ATM_TX_CLK : in bit; ATM_RX_DATA8 : out bit; ATM_RX_DATA9 : out bit; ATM_RX_DATA10 : out bit; ATM_RX_DATA11 : out bit; ATM_RX_DATA12 : out bit; ATM_RX_DATA13 : out bit; ATM_RX_DATA14 : out bit; ATM_RX_DATA15 : out bit; ATM_RX_SOC : out bit; ATM_RX_CLK : in bit; ATM_RX_CLAV : out bit; ATM_RX_ENB_N : in bit; ATM_RX_DATA0 : out bit; ATM_RX_DATA1 : out bit; ATM_RX_DATA2 : out bit; ATM_RX_DATA3 : out bit; TC_RX_SYNC3 : in bit; TC_RX_SYNC4 : in bit; TC_RX_SYNC5 : in bit; TC_RX_SYNC6 : in bit; TC_RX_SYNC7 : in bit; MEM_DATA14 : inout bit; MEM_DATA15 : inout bit; ATM_RX_DATA4 : out bit; ATM_RX_DATA5 : out bit; ATM_RX_DATA6 : out bit; ATM_RX_DATA7 : out bit; ATM_RX_PRTY : out bit; ATM_RX_ADDR0 : in bit; ATM_RX_ADDR1 : in bit; ATM_RX_ADDR2 : in bit; ATM_RX_ADDR3 : in bit; ATM_RX_ADDR4 : in bit; TXTRL1 : out bit; VDDC_G11 : linkage bit; VDDC_G12 : linkage bit; VDDC_G5 : linkage bit; VDDC_G6 : linkage bit; VDDC_H11 : linkage bit; VDDC_H12 : linkage bit; VDDC_H5 : linkage bit; VDDC_H6 : linkage bit; VDDC_J11 : linkage bit; VDDC_J12 : linkage bit; VDDC_J5 : linkage bit; VDDC_J6 : linkage bit; VDDC_K11 : linkage bit; VDDC_K12 : linkage bit; VDDC_K5 : linkage bit; VDDC_K6 : linkage bit; VDDIO_E10 : linkage bit; VDDIO_E11 : linkage bit; VDDIO_E12 : linkage bit; VDDIO_E5 : linkage bit; VDDIO_E6 : linkage bit; VDDIO_E7 : linkage bit; VDDIO_E8 : linkage bit; VDDIO_E9 : linkage bit; VDDIO_F10 : linkage bit; VDDIO_F11 : linkage bit; VDDIO_F12 : linkage bit; VDDIO_F5 : linkage bit; VDDIO_F6 : linkage bit; VDDIO_F7 : linkage bit; VDDIO_F8 : linkage bit; VDDIO_F9 : linkage bit; VDDIO_L10 : linkage bit; VDDIO_L11 : linkage bit; VDDIO_L12 : linkage bit; VDDIO_L5 : linkage bit; VDDIO_L6 : linkage bit; VDDIO_L7 : linkage bit; VDDIO_L8 : linkage bit; VDDIO_L9 : linkage bit; VDDIO_M10 : linkage bit; VDDIO_M11 : linkage bit; VDDIO_M12 : linkage bit; VDDIO_M5 : linkage bit; VDDIO_M6 : linkage bit; VDDIO_M7 : linkage bit; VDDIO_M8 : linkage bit; VDDIO_M9 : linkage bit; VGG_B3 : linkage bit; VSS_G10 : linkage bit; VSS_G7 : linkage bit; VSS_G8 : linkage bit; VSS_G9 : linkage bit; VSS_H10 : linkage bit; VSS_H7 : linkage bit; VSS_H8 : linkage bit; VSS_H9 : linkage bit; VSS_J10 : linkage bit; VSS_J7 : linkage bit; VSS_J8 : linkage bit; VSS_J9 : linkage bit; VSS_K10 : linkage bit; VSS_K7 : linkage bit; VSS_K8 : linkage bit; VSS_K9 : linkage bit ); -- Libraries -- bcad won't recognize the reference to the work library. -- use work.STD_1149_1_1994.all; use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of CX28229 : entity is "STD_1149_1_1993"; attribute PIN_MAP of CX28229 : entity is PHYSICAL_PIN_MAP; constant BGA_256: PIN_MAP_STRING := "MICRO_W_N : A2," & "MICRO_CS : B2," & "MICRO_AS : A1," & "MICRO_ADDR0 : B1," & "MICRO_ADDR1 : C2," & "MICRO_ADDR2 : E4," & "MICRO_ADDR3 : D2," & "MICRO_ADDR4 : C1," & "MICRO_ADDR5 : D1," & "MICRO_ADDR6 : E3," & "MICRO_ADDR7 : F4," & "MICRO_ADDR8 : E2," & "MICRO_ADDR9 : E1," & "MEM_ADDR0 : F3," & "MEM_ADDR1 : F2," & "MEM_ADDR2 : G4," & "MEM_ADDR3 : G3," & "MEM_ADDR4 : F1," & "MEM_ADDR5 : G2," & "MEM_ADDR6 : H4," & "MEM_ADDR7 : G1," & "MEM_ADDR8 : H3," & "MEM_ADDR9 : H1," & "MEM_ADDR10 : H2," & "MEM_ADDR11 : J4," & "MEM_ADDR12 : J3," & "MEM_ADDR13 : J1," & "MEM_ADDR14 : J2," & "MEM_ADDR15 : K3," & "BONDOUT0 : NC1," & "MEM_ADDR16 : K4," & "MEM_ADDR17 : K1," & "MEM_ADDR18 : K2," & "MEM_CE : L3," & "MEM_OE : L4," & "MEM_WE : L1," & "MEM_CLK : L2," & "MEM_ADSC : M3," & "MICRO_ADDR10 : M4," & "STATOUT0 : M1," & "STATOUT1 : M2," & "MICRO_DATA0 : N3," & "MICRO_DATA1 : N4," & "MICRO_DATA2 : N1," & "MICRO_DATA3 : N2," & "MEM_ADDR19 : P3," & "TXTRL0 : P4," & "MICRO_DATA4 : P2," & "MICRO_DATA5 : P1," & "MICRO_DATA6 : R1," & "MICRO_DATA7 : R2," & "MICRO_INT : T1," & "MICRO_RDY : T2," & "MICRO_CLK : R3," & "MICRO_SYNCMODE : N5," & "PHY_MUX_SELECT : R4," & "TEST_ENABLE : T3," & "TEST_MODE : T4," & "RESET_N : P5," & "ONESEC_CLK : N6," & "ONESEC_IO : R5," & "MEM_DATA0 : T5," & "MEM_DATA1 : P6," & "MEM_DATA2 : R6," & "MEM_DATA3 : N7," & "MEM_DATA4 : P7," & "PHY_RX_ADDR0 : T6," & "PHY_RX_CLK : R7," & "PHY_RX_ENB0_N : N8," & "PHY_RX_ADDR1 : T7," & "PHY_RX_ADDR2 : P8," & "PHY_RX_ADDR3 : T8," & "PHY_RX_ADDR4 : R8," & "PHY_RX_CLAV0 : N9," & "PHY_RX_DATA0 : P9," & "PHY_RX_DATA1 : T9," & "PHY_RX_DATA2 : R9," & "PHY_RX_DATA3 : P10," & "MEM_DATA5 : N10," & "MEM_DATA6 : T10," & "MEM_DATA7 : R10," & "MEM_DATA8 : P11," & "MEM_DATA9 : N11," & "MEM_DATA10 : T11," & "MEM_DATA11 : R11," & "MEM_DATA12 : P12," & "MEM_DATA13 : N12," & "PHY_RX_DATA4 : T12," & "PHY_RX_DATA5 : R12," & "PHY_RX_DATA6 : P13," & "PHY_RX_DATA7 : N13," & "PHY_TX_ADDR1 : T13," & "PHY_TX_ADDR2 : R13," & "PHY_RX_ENB1_N : P14," & "PHY_RX_SOC : N14," & "PHY_TX_ADDR0 : T14," & "PHY_TX_CLAV0 : R14," & "PHY_TX_CLK : T15," & "PHY_TX_CLAV1 : R15," & "PHY_RX_CLAV1 : T16," & "PHY_TX_DATA0 : R16," & "PHY_TX_DATA1 : P15," & "PHY_TX_DATA2 : M13," & "PHY_TX_DATA3 : N15," & "PHY_TX_DATA4 : P16," & "PHY_TX_DATA5 : N16," & "PHY_TX_DATA6 : M14," & "PHY_TX_DATA7 : L13," & "PHY_TX_ENB0_N : M15," & "IMA_SYSCLK : M16," & "IMA_REFCLK : L14," & "PHY_TX_ADDR3 : L15," & "PHY_TX_ADDR4 : K13," & "BONDOUT1 : NC2," & "TC_RX_CLK2 : K14," & "TC_RX_CLK3 : L16," & "TC_RX_CLK4 : K15," & "TC_RX_CLK5 : J13," & "TC_RX_CLK6 : K16," & "TC_RX_CLK7 : J14," & "TC_RX_DATA3 : J16," & "TC_RX_DATA4 : J15," & "TC_RX_DATA5 : H13," & "TC_RX_DATA6 : H14," & "TC_RX_DATA7 : H16," & "ATM_TX_DATA8 : H15," & "ATM_TX_DATA9 : G14," & "ATM_TX_DATA10 : G13," & "ATM_TX_DATA11 : G16," & "ATM_TX_DATA12 : G15," & "ATM_TX_DATA13 : F14," & "TCK : F13," & "TDI : F16," & "TDO : F15," & "TMS : E14," & "TRST_N : E13," & "PHY_TX_SOC : E16," & "ATM_TX_ADDR0 : E15," & "ATM_TX_ADDR1 : D14," & "ATM_TX_ADDR2 : D13," & "ATM_TX_ADDR3 : D16," & "ATM_TX_ADDR4 : D15," & "PHY_TX_ENB1_N : C14," & "EXTMEMSEL : C13," & "ATM_TX_DATA0 : C16," & "ATM_TX_DATA1 : C15," & "ATM_TX_DATA2 : B16," & "ATM_TX_DATA3 : B15," & "ATM_TX_DATA14 : A16," & "ATM_TX_DATA15 : A15," & "ATM_TX_DATA4 : B14," & "ATM_TX_DATA5 : D12," & "ATM_TX_DATA6 : B13," & "ATM_TX_DATA7 : A14," & "ATM_TX_PRTY : A13," & "ATM_TX_CLAV : C12," & "ATM_TX_SOC : D11," & "ATM_TX_ENB_N : B12," & "ATM_TX_CLK : A12," & "ATM_RX_DATA8 : C11," & "ATM_RX_DATA9 : B11," & "ATM_RX_DATA10 : D10," & "ATM_RX_DATA11 : C10," & "ATM_RX_DATA12 : A11," & "ATM_RX_DATA13 : B10," & "ATM_RX_DATA14 : D9," & "ATM_RX_DATA15 : A10," & "ATM_RX_SOC : C9," & "ATM_RX_CLK : A9," & "ATM_RX_CLAV : B9," & "ATM_RX_ENB_N : D8," & "ATM_RX_DATA0 : C8," & "ATM_RX_DATA1 : A8," & "ATM_RX_DATA2 : B8," & "ATM_RX_DATA3 : C7," & "TC_RX_SYNC3 : D7," & "TC_RX_SYNC4 : A7," & "TC_RX_SYNC5 : B7," & "TC_RX_SYNC6 : C6," & "TC_RX_SYNC7 : D6," & "MEM_DATA14 : A6," & "MEM_DATA15 : B6," & "ATM_RX_DATA4 : C5," & "ATM_RX_DATA5 : D5," & "ATM_RX_DATA6 : A5," & "ATM_RX_DATA7 : B5," & "ATM_RX_PRTY : C4," & "ATM_RX_ADDR0 : D4," & "ATM_RX_ADDR1 : A4," & "ATM_RX_ADDR2 : B4," & "ATM_RX_ADDR3 : C3," & "ATM_RX_ADDR4 : D3," & "TXTRL1 : A3," & "VDDC_G11 : G11," & "VDDC_G12 : G12," & "VDDC_G5 : G5," & "VDDC_G6 : G6," & "VDDC_H11 : H11," & "VDDC_H12 : H12," & "VDDC_H5 : H5," & "VDDC_H6 : H6," & "VDDC_J11 : J11," & "VDDC_J12 : J12," & "VDDC_J5 : J5," & "VDDC_J6 : J6," & "VDDC_K11 : K11," & "VDDC_K12 : K12," & "VDDC_K5 : K5," & "VDDC_K6 : K6," & "VDDIO_E10 : E10," & "VDDIO_E11 : E11," & "VDDIO_E12 : E12," & "VDDIO_E5 : E5," & "VDDIO_E6 : E6," & "VDDIO_E7 : E7," & "VDDIO_E8 : E8," & "VDDIO_E9 : E9," & "VDDIO_F10 : F10," & "VDDIO_F11 : F11," & "VDDIO_F12 : F12," & "VDDIO_F5 : F5," & "VDDIO_F6 : F6," & "VDDIO_F7 : F7," & "VDDIO_F8 : F8," & "VDDIO_F9 : F9," & "VDDIO_L10 : L10," & "VDDIO_L11 : L11," & "VDDIO_L12 : L12," & "VDDIO_L5 : L5," & "VDDIO_L6 : L6," & "VDDIO_L7 : L7," & "VDDIO_L8 : L8," & "VDDIO_L9 : L9," & "VDDIO_M10 : M10," & "VDDIO_M11 : M11," & "VDDIO_M12 : M12," & "VDDIO_M5 : M5," & "VDDIO_M6 : M6," & "VDDIO_M7 : M7," & "VDDIO_M8 : M8," & "VDDIO_M9 : M9," & "VGG_B3 : B3," & "VSS_G10 : G10," & "VSS_G7 : G7," & "VSS_G8 : G8," & "VSS_G9 : G9," & "VSS_H10 : H10," & "VSS_H7 : H7," & "VSS_H8 : H8," & "VSS_H9 : H9," & "VSS_J10 : J10," & "VSS_J7 : J7," & "VSS_J8 : J8," & "VSS_J9 : J9," & "VSS_K10 : K10," & "VSS_K7 : K7," & "VSS_K8 : K8," & "VSS_K9 : K9"; -- TAP Port Name Attributes attribute TAP_SCAN_IN of tdi : signal is true; attribute TAP_SCAN_OUT of tdo : signal is true; attribute TAP_SCAN_MODE of tms : signal is true; attribute TAP_SCAN_CLOCK of tck : signal is (1.0e+07, BOTH); attribute TAP_SCAN_RESET of trst_n : signal is true; -- Instruction Register Attributes attribute INSTRUCTION_LENGTH of CX28229 : entity is 3; attribute INSTRUCTION_OPCODE of CX28229 : entity is "BYPASS (111)," & "SAMPLE (001)," & "EXTEST (000)," & "HIGHZ (100)," & "IDCODE (010)"; attribute INSTRUCTION_CAPTURE of CX28229 : entity is "001"; attribute IDCODE_REGISTER of CX28229 : entity is "0100" & -- Version "1000001000101001" & -- Part Number "00000010011" & -- Manufacturer's ID "1"; attribute REGISTER_ACCESS of CX28229 : entity is "BYPASS (BYPASS, HIGHZ)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Boundary Register Attributes attribute BOUNDARY_LENGTH of CX28229 : entity is 248; attribute BOUNDARY_REGISTER of CX28229 : entity is -- num cell port function safe ccell dsval rslt "0 (BC_1, TXTRL1 , output3, X, 192, 1, Z)," & "1 (BC_1, ATM_RX_ADDR4 , input, X)," & "2 (BC_1, ATM_RX_ADDR3 , input, X)," & "3 (BC_1, ATM_RX_ADDR2 , input, X)," & "4 (BC_1, ATM_RX_ADDR1 , input, X)," & "5 (BC_1, ATM_RX_ADDR0 , input, X)," & "6 (BC_1, * , control, 1)," & "7 (BC_1, ATM_RX_PRTY , output3, X, 6, 1, Z)," & "8 (BC_1, * , control, 1)," & "9 (BC_1, ATM_RX_DATA7 , output3, X, 8, 1, Z)," & "10 (BC_1, * , control, 1)," & "11 (BC_1, ATM_RX_DATA6 , output3, X, 10, 1, Z)," & "12 (BC_1, * , control, 1)," & "13 (BC_1, ATM_RX_DATA5 , output3, X, 12, 1, Z)," & "14 (BC_1, * , control, 1)," & "15 (BC_1, ATM_RX_DATA4 , output3, X, 14, 1, Z)," & "16 (BC_7, MEM_DATA15 , bidir, X, 17, 1, PULL0)," & "17 (BC_1, * , control, 1)," & "18 (BC_7, MEM_DATA14 , bidir, X, 17, 1, PULL0)," & "19 (BC_1, TC_RX_SYNC7 , input, X)," & "20 (BC_1, TC_RX_SYNC6 , input, X)," & "21 (BC_1, TC_RX_SYNC5 , input, X)," & "22 (BC_1, TC_RX_SYNC4 , input, X)," & "23 (BC_1, TC_RX_SYNC3 , input, X)," & "24 (BC_1, * , control, 1)," & "25 (BC_1, ATM_RX_DATA3 , output3, X, 24, 1, Z)," & "26 (BC_1, * , control, 1)," & "27 (BC_1, ATM_RX_DATA2 , output3, X, 26, 1, Z)," & "28 (BC_1, * , control, 1)," & "29 (BC_1, ATM_RX_DATA1 , output3, X, 28, 1, Z)," & "30 (BC_1, * , control, 1)," & "31 (BC_1, ATM_RX_DATA0 , output3, X, 30, 1, Z)," & "32 (BC_1, ATM_RX_ENB_N , input, X)," & "33 (BC_1, * , control, 1)," & "34 (BC_1, ATM_RX_CLAV , output3, X, 33, 1, Z)," & "35 (BC_1, ATM_RX_CLK , input, X)," & "36 (BC_1, * , control, 1)," & "37 (BC_1, ATM_RX_SOC , output3, X, 36, 1, Z)," & "38 (BC_1, * , control, 1)," & "39 (BC_1, ATM_RX_DATA15 , output3, X, 38, 1, Z)," & "40 (BC_1, * , control, 1)," & "41 (BC_1, ATM_RX_DATA14 , output3, X, 40, 1, Z)," & "42 (BC_1, * , control, 1)," & "43 (BC_1, ATM_RX_DATA13 , output3, X, 42, 1, Z)," & "44 (BC_1, * , control, 1)," & "45 (BC_1, ATM_RX_DATA12 , output3, X, 44, 1, Z)," & "46 (BC_1, * , control, 1)," & "47 (BC_1, ATM_RX_DATA11 , output3, X, 46, 1, Z)," & "48 (BC_1, * , control, 1)," & "49 (BC_1, ATM_RX_DATA10 , output3, X, 48, 1, Z)," & "50 (BC_1, * , control, 1)," & "51 (BC_1, ATM_RX_DATA9 , output3, X, 50, 1, Z)," & "52 (BC_1, * , control, 1)," & "53 (BC_1, ATM_RX_DATA8 , output3, X, 52, 1, Z)," & "54 (BC_1, ATM_TX_CLK , input, X)," & "55 (BC_1, ATM_TX_ENB_N , input, X)," & "56 (BC_1, ATM_TX_SOC , input, X)," & "57 (BC_1, * , control, 1)," & "58 (BC_1, ATM_TX_CLAV , output3, X, 57, 1, Z)," & "59 (BC_1, ATM_TX_PRTY , input, X)," & "60 (BC_1, ATM_TX_DATA7 , input, X)," & "61 (BC_1, ATM_TX_DATA6 , input, X)," & "62 (BC_1, ATM_TX_DATA5 , input, X)," & "63 (BC_1, ATM_TX_DATA4 , input, X)," & "64 (BC_1, ATM_TX_DATA15 , input, X)," & "65 (BC_1, ATM_TX_DATA14 , input, X)," & "66 (BC_1, ATM_TX_DATA3 , input, X)," & "67 (BC_1, ATM_TX_DATA2 , input, X)," & "68 (BC_1, ATM_TX_DATA1 , input, X)," & "69 (BC_1, ATM_TX_DATA0 , input, X)," & "70 (BC_1, EXTMEMSEL , input, X)," & "71 (BC_1, * , control, 1)," & "72 (BC_1, PHY_TX_ENB1_N , output3, X, 71, 1, Z)," & "73 (BC_1, ATM_TX_ADDR4 , input, X)," & "74 (BC_1, ATM_TX_ADDR3 , input, X)," & "75 (BC_1, ATM_TX_ADDR2 , input, X)," & "76 (BC_1, ATM_TX_ADDR1 , input, X)," & "77 (BC_1, ATM_TX_ADDR0 , input, X)," & "78 (BC_1, * , control, 1)," & "79 (BC_7, PHY_TX_SOC , bidir, X, 78, 1, Z)," & "80 (BC_1, ATM_TX_DATA13 , input, X)," & "81 (BC_1, ATM_TX_DATA12 , input, X)," & "82 (BC_1, ATM_TX_DATA11 , input, X)," & "83 (BC_1, ATM_TX_DATA10 , input, X)," & "84 (BC_1, ATM_TX_DATA9 , input, X)," & "85 (BC_1, ATM_TX_DATA8 , input, X)," & "86 (BC_1, TC_RX_DATA7 , input, X)," & "87 (BC_1, TC_RX_DATA6 , input, X)," & "88 (BC_1, TC_RX_DATA5 , input, X)," & "89 (BC_1, TC_RX_DATA4 , input, X)," & "90 (BC_1, TC_RX_DATA3 , input, X)," & "91 (BC_1, TC_RX_CLK7 , input, X)," & "92 (BC_1, TC_RX_CLK6 , input, X)," & "93 (BC_1, TC_RX_CLK5 , input, X)," & "94 (BC_1, TC_RX_CLK4 , input, X)," & "95 (BC_1, TC_RX_CLK3 , input, X)," & "96 (BC_1, TC_RX_CLK2 , input, X)," & "97 (BC_1, * , control, 1)," & "98 (BC_1, PHY_TX_ADDR4 , output3, X, 97, 1, Z)," & "99 (BC_1, * , control, 1)," & "100 (BC_1, PHY_TX_ADDR3 , output3, X, 99, 1, Z)," & "101 (BC_1, IMA_REFCLK , input, X)," & "102 (BC_1, IMA_SYSCLK , input, X)," & "103 (BC_1, * , control, 1)," & "104 (BC_1, PHY_TX_ENB0_N , output3, X, 103, 1, Z)," & "105 (BC_1, * , control, 1)," & "106 (BC_7, PHY_TX_DATA7 , bidir, X, 105, 1, Z)," & "107 (BC_1, * , control, 1)," & "108 (BC_7, PHY_TX_DATA6 , bidir, X, 107, 1, Z)," & "109 (BC_1, * , control, 1)," & "110 (BC_7, PHY_TX_DATA5 , bidir, X, 109, 1, Z)," & "111 (BC_1, * , control, 1)," & "112 (BC_7, PHY_TX_DATA4 , bidir, X, 111, 1, Z)," & "113 (BC_1, * , control, 1)," & "114 (BC_7, PHY_TX_DATA3 , bidir, X, 113, 1, Z)," & "115 (BC_1, * , control, 1)," & "116 (BC_7, PHY_TX_DATA2 , bidir, X, 115, 1, Z)," & "117 (BC_1, * , control, 1)," & "118 (BC_7, PHY_TX_DATA1 , bidir, X, 117, 1, Z)," & "119 (BC_1, * , control, 1)," & "120 (BC_7, PHY_TX_DATA0 , bidir, X, 119, 1, Z)," & "121 (BC_1, PHY_RX_CLAV1 , input, X)," & "122 (BC_1, PHY_TX_CLAV1 , input, X)," & "123 (BC_1, * , control, 1)," & "124 (BC_7, PHY_TX_CLK , bidir, X, 123, 1, Z)," & "125 (BC_1, PHY_TX_CLAV0 , input, X)," & "126 (BC_1, * , control, 1)," & "127 (BC_1, PHY_TX_ADDR0 , output3, X, 126, 1, Z)," & "128 (BC_1, PHY_RX_SOC , input, X)," & "129 (BC_1, * , control, 1)," & "130 (BC_1, PHY_RX_ENB1_N , output3, X, 129, 1, Z)," & "131 (BC_1, * , control, 1)," & "132 (BC_1, PHY_TX_ADDR2 , output3, X, 131, 1, Z)," & "133 (BC_1, * , control, 1)," & "134 (BC_1, PHY_TX_ADDR1 , output3, X, 133, 1, Z)," & "135 (BC_1, PHY_RX_DATA7 , input, X)," & "136 (BC_1, PHY_RX_DATA6 , input, X)," & "137 (BC_1, PHY_RX_DATA5 , input, X)," & "138 (BC_1, PHY_RX_DATA4 , input, X)," & "139 (BC_7, MEM_DATA13 , bidir, X, 144, 1, PULL0)," & "140 (BC_7, MEM_DATA12 , bidir, X, 144, 1, PULL0)," & "141 (BC_7, MEM_DATA11 , bidir, X, 144, 1, PULL0)," & "142 (BC_7, MEM_DATA10 , bidir, X, 144, 1, PULL0)," & "143 (BC_7, MEM_DATA9 , bidir, X, 144, 1, PULL0)," & "144 (BC_1, * , control, 1)," & "145 (BC_7, MEM_DATA8 , bidir, X, 144, 1, PULL0)," & "146 (BC_7, MEM_DATA7 , bidir, X, 172, 1, PULL0)," & "147 (BC_7, MEM_DATA6 , bidir, X, 172, 1, PULL0)," & "148 (BC_7, MEM_DATA5 , bidir, X, 172, 1, PULL0)," & "149 (BC_1, PHY_RX_DATA3 , input, X)," & "150 (BC_1, PHY_RX_DATA2 , input, X)," & "151 (BC_1, PHY_RX_DATA1 , input, X)," & "152 (BC_1, PHY_RX_DATA0 , input, X)," & "153 (BC_1, PHY_RX_CLAV0 , input, X)," & "154 (BC_1, * , control, 1)," & "155 (BC_1, PHY_RX_ADDR4 , output3, X, 154, 1, Z)," & "156 (BC_1, * , control, 1)," & "157 (BC_1, PHY_RX_ADDR3 , output3, X, 156, 1, Z)," & "158 (BC_1, * , control, 1)," & "159 (BC_1, PHY_RX_ADDR2 , output3, X, 158, 1, Z)," & "160 (BC_1, * , control, 1)," & "161 (BC_1, PHY_RX_ADDR1 , output3, X, 160, 1, Z)," & "162 (BC_1, * , control, 1)," & "163 (BC_1, PHY_RX_ENB0_N , output3, X, 162, 1, Z)," & "164 (BC_1, * , control, 1)," & "165 (BC_7, PHY_RX_CLK , bidir, X, 164, 1, Z)," & "166 (BC_1, * , control, 1)," & "167 (BC_1, PHY_RX_ADDR0 , output3, X, 166, 1, Z)," & "168 (BC_7, MEM_DATA4 , bidir, X, 172, 1, PULL0)," & "169 (BC_7, MEM_DATA3 , bidir, X, 172, 1, PULL0)," & "170 (BC_7, MEM_DATA2 , bidir, X, 172, 1, PULL0)," & "171 (BC_7, MEM_DATA1 , bidir, X, 172, 1, PULL0)," & "172 (BC_1, * , control, 1)," & "173 (BC_7, MEM_DATA0 , bidir, X, 172, 1, PULL0)," & "174 (BC_1, * , control, 1)," & "175 (BC_7, ONESEC_IO , bidir, X, 174, 1, Z)," & "176 (BC_1, ONESEC_CLK , input, X)," & "177 (BC_1, RESET_N , input, X)," & "178 (BC_1, TEST_MODE , input, X)," & "179 (BC_1, TEST_ENABLE , input, X)," & "180 (BC_1, PHY_MUX_SELECT , input, X)," & "181 (BC_1, MICRO_SYNCMODE , input, X)," & "182 (BC_1, MICRO_CLK , input, X)," & "183 (BC_1, * , control, 1)," & "184 (BC_1, MICRO_RDY , output3, X, 183, 1, Z)," & "185 (BC_1, * , control, 1)," & "186 (BC_1, MICRO_INT , output3, X, 185, 1, Z)," & "187 (BC_7, MICRO_DATA7 , bidir, X, 190, 1, Z)," & "188 (BC_7, MICRO_DATA6 , bidir, X, 190, 1, Z)," & "189 (BC_7, MICRO_DATA5 , bidir, X, 190, 1, Z)," & "190 (BC_1, * , control, 1)," & "191 (BC_7, MICRO_DATA4 , bidir, X, 190, 1, Z)," & "192 (BC_1, * , control, 1)," & "193 (BC_1, TXTRL0 , output3, X, 192, 1, Z)," & "194 (BC_1, MEM_ADDR19 , output3, X, 222, 1, Z)," & "195 (BC_7, MICRO_DATA3 , bidir, X, 198, 1, Z)," & "196 (BC_7, MICRO_DATA2 , bidir, X, 198, 1, Z)," & "197 (BC_7, MICRO_DATA1 , bidir, X, 198, 1, Z)," & "198 (BC_1, * , control, 1)," & "199 (BC_7, MICRO_DATA0 , bidir, X, 198, 1, Z)," & "200 (BC_1, STATOUT1 , output3, X, 201, 1, Z)," & "201 (BC_1, * , control, 1)," & "202 (BC_1, STATOUT0 , output3, X, 201, 1, Z)," & "203 (BC_1, MICRO_ADDR10 , input, X)," & "204 (BC_1, * , control, 1)," & "205 (BC_1, MEM_ADSC , output3, X, 204, 1, Z)," & "206 (BC_1, * , control, 1)," & "207 (BC_1, MEM_CLK , output3, X, 206, 1, Z)," & "208 (BC_1, * , control, 1)," & "209 (BC_1, MEM_WE , output3, X, 208, 1, Z)," & "210 (BC_1, * , control, 1)," & "211 (BC_1, MEM_OE , output3, X, 210, 1, Z)," & "212 (BC_1, * , control, 1)," & "213 (BC_1, MEM_CE , output3, X, 212, 1, Z)," & "214 (BC_1, MEM_ADDR18 , output3, X, 222, 1, Z)," & "215 (BC_1, MEM_ADDR17 , output3, X, 222, 1, Z)," & "216 (BC_1, MEM_ADDR16 , output3, X, 222, 1, Z)," & "217 (BC_1, MEM_ADDR15 , output3, X, 222, 1, Z)," & "218 (BC_1, MEM_ADDR14 , output3, X, 222, 1, Z)," & "219 (BC_1, MEM_ADDR13 , output3, X, 222, 1, Z)," & "220 (BC_1, MEM_ADDR12 , output3, X, 222, 1, Z)," & "221 (BC_1, MEM_ADDR11 , output3, X, 222, 1, Z)," & "222 (BC_1, * , control, 1)," & "223 (BC_1, MEM_ADDR10 , output3, X, 222, 1, Z)," & "224 (BC_1, MEM_ADDR9 , output3, X, 233, 1, Z)," & "225 (BC_1, MEM_ADDR8 , output3, X, 233, 1, Z)," & "226 (BC_1, MEM_ADDR7 , output3, X, 233, 1, Z)," & "227 (BC_1, MEM_ADDR6 , output3, X, 233, 1, Z)," & "228 (BC_1, MEM_ADDR5 , output3, X, 233, 1, Z)," & "229 (BC_1, MEM_ADDR4 , output3, X, 233, 1, Z)," & "230 (BC_1, MEM_ADDR3 , output3, X, 233, 1, Z)," & "231 (BC_1, MEM_ADDR2 , output3, X, 233, 1, Z)," & "232 (BC_1, MEM_ADDR1 , output3, X, 233, 1, Z)," & "233 (BC_1, * , control, 1)," & "234 (BC_1, MEM_ADDR0 , output3, X, 233, 1, Z)," & "235 (BC_1, MICRO_ADDR9 , input, X)," & "236 (BC_1, MICRO_ADDR8 , input, X)," & "237 (BC_1, MICRO_ADDR7 , input, X)," & "238 (BC_1, MICRO_ADDR6 , input, X)," & "239 (BC_1, MICRO_ADDR5 , input, X)," & "240 (BC_1, MICRO_ADDR4 , input, X)," & "241 (BC_1, MICRO_ADDR3 , input, X)," & "242 (BC_1, MICRO_ADDR2 , input, X)," & "243 (BC_1, MICRO_ADDR1 , input, X)," & "244 (BC_1, MICRO_ADDR0 , input, X)," & "245 (BC_1, MICRO_AS , input, X)," & "246 (BC_1, MICRO_CS , input, X)," & "247 (BC_1, MICRO_W_N , input, X)"; end CX28229;