-------------------------------------------------------------------------------- -- Freescale Boundary Scan Description Language -- -------------------------------------------------------------------------------- -- Boundary Scan Description Language (IEEE 1149.1b) -- -- -- -- Device : MPC8309 Revision 1.0 -- -- File Version : A -- -- File Name : MPC8309.R1A -- -- File created : FEB 01, 2010 -- -- Package type : MAPBGA -- -- Voltage Level : 1V -- -------------------------------------------------------------------------------- -- Revision History: -- -- A - Original version -- -- -- -- NOTE: The IEEE 1149.1 standard optional instructions HIGHZ, -- -- IDCODE, and CLAMP are supported. -- -- -- -- NOTE: SYS_CR_CLK_OUT pin is non-complaint with IEEE 1149.1 Standard -- -- NOTE: USB_CR_CLK_OUT pin is non-complaint with IEEE 1149.1 Standard -- -- -- -- NOTE: For assistance with this file, contact your sales office. -- -- -- -- -- -------------------------------------------------------------------------------- -- -- -------------------------------------------------------------------------------- -- -- --============================================================================-- -- IMPORTANT NOTICE -- -- This information is provided on an AS IS basis and without warranty. -- -- IN NO EVENT SHALL FREESCALE BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL -- -- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF -- -- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR CUSTOMERS -- -- OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES WHETHER EXPRESS, -- -- IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY -- -- OR FITNESS FOR PARTICULAR PURPOSE. -- -- -- -- FREESCALE does not represent or warrant that the information furnished -- -- hereunder is free of infringement of any third party patents, -- -- copyrights, trade secrets, or other intellectual property rights. -- -- -- -- FREESCALE does not represent or warrant that the information is free of -- -- defect, or that it meets any particular standard, requirements or need -- -- of the user of the infomation or their customers. -- -- -- -- FREESCALE reserves the right to change the information in this file -- -- without notice. The BSDL files are also available at: -- -- -- -- http://www.freescale.com -- -- -- --============================================================================-- entity MPC8309 is generic (PHYSICAL_PIN_MAP : string := "PBGA"); -- PORT DESCRIPTION TERMS -- in = input only -- out = three-state output (0, Z, 1) -- buffer = two-state output (0, 1) -- inout = bidirectional -- linkage = OTHER (vdd, vss, analog) -- -- bit = single pin -- bit_vector = group of pins with suffix 0 to n port ( CFG_CLKIN_DIV_B: in bit; FEC1_COL_FEC1_COL: inout bit; FEC1_CRS_FEC1_CRS: inout bit; FEC1_RXD3_FEC1_RXD3: inout bit; FEC1_RXD2_FEC1_RXD2: inout bit; FEC1_RXD1_FEC1_RXD1: inout bit; FEC1_RXD0_FEC1_RXD0: inout bit; FEC1_RX_CLK_FEC1_RX_CLK: inout bit; FEC1_RX_DV_FEC1_RX_DV: inout bit; FEC1_RX_ER_FEC1_RX_ER: inout bit; FEC1_TXD3_FEC1_TXD3: inout bit; FEC1_TXD2_FEC1_TXD2: inout bit; FEC1_TXD1_FEC1_TXD1: inout bit; FEC1_TXD0_FEC1_TXD0: inout bit; FEC1_TX_CLK_FEC1_TX_CLK: inout bit; FEC1_TX_EN_FEC1_TX_EN: inout bit; FEC1_TX_ER_FEC1_TX_ER: inout bit; FEC2_COL_FEC2_COL: inout bit; FEC2_CRS_FEC2_CRS: inout bit; FEC2_RXD3_FEC2_RXD3: inout bit; FEC2_RXD2_FEC2_RXD2: inout bit; FEC2_RXD1_FEC2_RXD1: inout bit; FEC2_RXD0_FEC2_RXD0: inout bit; FEC2_RX_CLK_FEC2_RX_CLK: inout bit; FEC2_RX_DV_FEC2_RX_DV: inout bit; FEC2_RX_ER_FEC2_RX_ER: inout bit; FEC2_TXD3_FEC2_TXD3: inout bit; FEC2_TXD2_FEC2_TXD2: inout bit; FEC2_TXD1_FEC2_TXD1: inout bit; FEC2_TXD0_FEC2_TXD0: inout bit; FEC2_TX_CLK_FEC2_TX_CLK: inout bit; FEC2_TX_EN_FEC2_TX_EN: inout bit; FEC2_TX_ER_FEC2_TX_ER: inout bit; FEC3_COL_USBDR_TXDRXD0: inout bit; FEC3_CRS: inout bit; FEC3_RXD3_USBDR_TXDRXD4: inout bit; FEC3_RXD2: inout bit; FEC3_RXD1_USBDR_TXDRXD3: inout bit; FEC3_RXD0: inout bit; FEC3_RX_CLK_USBDR_TXDRXD1: inout bit; FEC3_RX_DV: inout bit; FEC3_RX_ER_USBDR_TXDRXD2: inout bit; FEC3_TXD3: inout bit; FEC3_TXD2_USBDR_TXDRXD7: inout bit; FEC3_TXD1: inout bit; FEC3_TXD0_USBDR_TXDRXD6: inout bit; FEC3_TX_CLK: inout bit; FEC3_TX_EN_USBDR_TXDRXD5: inout bit; FEC3_TX_ER: inout bit; FEC_MDC: inout bit; FEC_MDIO: inout bit; GPIO_0_GPIO_0: inout bit; GPIO_10_LWE_B1: inout bit; GPIO_11: inout bit; GPIO_12_LBCTL: inout bit; GPIO_13: inout bit; GPIO_14_LALE: inout bit; GPIO_15: inout bit; GPIO_1_GPIO_1: inout bit; GPIO_2_GPIO_2: inout bit; GPIO_3_GPIO_3: inout bit; GPIO_4_GPIO_4: inout bit; GPIO_5_GPIO_5: inout bit; GPIO_6_GPIO_6: inout bit; GPIO_7_GPIO_7: inout bit; GPIO_8_LWE_B0: inout bit; GPIO_9: inout bit; HDLC1_CD_B_HDLC1_CD_B: inout bit; HDLC1_CTS_B_HDLC1_CTS_B: inout bit; HDLC1_RTS_B_HDLC1_RTS_B: inout bit; HDLC1_RXCLK: inout bit; HDLC1_RXD: inout bit; HDLC1_TXCLK_HDLC1_TXCLK: inout bit; HDLC1_TXD_HDLC1_TXD: inout bit; HDLC2_CD_B_HDLC2_CD_B: inout bit; HDLC2_CTS_B_HDLC2_CTS_B: inout bit; HDLC2_RTS_B_HDLC2_RTS_B: inout bit; HDLC2_RXCLK_HDLC2_RXCLK: inout bit; HDLC2_RXD_HDLC2_RXD: inout bit; HDLC2_TXCLK_HDLC2_TXCLK: inout bit; HDLC2_TXD_HDLC2_TXD: inout bit; HRESET_B: inout bit; IIC_SCL1: inout bit; IIC_SCL2: inout bit; IIC_SDA1_LGPL2: inout bit; IIC_SDA2_LGPL3: inout bit; IRQ_B0_MCP_IN_B_LGPL4: inout bit; IRQ_B1: inout bit; IRQ_B2_LGPL5: inout bit; IRQ_B3: inout bit; LA16_LA16: inout bit; LA17_LA17: inout bit; LA18_LA18: inout bit; LA19_LA19: inout bit; LA20_LA20: inout bit; LA21_LA21: inout bit; LA22_LA22: inout bit; LA23_LA23: inout bit; LA24_LA24: inout bit; LA25_LA25: inout bit; LAD0_LAD0: inout bit; LAD10_LAD10: inout bit; LAD11_LAD11: inout bit; LAD12_LAD12: inout bit; LAD13_LAD13: inout bit; LAD14_LAD14: inout bit; LAD15_LAD15: inout bit; LAD1_LAD1: inout bit; LAD2_LAD2: inout bit; LAD3_LAD3: inout bit; LAD4_LAD4: inout bit; LAD5_LAD5: inout bit; LAD6_LAD6: inout bit; LAD7_LAD7: inout bit; LAD8_LAD8: inout bit; LAD9_LAD9: inout bit; LALE: inout bit; LBCTL: inout bit; LCLK0_LCLK0: inout bit; LCS_B0_LCS_B0: inout bit; LCS_B1_LCS_B1: inout bit; LCS_B2_LCS_B2: inout bit; LCS_B3_LCS_B3: inout bit; LGPL0: inout bit; LGPL1: inout bit; LGPL2: inout bit; LGPL3: inout bit; LGPL4: inout bit; LGPL5: inout bit; LWE_B0: inout bit; LWE_B1: inout bit; M66EN_HDLC1_RXD: inout bit; MEMC_MA0: inout bit; MEMC_MA1: inout bit; MEMC_MA10: inout bit; MEMC_MA11: inout bit; MEMC_MA12: inout bit; MEMC_MA13: inout bit; MEMC_MA2: inout bit; MEMC_MA3: inout bit; MEMC_MA4: inout bit; MEMC_MA5: inout bit; MEMC_MA6: inout bit; MEMC_MA7: inout bit; MEMC_MA8: inout bit; MEMC_MA9: inout bit; MEMC_MBA0: inout bit; MEMC_MBA1: inout bit; MEMC_MBA2: inout bit; MEMC_MCAS_B: inout bit; MEMC_MCK0: inout bit; MEMC_MCK1: inout bit; MEMC_MCKE: inout bit; MEMC_MCK_B0: inout bit; MEMC_MCK_B1: inout bit; MEMC_MCS_B0: inout bit; MEMC_MCS_B1: inout bit; MEMC_MDM0: inout bit; MEMC_MDM1: inout bit; MEMC_MDM2: inout bit; MEMC_MDM3: inout bit; MEMC_MDM8: inout bit; MEMC_MDQ0: inout bit; MEMC_MDQ1: inout bit; MEMC_MDQ10: inout bit; MEMC_MDQ11: inout bit; MEMC_MDQ12: inout bit; MEMC_MDQ13: inout bit; MEMC_MDQ14: inout bit; MEMC_MDQ15: inout bit; MEMC_MDQ16: inout bit; MEMC_MDQ17: inout bit; MEMC_MDQ18: inout bit; MEMC_MDQ19: inout bit; MEMC_MDQ2: inout bit; MEMC_MDQ20: inout bit; MEMC_MDQ21: inout bit; MEMC_MDQ22: inout bit; MEMC_MDQ23: inout bit; MEMC_MDQ24: inout bit; MEMC_MDQ25: inout bit; MEMC_MDQ26: inout bit; MEMC_MDQ27: inout bit; MEMC_MDQ28: inout bit; MEMC_MDQ29: inout bit; MEMC_MDQ3: inout bit; MEMC_MDQ30: inout bit; MEMC_MDQ31: inout bit; MEMC_MDQ4: inout bit; MEMC_MDQ5: inout bit; MEMC_MDQ6: inout bit; MEMC_MDQ7: inout bit; MEMC_MDQ8: inout bit; MEMC_MDQ9: inout bit; MEMC_MDQS0: inout bit; MEMC_MDQS1: inout bit; MEMC_MDQS2: inout bit; MEMC_MDQS3: inout bit; MEMC_MDQS8: inout bit; MEMC_MECC0: inout bit; MEMC_MECC1: inout bit; MEMC_MECC2: inout bit; MEMC_MECC3: inout bit; MEMC_MECC4: inout bit; MEMC_MECC5: inout bit; MEMC_MECC6: inout bit; MEMC_MECC7: inout bit; MEMC_MODT0: inout bit; MEMC_MODT1: inout bit; MEMC_MRAS_B: inout bit; MEMC_MWE_B: inout bit; PCI_AD0_UART1_SIN1: inout bit; PCI_AD1: inout bit; PCI_AD10_IRQ_B2: inout bit; PCI_AD11: inout bit; PCI_AD12_IRQ_B3: inout bit; PCI_AD13: inout bit; PCI_AD14_IIC_SDA1: inout bit; PCI_AD15: inout bit; PCI_AD16_IIC_SCL1: inout bit; PCI_AD17: inout bit; PCI_AD18_SPISEL_BOOT: inout bit; PCI_AD19: inout bit; PCI_AD20_LCLK1: inout bit; PCI_AD21: inout bit; PCI_AD22_SPIMOSI: inout bit; PCI_AD23: inout bit; PCI_AD24_SPIMISO: inout bit; PCI_AD25: inout bit; PCI_AD26_SPICLK: inout bit; PCI_AD27: inout bit; PCI_AD28_SPISEL: inout bit; PCI_AD29: inout bit; PCI_AD2_UART1_SOUT2: inout bit; PCI_AD3: inout bit; PCI_AD30_FEC_MDC: inout bit; PCI_AD31: inout bit; PCI_AD4_UART1_SIN2: inout bit; PCI_AD5: inout bit; PCI_AD6_IRQ_B0_MCP_IN_B: inout bit; PCI_AD7: inout bit; PCI_AD8_IRQ_B1: inout bit; PCI_AD9: inout bit; PCI_CLK0: inout bit; PCI_CLK1: inout bit; PCI_CLK2: inout bit; PCI_C_BE_B0_FEC_MDIO: inout bit; PCI_C_BE_B1: inout bit; PCI_C_BE_B2_FEC3_COL: inout bit; PCI_C_BE_B3_FEC3_CRS: inout bit; PCI_DEVSEL_B_FEC3_RXD2: inout bit; PCI_FRAME_B_FEC3_RX_DV: inout bit; PCI_GNT_B0_FEC3_TXD2: inout bit; PCI_GNT_B1_FEC3_TXD3: inout bit; PCI_GNT_B2_HDLC1_RXCLK: inout bit; PCI_IDSEL_FEC3_RXD3: inout bit; PCI_INTA_B_UART1_SOUT1: inout bit; PCI_IRDY_B_FEC3_RXD0: inout bit; PCI_PAR_FEC3_RX_CLK: inout bit; PCI_PERR_B_FEC3_TX_EN: inout bit; PCI_REQ_B0_FEC3_TX_ER: inout bit; PCI_REQ_B1_FEC3_TXD0: inout bit; PCI_REQ_B2_FEC3_TXD1: inout bit; PCI_RESET_OUT_B: inout bit; PCI_SERR_B_FEC3_TX_CLK: inout bit; PCI_STOP_B_FEC3_RXD1: inout bit; PCI_SYNC_IN: in bit; PCI_SYNC_OUT: inout bit; PCI_TRDY_B_FEC3_RX_ER: inout bit; PORESET_B: in bit; QE_CLK_IN: in bit; QUIESCE_B: inout bit; RTC_PIT_CLOCK: in bit; SPICLK_LGPL1: inout bit; SPIMISO: inout bit; SPIMOSI_LGPL0: inout bit; SPISEL: inout bit; SPISEL_BOOT: inout bit; SYS_CLK_IN: in bit; SYS_XTAL_IN: in bit; TCK: in bit; TDI: in bit; TDO: out bit; TEST_MODE: in bit; TMS: in bit; TRST_B: in bit; UART1_SIN1: inout bit; UART1_SIN2: inout bit; UART1_SOUT1: inout bit; UART1_SOUT2: inout bit; USBDR_CLK_USBDR_CLK: inout bit; USBDR_DIR_USBDR_DIR: inout bit; USBDR_NXT_USBDR_NXT: inout bit; USBDR_PCTL0_USBDR_PCTL0: inout bit; USBDR_PCTL1_USBDR_PCTL1: inout bit; USBDR_PWRFAULT_USBDR_PWRFAULT: inout bit; USBDR_STP_USBDR_STP: inout bit; USBDR_TXDRXD0: inout bit; USBDR_TXDRXD1: inout bit; USBDR_TXDRXD2: inout bit; USBDR_TXDRXD3: inout bit; USBDR_TXDRXD4: inout bit; USBDR_TXDRXD5: inout bit; USBDR_TXDRXD6: inout bit; USBDR_TXDRXD7: inout bit; AVDD1: linkage bit; AVDD2: linkage bit; AVDD3: linkage bit; GVDD: linkage bit_vector(0 to 12); MEMC_MVREF: linkage bit; NVDD: linkage bit_vector(0 to 32); SYS_XTAL_OUT: linkage bit; THERM0: linkage bit; VDD: linkage bit_vector(0 to 28); VSS: linkage bit_vector(0 to 102)); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of MPC8309: entity is "STD_1149_1_2001"; attribute PIN_MAP of MPC8309: entity is PHYSICAL_PIN_MAP; constant PBGA :PIN_MAP_STRING := "CFG_CLKIN_DIV_B: U23," & "FEC1_COL_FEC1_COL: Y18," & "FEC1_CRS_FEC1_CRS: AA19," & "FEC1_RXD3_FEC1_RXD3: AC21," & "FEC1_RXD2_FEC1_RXD2: AB19," & "FEC1_RXD1_FEC1_RXD1: Y17," & "FEC1_RXD0_FEC1_RXD0: AB20," & "FEC1_RX_CLK_FEC1_RX_CLK: W16," & "FEC1_RX_DV_FEC1_RX_DV: AC22," & "FEC1_RX_ER_FEC1_RX_ER: AA18," & "FEC1_TXD3_FEC1_TXD3: AB17," & "FEC1_TXD2_FEC1_TXD2: AA16," & "FEC1_TXD1_FEC1_TXD1: AC18," & "FEC1_TXD0_FEC1_TXD0: AA17," & "FEC1_TX_CLK_FEC1_TX_CLK: W15," & "FEC1_TX_EN_FEC1_TX_EN: AC19," & "FEC1_TX_ER_FEC1_TX_ER: AC20," & "FEC2_COL_FEC2_COL: Y15," & "FEC2_CRS_FEC2_CRS: AC17," & "FEC2_RXD3_FEC2_RXD3: AA14," & "FEC2_RXD2_FEC2_RXD2: AC16," & "FEC2_RXD1_FEC2_RXD1: AC15," & "FEC2_RXD0_FEC2_RXD0: AA15," & "FEC2_RX_CLK_FEC2_RX_CLK: W14," & "FEC2_RX_DV_FEC2_RX_DV: AB16," & "FEC2_RX_ER_FEC2_RX_ER: Y14," & "FEC2_TXD3_FEC2_TXD3: AC13," & "FEC2_TXD2_FEC2_TXD2: AB13," & "FEC2_TXD1_FEC2_TXD1: AA13," & "FEC2_TXD0_FEC2_TXD0: Y12," & "FEC2_TX_CLK_FEC2_TX_CLK: W13," & "FEC2_TX_EN_FEC2_TX_EN: AB14," & "FEC2_TX_ER_FEC2_TX_ER: AC14," & "FEC3_COL_USBDR_TXDRXD0: AC12," & "FEC3_CRS: W11," & "FEC3_RXD3_USBDR_TXDRXD4: AB10," & "FEC3_RXD2: Y11," & "FEC3_RXD1_USBDR_TXDRXD3: AC11," & "FEC3_RXD0: AA11," & "FEC3_RX_CLK_USBDR_TXDRXD1: W12," & "FEC3_RX_DV: AA12," & "FEC3_RX_ER_USBDR_TXDRXD2: AB11," & "FEC3_TXD3: AC7," & "FEC3_TXD2_USBDR_TXDRXD7: AA8," & "FEC3_TXD1: AA9," & "FEC3_TXD0_USBDR_TXDRXD6: AB8," & "FEC3_TX_CLK: AC10," & "FEC3_TX_EN_USBDR_TXDRXD5: AA10," & "FEC3_TX_ER: AC8," & "FEC_MDC: W18," & "FEC_MDIO: W17," & "GPIO_0_GPIO_0: E4," & "GPIO_10_LWE_B1: E15," & "GPIO_11: A18," & "GPIO_12_LBCTL: D15," & "GPIO_13: C18," & "GPIO_14_LALE: D16," & "GPIO_15: C19," & "GPIO_1_GPIO_1: E6," & "GPIO_2_GPIO_2: D3," & "GPIO_3_GPIO_3: E7," & "GPIO_4_GPIO_4: D4," & "GPIO_5_GPIO_5: C4," & "GPIO_6_GPIO_6: B2," & "GPIO_7_GPIO_7: B3," & "GPIO_8_LWE_B0: C16," & "GPIO_9: C17," & "HDLC1_CD_B_HDLC1_CD_B: W19," & "HDLC1_CTS_B_HDLC1_CTS_B: V19," & "HDLC1_RTS_B_HDLC1_RTS_B: AA23," & "HDLC1_RXCLK: AA21," & "HDLC1_RXD: AB23," & "HDLC1_TXCLK_HDLC1_TXCLK: AA20," & "HDLC1_TXD_HDLC1_TXD: AB22," & "HDLC2_CD_B_HDLC2_CD_B: V20," & "HDLC2_CTS_B_HDLC2_CTS_B: Y23," & "HDLC2_RTS_B_HDLC2_RTS_B: U20," & "HDLC2_RXCLK_HDLC2_RXCLK: Y22," & "HDLC2_RXD_HDLC2_RXD: W21," & "HDLC2_TXCLK_HDLC2_TXCLK: Y20," & "HDLC2_TXD_HDLC2_TXD: W20," & "HRESET_B: W23," & "IIC_SCL1: B20," & "IIC_SCL2: C20," & "IIC_SDA1_LGPL2: A20," & "IIC_SDA2_LGPL3: D19," & "IRQ_B0_MCP_IN_B_LGPL4: A21," & "IRQ_B1: A22," & "IRQ_B2_LGPL5: E18," & "IRQ_B3: E19," & "LA16_LA16: C11," & "LA17_LA17: B10," & "LA18_LA18: D12," & "LA19_LA19: A9," & "LA20_LA20: E12," & "LA21_LA21: B11," & "LA22_LA22: A11," & "LA23_LA23: A10," & "LA24_LA24: C12," & "LA25_LA25: A12," & "LAD0_LAD0: B5," & "LAD10_LAD10: B7," & "LAD11_LAD11: C9," & "LAD12_LAD12: E11," & "LAD13_LAD13: B8," & "LAD14_LAD14: A8," & "LAD15_LAD15: C10," & "LAD1_LAD1: A4," & "LAD2_LAD2: C7," & "LAD3_LAD3: D9," & "LAD4_LAD4: A5," & "LAD5_LAD5: E10," & "LAD6_LAD6: A6," & "LAD7_LAD7: C8," & "LAD8_LAD8: D10," & "LAD9_LAD9: A7," & "LALE: A17," & "LBCTL: A15," & "LCLK0_LCLK0: E13," & "LCS_B0_LCS_B0: D13," & "LCS_B1_LCS_B1: C13," & "LCS_B2_LCS_B2: A13," & "LCS_B3_LCS_B3: B13," & "LGPL0: C14," & "LGPL1: C15," & "LGPL2: B16," & "LGPL3: A16," & "LGPL4: E14," & "LGPL5: B17," & "LWE_B0: A14," & "LWE_B1: B14," & "M66EN_HDLC1_RXD: V21," & "MEMC_MA0: L3," & "MEMC_MA1: L5," & "MEMC_MA10: L4," & "MEMC_MA11: P2," & "MEMC_MA12: N4," & "MEMC_MA13: P1," & "MEMC_MA2: L2," & "MEMC_MA3: L1," & "MEMC_MA4: M3," & "MEMC_MA5: M4," & "MEMC_MA6: M1," & "MEMC_MA7: N1," & "MEMC_MA8: N2," & "MEMC_MA9: N3," & "MEMC_MBA0: K2," & "MEMC_MBA1: K3," & "MEMC_MBA2: N5," & "MEMC_MCAS_B: J3," & "MEMC_MCK0: R1," & "MEMC_MCK1: R3," & "MEMC_MCKE: P4," & "MEMC_MCK_B0: T1," & "MEMC_MCK_B1: P3," & "MEMC_MCS_B0: J4," & "MEMC_MCS_B1: K5," & "MEMC_MDM0: W1," & "MEMC_MDM1: E1," & "MEMC_MDM2: V3," & "MEMC_MDM3: D1," & "MEMC_MDM8: W5," & "MEMC_MDQ0: U5," & "MEMC_MDQ1: AA1," & "MEMC_MDQ10: G3," & "MEMC_MDQ11: F3," & "MEMC_MDQ12: G5," & "MEMC_MDQ13: F4," & "MEMC_MDQ14: F5," & "MEMC_MDQ15: E3," & "MEMC_MDQ16: V4," & "MEMC_MDQ17: Y2," & "MEMC_MDQ18: Y1," & "MEMC_MDQ19: U4," & "MEMC_MDQ2: W3," & "MEMC_MDQ20: V1," & "MEMC_MDQ21: R4," & "MEMC_MDQ22: U1," & "MEMC_MDQ23: T2," & "MEMC_MDQ24: J5," & "MEMC_MDQ25: G2," & "MEMC_MDQ26: G1," & "MEMC_MDQ27: F1," & "MEMC_MDQ28: E2," & "MEMC_MDQ29: D2," & "MEMC_MDQ3: R5," & "MEMC_MDQ30: C2," & "MEMC_MDQ31: C1," & "MEMC_MDQ4: W2," & "MEMC_MDQ5: U3," & "MEMC_MDQ6: U2," & "MEMC_MDQ7: T3," & "MEMC_MDQ8: H3," & "MEMC_MDQ9: H4," & "MEMC_MDQS0: T5," & "MEMC_MDQS1: H5," & "MEMC_MDQS2: P5," & "MEMC_MDQS3: E5," & "MEMC_MDQS8: V5," & "MEMC_MECC0: Y5," & "MEMC_MECC1: AA4," & "MEMC_MECC2: Y4," & "MEMC_MECC3: AA3," & "MEMC_MECC4: AC2," & "MEMC_MECC5: AB2," & "MEMC_MECC6: Y3," & "MEMC_MECC7: AB1," & "MEMC_MODT0: H1," & "MEMC_MODT1: H2," & "MEMC_MRAS_B: K1," & "MEMC_MWE_B: J1," & "PCI_AD0_UART1_SIN1: B23," & "PCI_AD1: C21," & "PCI_AD10_IRQ_B2: D22," & "PCI_AD11: D23," & "PCI_AD12_IRQ_B3: J19," & "PCI_AD13: F21," & "PCI_AD14_IIC_SDA1: G21," & "PCI_AD15: E22," & "PCI_AD16_IIC_SCL1: E23," & "PCI_AD17: J20," & "PCI_AD18_SPISEL_BOOT: F23," & "PCI_AD19: G23," & "PCI_AD20_LCLK1: K19," & "PCI_AD21: H21," & "PCI_AD22_SPIMOSI: L19," & "PCI_AD23: G22," & "PCI_AD24_SPIMISO: H23," & "PCI_AD25: J21," & "PCI_AD26_SPICLK: H22," & "PCI_AD27: J23," & "PCI_AD28_SPISEL: K18," & "PCI_AD29: K21," & "PCI_AD2_UART1_SOUT2: E20," & "PCI_AD3: G19," & "PCI_AD30_FEC_MDC: K22," & "PCI_AD31: K23," & "PCI_AD4_UART1_SIN2: C23," & "PCI_AD5: H19," & "PCI_AD6_IRQ_B0_MCP_IN_B: D21," & "PCI_AD7: F20," & "PCI_AD8_IRQ_B1: E21," & "PCI_AD9: H20," & "PCI_CLK0: T19," & "PCI_CLK1: U19," & "PCI_CLK2: R19," & "PCI_C_BE_B0_FEC_MDIO: L20," & "PCI_C_BE_B1: L23," & "PCI_C_BE_B2_FEC3_COL: L22," & "PCI_C_BE_B3_FEC3_CRS: L21," & "PCI_DEVSEL_B_FEC3_RXD2: N22," & "PCI_FRAME_B_FEC3_RX_DV: M20," & "PCI_GNT_B0_FEC3_TXD2: T21," & "PCI_GNT_B1_FEC3_TXD3: U22," & "PCI_GNT_B2_HDLC1_RXCLK: U21," & "PCI_IDSEL_FEC3_RXD3: N21," & "PCI_INTA_B_UART1_SOUT1: B22," & "PCI_IRDY_B_FEC3_RXD0: M21," & "PCI_PAR_FEC3_RX_CLK: M19," & "PCI_PERR_B_FEC3_TX_EN: P20," & "PCI_REQ_B0_FEC3_TX_ER: P21," & "PCI_REQ_B1_FEC3_TXD0: P22," & "PCI_REQ_B2_FEC3_TXD1: T22," & "PCI_RESET_OUT_B: F19," & "PCI_SERR_B_FEC3_TX_CLK: N19," & "PCI_STOP_B_FEC3_RXD1: N23," & "PCI_SYNC_IN: T23," & "PCI_SYNC_OUT: R20," & "PCI_TRDY_B_FEC3_RX_ER: M23," & "PORESET_B: W22," & "QE_CLK_IN: R22," & "QUIESCE_B: D6," & "RTC_PIT_CLOCK: V23," & "SPICLK_LGPL1: E17," & "SPIMISO: E16," & "SPIMOSI_LGPL0: B19," & "SPISEL: A19," & "SPISEL_BOOT: D18," & "SYS_CLK_IN: R23," & "SYS_XTAL_IN: P23," & "TCK: A2," & "TDI: C5," & "TDO: A3," & "TEST_MODE: C6," & "TMS: D7," & "TRST_B: E9," & "UART1_SIN1: AC6," & "UART1_SIN2: Y9," & "UART1_SOUT1: AB7," & "UART1_SOUT2: W10," & "USBDR_CLK_USBDR_CLK: AC9," & "USBDR_DIR_USBDR_DIR: AA7," & "USBDR_NXT_USBDR_NXT: AC5," & "USBDR_PCTL0_USBDR_PCTL0: W8," & "USBDR_PCTL1_USBDR_PCTL1: W7," & "USBDR_PWRFAULT_USBDR_PWRFAULT: AA6," & "USBDR_STP_USBDR_STP: W6," & "USBDR_TXDRXD0: Y6," & "USBDR_TXDRXD1: W9," & "USBDR_TXDRXD2: AB5," & "USBDR_TXDRXD3: AA5," & "USBDR_TXDRXD4: Y8," & "USBDR_TXDRXD5: AC4," & "USBDR_TXDRXD6: AC3," & "USBDR_TXDRXD7: AB3," & "AVDD1: L16," & "AVDD2: M16," & "AVDD3: N8," & "GVDD: (F6, G6, H6, J6, K6, L6," & "N6, P6, R6, T6, U6, V6," & "V7)," & "MEMC_MVREF: M6," & "NVDD: (F7, F8, F9, F10, F11, F12," & "F13, F14, F15, F16, F17, F18," & "G18, H18, J18, L18, M18, N18," & "P18, R18, T18, U18, V8, V9," & "V10, V11, V12, V13, V14, V15," & "V16, V17, V18)," & "SYS_XTAL_OUT: P19," & "THERM0: E8," & "VDD: (H8, H9, H10, H11, H12, H13," & "H14, H15, H16, J8, J16, K8," & "K16, L8, M8, N16, P8, P16," & "R8, R16, T8, T9, T10, T11," & "T12, T13, T14, T15, T16)," & "VSS: (A1, A23, B1, B4, B6, B9," & "B12, B15, B18, B21, C3, C22," & "D5, D8, D11, D14, D17, D20," & "F2, F22, G4, G20, J2, J9," & "J10, J11, J12, J13, J14, J15," & "J22, K4, K9, K10, K11, K12," & "K13, K14, K15, K20, L9, L10," & "L11, L12, L13, L14, L15, M2," & "M5, M9, M10, M11, M12, M13," & "M14, M15, M22, N9, N10, N11," & "N12, N13, N14, N15, N20, P9," & "P10, P11, P12, P13, P14, P15," & "R2, R9, R10, R11, R12, R13," & "R14, R15, R21, T4, T20, V2," & "V22, W4, Y7, Y10, Y13, Y16," & "Y19, Y21, AA2, AA22, AB4, AB6," & "AB9, AB12, AB15, AB18, AB21, AC1," & "AC23)" ; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (4.00e+07,BOTH); attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute COMPLIANCE_PATTERNS of MPC8309: entity is "(TEST_MODE) (0)"; attribute INSTRUCTION_LENGTH of MPC8309: entity is 8; attribute INSTRUCTION_OPCODE of MPC8309: entity is "BYPASS (11111111)," & "CLAMP (11110001)," & "EXTEST (00000000)," & "HIGHZ (11110010)," & "IDCODE (11110011)," & "PRELOAD (11110000)," & "SAMPLE (11110000)," & "PRIVATE001 (00000101)," & "PRIVATE002 (10010000)," & "PRIVATE003 (10010001)," & "PRIVATE004 (10010010)," & "PRIVATE005 (10010011)," & "PRIVATE006 (00001001)," & "PRIVATE007 (00001010)," & "PRIVATE008 (00110001)," & "PRIVATE009 (00110011)," & "PRIVATE010 (00110100)," & "PRIVATE011 (00110101)," & "PRIVATE012 (00110110)," & "PRIVATE013 (00110111)," & "PRIVATE014 (01100000)," & "PRIVATE015 (01100001)," & "PRIVATE016 (01100010)," & "PRIVATE017 (01100011)," & "PRIVATE018 (01100100)," & "PRIVATE019 (01100101)," & "PRIVATE020 (01100110)," & "PRIVATE021 (01101011)," & "PRIVATE022 (00010000)," & "PRIVATE023 (00010001)," & "PRIVATE024 (00010010)," & "PRIVATE025 (00010011)," & "PRIVATE026 (00010100)," & "PRIVATE027 (01110000)," & "PRIVATE028 (01110001)," & "PRIVATE029 (01110010)," & "PRIVATE030 (01110011)," & "PRIVATE031 (01110100)," & "PRIVATE032 (01110101)," & "PRIVATE033 (01111001)," & "PRIVATE034 (01111010)," & "PRIVATE035 (10000000)," & "PRIVATE036 (10000001)," & "PRIVATE037 (10000010)," & "PRIVATE038 (10000011)," & "PRIVATE039 (00110000)," & "PRIVATE040 (11110100)"; attribute INSTRUCTION_CAPTURE of MPC8309: entity is "xxxxxx01"; attribute INSTRUCTION_PRIVATE of MPC8309: entity is "PRIVATE001," & "PRIVATE002," & "PRIVATE003," & "PRIVATE004," & "PRIVATE005," & "PRIVATE006," & "PRIVATE007," & "PRIVATE008," & "PRIVATE009," & "PRIVATE010," & "PRIVATE011," & "PRIVATE012," & "PRIVATE013," & "PRIVATE014," & "PRIVATE015," & "PRIVATE016," & "PRIVATE017," & "PRIVATE018," & "PRIVATE019," & "PRIVATE020," & "PRIVATE021," & "PRIVATE022," & "PRIVATE023," & "PRIVATE024," & "PRIVATE025," & "PRIVATE026," & "PRIVATE027," & "PRIVATE028," & "PRIVATE029," & "PRIVATE030," & "PRIVATE031," & "PRIVATE032," & "PRIVATE033," & "PRIVATE034," & "PRIVATE035," & "PRIVATE036," & "PRIVATE037," & "PRIVATE038," & "PRIVATE039," & "PRIVATE040"; attribute IDCODE_REGISTER of MPC8309: entity is "0000" & -- Version "0110101011000001" & -- Part Number "00000001110" & -- Manufacturer Identity "1"; -- IEEE 1149.1 Requirement attribute REGISTER_ACCESS of MPC8309: entity is "BYPASS(BYPASS),"& "BOUNDARY (SAMPLE)"; attribute BOUNDARY_LENGTH of MPC8309: entity is 598; attribute BOUNDARY_REGISTER of MPC8309: entity is -- BSR DESCRIPTION TERMS -- cell type = BC_0 - BC_99 -- port = port name -- function -- input = input only -- bidir = bidirectional -- output2 = two state ouput -- output3 = three state ouput -- control = control cell -- controlr = control cell -- internal = placeholder cell -- safe = value that turns off drivers in control cells -- ccell = controlling cell number for I/O direction -- dsval = disabling (input) value -- rslt = result if disabled (input = Z) -- -- num cell port/* func safe [ccell dis rslt] "0 (BC_2, *, control, 0)," & "1 (BC_7, LAD0_LAD0, bidir, X, 0, 0, Z)," & "2 (BC_2, *, control, 0)," & "3 (BC_7, QUIESCE_B, bidir, X, 2, 0, Z)," & "4 (BC_2, *, control, 0)," & "5 (BC_7, GPIO_7_GPIO_7, bidir, X, 4, 0, Z)," & "6 (BC_2, *, control, 0)," & "7 (BC_7, GPIO_6_GPIO_6, bidir, X, 6, 0, Z)," & "8 (BC_2, *, control, 0)," & "9 (BC_7, GPIO_5_GPIO_5, bidir, X, 8, 0, Z)," & "10 (BC_2, *, control, 0)," & "11 (BC_7, GPIO_4_GPIO_4, bidir, X, 10, 0, Z)," & "12 (BC_2, *, control, 0)," & "13 (BC_7, GPIO_3_GPIO_3, bidir, X, 12, 0, Z)," & "14 (BC_2, *, control, 0)," & "15 (BC_7, GPIO_2_GPIO_2, bidir, X, 14, 0, Z)," & "16 (BC_2, *, control, 0)," & "17 (BC_7, GPIO_1_GPIO_1, bidir, X, 16, 0, Z)," & "18 (BC_2, *, control, 0)," & "19 (BC_7, GPIO_0_GPIO_0, bidir, X, 18, 0, Z)," & "20 (BC_2, *, control, 0)," & "21 (BC_7, MEMC_MDQ31, bidir, X, 20, 0, Z)," & "22 (BC_2, *, control, 0)," & "23 (BC_7, MEMC_MDQ15, bidir, X, 22, 0, Z)," & "24 (BC_2, *, control, 0)," & "25 (BC_7, MEMC_MDQ30, bidir, X, 24, 0, Z)," & "26 (BC_2, *, control, 0)," & "27 (BC_7, MEMC_MDQ14, bidir, X, 26, 0, Z)," & "28 (BC_2, *, control, 0)," & "29 (BC_7, MEMC_MDQ29, bidir, X, 28, 0, Z)," & "30 (BC_2, *, control, 0)," & "31 (BC_7, MEMC_MDQ13, bidir, X, 30, 0, Z)," & "32 (BC_2, *, control, 0)," & "33 (BC_7, MEMC_MDQ28, bidir, X, 32, 0, Z)," & "34 (BC_2, *, control, 0)," & "35 (BC_7, MEMC_MDQ12, bidir, X, 34, 0, Z)," & "36 (BC_2, *, control, 0)," & "37 (BC_7, MEMC_MDQS3, bidir, X, 36, 0, Z)," & "38 (BC_2, *, control, 0)," & "39 (BC_7, MEMC_MDQS1, bidir, X, 38, 0, Z)," & "40 (BC_2, *, control, 0)," & "41 (BC_7, MEMC_MDM3, bidir, X, 40, 0, Z)," & "42 (BC_2, *, control, 0)," & "43 (BC_7, MEMC_MDM1, bidir, X, 42, 0, Z)," & "44 (BC_2, *, control, 0)," & "45 (BC_7, MEMC_MDQ27, bidir, X, 44, 0, Z)," & "46 (BC_2, *, control, 0)," & "47 (BC_7, MEMC_MDQ11, bidir, X, 46, 0, Z)," & "48 (BC_2, *, control, 0)," & "49 (BC_7, MEMC_MDQ26, bidir, X, 48, 0, Z)," & "50 (BC_2, *, control, 0)," & "51 (BC_7, MEMC_MDQ10, bidir, X, 50, 0, Z)," & "52 (BC_2, *, control, 0)," & "53 (BC_7, MEMC_MDQ25, bidir, X, 52, 0, Z)," & "54 (BC_2, *, control, 0)," & "55 (BC_7, MEMC_MDQ9, bidir, X, 54, 0, Z)," & "56 (BC_2, *, control, 0)," & "57 (BC_7, MEMC_MDQ24, bidir, X, 56, 0, Z)," & "58 (BC_2, *, control, 0)," & "59 (BC_7, MEMC_MDQ8, bidir, X, 58, 0, Z)," & "60 (BC_2, *, control, 0)," & "61 (BC_7, MEMC_MODT1, bidir, X, 60, 0, Z)," & "62 (BC_2, *, control, 0)," & "63 (BC_7, MEMC_MODT0, bidir, X, 62, 0, Z)," & "64 (BC_2, *, control, 0)," & "65 (BC_7, MEMC_MCS_B1, bidir, X, 64, 0, Z)," & "66 (BC_2, *, control, 0)," & "67 (BC_7, MEMC_MCS_B0, bidir, X, 66, 0, Z)," & "68 (BC_2, *, control, 0)," & "69 (BC_7, MEMC_MCAS_B, bidir, X, 68, 0, Z)," & "70 (BC_2, *, control, 0)," & "71 (BC_7, MEMC_MWE_B, bidir, X, 70, 0, Z)," & "72 (BC_2, *, control, 0)," & "73 (BC_7, MEMC_MRAS_B, bidir, X, 72, 0, Z)," & "74 (BC_2, *, control, 0)," & "75 (BC_7, MEMC_MBA1, bidir, X, 74, 0, Z)," & "76 (BC_2, *, control, 0)," & "77 (BC_7, MEMC_MBA0, bidir, X, 76, 0, Z)," & "78 (BC_2, *, control, 0)," & "79 (BC_7, MEMC_MA10, bidir, X, 78, 0, Z)," & "80 (BC_2, *, control, 0)," & "81 (BC_7, MEMC_MA0, bidir, X, 80, 0, Z)," & "82 (BC_2, *, control, 0)," & "83 (BC_7, MEMC_MA1, bidir, X, 82, 0, Z)," & "84 (BC_2, *, control, 0)," & "85 (BC_7, MEMC_MA2, bidir, X, 84, 0, Z)," & "86 (BC_2, *, control, 0)," & "87 (BC_7, MEMC_MA3, bidir, X, 86, 0, Z)," & "88 (BC_2, *, control, 0)," & "89 (BC_7, MEMC_MA4, bidir, X, 88, 0, Z)," & "90 (BC_2, *, control, 0)," & "91 (BC_7, MEMC_MA5, bidir, X, 90, 0, Z)," & "92 (BC_2, *, control, 0)," & "93 (BC_7, MEMC_MA6, bidir, X, 92, 0, Z)," & "94 (BC_2, *, control, 0)," & "95 (BC_7, MEMC_MA7, bidir, X, 94, 0, Z)," & "96 (BC_2, *, control, 0)," & "97 (BC_7, MEMC_MA8, bidir, X, 96, 0, Z)," & "98 (BC_2, *, control, 0)," & "99 (BC_7, MEMC_MA9, bidir, X, 98, 0, Z)," & "100 (BC_2, *, control, 0)," & "101 (BC_7, MEMC_MA11, bidir, X, 100, 0, Z)," & "102 (BC_2, *, control, 0)," & "103 (BC_7, MEMC_MA12, bidir, X, 102, 0, Z)," & "104 (BC_2, *, control, 0)," & "105 (BC_7, MEMC_MA13, bidir, X, 104, 0, Z)," & "106 (BC_2, *, control, 0)," & "107 (BC_7, MEMC_MBA2, bidir, X, 106, 0, Z)," & "108 (BC_2, *, control, 0)," & "109 (BC_7, MEMC_MCK_B1, bidir, X, 108, 0, Z)," & "110 (BC_2, *, control, 0)," & "111 (BC_7, MEMC_MCK1, bidir, X, 110, 0, Z)," & "112 (BC_2, *, control, 0)," & "113 (BC_7, MEMC_MCK0, bidir, X, 112, 0, Z)," & "114 (BC_2, *, control, 0)," & "115 (BC_7, MEMC_MCK_B0, bidir, X, 114, 0, Z)," & "116 (BC_2, *, control, 0)," & "117 (BC_7, MEMC_MCKE, bidir, X, 116, 0, Z)," & "118 (BC_2, *, control, 0)," & "119 (BC_7, MEMC_MDQ23, bidir, X, 118, 0, Z)," & "120 (BC_2, *, control, 0)," & "121 (BC_7, MEMC_MDQ7, bidir, X, 120, 0, Z)," & "122 (BC_2, *, control, 0)," & "123 (BC_7, MEMC_MDQ22, bidir, X, 122, 0, Z)," & "124 (BC_2, *, control, 0)," & "125 (BC_7, MEMC_MDQ6, bidir, X, 124, 0, Z)," & "126 (BC_2, *, control, 0)," & "127 (BC_7, MEMC_MDQ21, bidir, X, 126, 0, Z)," & "128 (BC_2, *, control, 0)," & "129 (BC_7, MEMC_MDQ5, bidir, X, 128, 0, Z)," & "130 (BC_2, *, control, 0)," & "131 (BC_7, MEMC_MDQ20, bidir, X, 130, 0, Z)," & "132 (BC_2, *, control, 0)," & "133 (BC_7, MEMC_MDQ4, bidir, X, 132, 0, Z)," & "134 (BC_2, *, control, 0)," & "135 (BC_7, MEMC_MDQS2, bidir, X, 134, 0, Z)," & "136 (BC_2, *, control, 0)," & "137 (BC_7, MEMC_MDQS0, bidir, X, 136, 0, Z)," & "138 (BC_2, *, control, 0)," & "139 (BC_7, MEMC_MDM2, bidir, X, 138, 0, Z)," & "140 (BC_2, *, control, 0)," & "141 (BC_7, MEMC_MDM0, bidir, X, 140, 0, Z)," & "142 (BC_2, *, control, 0)," & "143 (BC_7, MEMC_MDQ19, bidir, X, 142, 0, Z)," & "144 (BC_2, *, control, 0)," & "145 (BC_7, MEMC_MDQ3, bidir, X, 144, 0, Z)," & "146 (BC_2, *, control, 0)," & "147 (BC_7, MEMC_MDQ18, bidir, X, 146, 0, Z)," & "148 (BC_2, *, control, 0)," & "149 (BC_7, MEMC_MDQ2, bidir, X, 148, 0, Z)," & "150 (BC_2, *, control, 0)," & "151 (BC_7, MEMC_MDQ17, bidir, X, 150, 0, Z)," & "152 (BC_2, *, control, 0)," & "153 (BC_7, MEMC_MDQ1, bidir, X, 152, 0, Z)," & "154 (BC_2, *, control, 0)," & "155 (BC_7, MEMC_MDQ16, bidir, X, 154, 0, Z)," & "156 (BC_2, *, control, 0)," & "157 (BC_7, MEMC_MDQ0, bidir, X, 156, 0, Z)," & "158 (BC_2, *, control, 0)," & "159 (BC_7, MEMC_MECC7, bidir, X, 158, 0, Z)," & "160 (BC_2, *, control, 0)," & "161 (BC_7, MEMC_MECC6, bidir, X, 160, 0, Z)," & "162 (BC_2, *, control, 0)," & "163 (BC_7, MEMC_MECC5, bidir, X, 162, 0, Z)," & "164 (BC_2, *, control, 0)," & "165 (BC_7, MEMC_MECC4, bidir, X, 164, 0, Z)," & "166 (BC_2, *, control, 0)," & "167 (BC_7, MEMC_MDM8, bidir, X, 166, 0, Z)," & "168 (BC_2, *, control, 0)," & "169 (BC_7, MEMC_MECC3, bidir, X, 168, 0, Z)," & "170 (BC_2, *, control, 0)," & "171 (BC_7, MEMC_MECC2, bidir, X, 170, 0, Z)," & "172 (BC_2, *, control, 0)," & "173 (BC_7, MEMC_MDQS8, bidir, X, 172, 0, Z)," & "174 (BC_2, *, control, 0)," & "175 (BC_7, MEMC_MECC1, bidir, X, 174, 0, Z)," & "176 (BC_2, *, control, 0)," & "177 (BC_7, MEMC_MECC0, bidir, X, 176, 0, Z)," & "178 (BC_2, *, control, 0)," & "179 (BC_7, USBDR_STP_USBDR_STP, bidir, X, 178, 0, Z)," & "180 (BC_2, *, control, 0)," & "181 (BC_7, USBDR_PCTL1_USBDR_PCTL1, bidir, X, 180, 0, Z)," & "182 (BC_2, *, control, 0)," & "183 (BC_7, USBDR_PCTL0_USBDR_PCTL0, bidir, X, 182, 0, Z)," & "184 (BC_2, *, control, 0)," & "185 (BC_7, USBDR_TXDRXD7, bidir, X, 184, 0, Z)," & "186 (BC_2, *, control, 0)," & "187 (BC_7, USBDR_TXDRXD6, bidir, X, 186, 0, Z)," & "188 (BC_2, *, control, 0)," & "189 (BC_7, USBDR_TXDRXD5, bidir, X, 188, 0, Z)," & "190 (BC_2, *, control, 0)," & "191 (BC_7, USBDR_TXDRXD4, bidir, X, 190, 0, Z)," & "192 (BC_2, *, control, 0)," & "193 (BC_7, USBDR_TXDRXD3, bidir, X, 192, 0, Z)," & "194 (BC_2, *, control, 0)," & "195 (BC_7, USBDR_TXDRXD2, bidir, X, 194, 0, Z)," & "196 (BC_2, *, control, 0)," & "197 (BC_7, USBDR_TXDRXD1, bidir, X, 196, 0, Z)," & "198 (BC_2, *, control, 0)," & "199 (BC_7, USBDR_TXDRXD0, bidir, X, 198, 0, Z)," & "200 (BC_2, *, control, 0)," & "201 (BC_7, USBDR_NXT_USBDR_NXT, bidir, X, 200, 0, Z)," & "202 (BC_2, *, control, 0)," & "203 (BC_7, USBDR_DIR_USBDR_DIR, bidir, X, 202, 0, Z)," & "204 (BC_2, *, control, 0)," & "205 (BC_7, USBDR_CLK_USBDR_CLK, bidir, X, 204, 0, Z)," & "206 (BC_2, *, control, 0)," & "207 (BC_7, USBDR_PWRFAULT_USBDR_PWRFAULT, bidir, X, 206, 0, Z)," & "208 (BC_2, *, control, 0)," & "209 (BC_7, UART1_SIN2, bidir, X, 208, 0, Z)," & "210 (BC_2, *, control, 0)," & "211 (BC_7, UART1_SOUT2, bidir, X, 210, 0, Z)," & "212 (BC_2, *, control, 0)," & "213 (BC_7, UART1_SIN1, bidir, X, 212, 0, Z)," & "214 (BC_2, *, control, 0)," & "215 (BC_7, UART1_SOUT1, bidir, X, 214, 0, Z)," & "216 (BC_2, *, control, 0)," & "217 (BC_7, FEC3_TXD3, bidir, X, 216, 0, Z)," & "218 (BC_2, *, control, 0)," & "219 (BC_7, FEC3_TXD2_USBDR_TXDRXD7, bidir, X, 218, 0, Z)," & "220 (BC_2, *, control, 0)," & "221 (BC_7, FEC3_TXD1, bidir, X, 220, 0, Z)," & "222 (BC_2, *, control, 0)," & "223 (BC_7, FEC3_TXD0_USBDR_TXDRXD6, bidir, X, 222, 0, Z)," & "224 (BC_2, *, control, 0)," & "225 (BC_7, FEC3_TX_ER, bidir, X, 224, 0, Z)," & "226 (BC_2, *, control, 0)," & "227 (BC_7, FEC3_TX_EN_USBDR_TXDRXD5, bidir, X, 226, 0, Z)," & "228 (BC_2, *, control, 0)," & "229 (BC_7, FEC3_TX_CLK, bidir, X, 228, 0, Z)," & "230 (BC_2, *, control, 0)," & "231 (BC_7, FEC3_RXD3_USBDR_TXDRXD4, bidir, X, 230, 0, Z)," & "232 (BC_2, *, control, 0)," & "233 (BC_7, FEC3_RXD2, bidir, X, 232, 0, Z)," & "234 (BC_2, *, control, 0)," & "235 (BC_7, FEC3_RXD1_USBDR_TXDRXD3, bidir, X, 234, 0, Z)," & "236 (BC_2, *, control, 0)," & "237 (BC_7, FEC3_RXD0, bidir, X, 236, 0, Z)," & "238 (BC_2, *, control, 0)," & "239 (BC_7, FEC3_RX_ER_USBDR_TXDRXD2, bidir, X, 238, 0, Z)," & "240 (BC_2, *, control, 0)," & "241 (BC_7, FEC3_RX_DV, bidir, X, 240, 0, Z)," & "242 (BC_2, *, control, 0)," & "243 (BC_7, FEC3_RX_CLK_USBDR_TXDRXD1, bidir, X, 242, 0, Z)," & "244 (BC_2, *, control, 0)," & "245 (BC_7, FEC3_CRS, bidir, X, 244, 0, Z)," & "246 (BC_2, *, control, 0)," & "247 (BC_7, FEC3_COL_USBDR_TXDRXD0, bidir, X, 246, 0, Z)," & "248 (BC_2, *, control, 0)," & "249 (BC_7, FEC2_TXD3_FEC2_TXD3, bidir, X, 248, 0, Z)," & "250 (BC_2, *, control, 0)," & "251 (BC_7, FEC2_TXD2_FEC2_TXD2, bidir, X, 250, 0, Z)," & "252 (BC_2, *, control, 0)," & "253 (BC_7, FEC2_TXD1_FEC2_TXD1, bidir, X, 252, 0, Z)," & "254 (BC_2, *, control, 0)," & "255 (BC_7, FEC2_TXD0_FEC2_TXD0, bidir, X, 254, 0, Z)," & "256 (BC_2, *, control, 0)," & "257 (BC_7, FEC2_TX_ER_FEC2_TX_ER, bidir, X, 256, 0, Z)," & "258 (BC_2, *, control, 0)," & "259 (BC_7, FEC2_TX_EN_FEC2_TX_EN, bidir, X, 258, 0, Z)," & "260 (BC_2, *, control, 0)," & "261 (BC_7, FEC2_TX_CLK_FEC2_TX_CLK, bidir, X, 260, 0, Z)," & "262 (BC_2, *, control, 0)," & "263 (BC_7, FEC2_RXD3_FEC2_RXD3, bidir, X, 262, 0, Z)," & "264 (BC_2, *, control, 0)," & "265 (BC_7, FEC2_RXD2_FEC2_RXD2, bidir, X, 264, 0, Z)," & "266 (BC_2, *, control, 0)," & "267 (BC_7, FEC2_RXD1_FEC2_RXD1, bidir, X, 266, 0, Z)," & "268 (BC_2, *, control, 0)," & "269 (BC_7, FEC2_RXD0_FEC2_RXD0, bidir, X, 268, 0, Z)," & "270 (BC_2, *, control, 0)," & "271 (BC_7, FEC2_RX_ER_FEC2_RX_ER, bidir, X, 270, 0, Z)," & "272 (BC_2, *, control, 0)," & "273 (BC_7, FEC2_RX_DV_FEC2_RX_DV, bidir, X, 272, 0, Z)," & "274 (BC_2, *, control, 0)," & "275 (BC_7, FEC2_RX_CLK_FEC2_RX_CLK, bidir, X, 274, 0, Z)," & "276 (BC_2, *, control, 0)," & "277 (BC_7, FEC2_CRS_FEC2_CRS, bidir, X, 276, 0, Z)," & "278 (BC_2, *, control, 0)," & "279 (BC_7, FEC2_COL_FEC2_COL, bidir, X, 278, 0, Z)," & "280 (BC_2, *, control, 0)," & "281 (BC_7, FEC1_TXD3_FEC1_TXD3, bidir, X, 280, 0, Z)," & "282 (BC_2, *, control, 0)," & "283 (BC_7, FEC1_TXD2_FEC1_TXD2, bidir, X, 282, 0, Z)," & "284 (BC_2, *, control, 0)," & "285 (BC_7, FEC1_TXD1_FEC1_TXD1, bidir, X, 284, 0, Z)," & "286 (BC_2, *, control, 0)," & "287 (BC_7, FEC1_TXD0_FEC1_TXD0, bidir, X, 286, 0, Z)," & "288 (BC_2, *, control, 0)," & "289 (BC_7, FEC1_TX_ER_FEC1_TX_ER, bidir, X, 288, 0, Z)," & "290 (BC_2, *, control, 0)," & "291 (BC_7, FEC1_TX_EN_FEC1_TX_EN, bidir, X, 290, 0, Z)," & "292 (BC_2, *, control, 0)," & "293 (BC_7, FEC1_TX_CLK_FEC1_TX_CLK, bidir, X, 292, 0, Z)," & "294 (BC_2, *, control, 0)," & "295 (BC_7, FEC1_RXD3_FEC1_RXD3, bidir, X, 294, 0, Z)," & "296 (BC_2, *, control, 0)," & "297 (BC_7, FEC1_RXD2_FEC1_RXD2, bidir, X, 296, 0, Z)," & "298 (BC_2, *, control, 0)," & "299 (BC_7, FEC1_RXD1_FEC1_RXD1, bidir, X, 298, 0, Z)," & "300 (BC_2, *, control, 0)," & "301 (BC_7, FEC1_RXD0_FEC1_RXD0, bidir, X, 300, 0, Z)," & "302 (BC_2, *, control, 0)," & "303 (BC_7, FEC1_RX_ER_FEC1_RX_ER, bidir, X, 302, 0, Z)," & "304 (BC_2, *, control, 0)," & "305 (BC_7, FEC1_RX_DV_FEC1_RX_DV, bidir, X, 304, 0, Z)," & "306 (BC_2, *, control, 0)," & "307 (BC_7, FEC1_RX_CLK_FEC1_RX_CLK, bidir, X, 306, 0, Z)," & "308 (BC_2, *, control, 0)," & "309 (BC_7, FEC1_CRS_FEC1_CRS, bidir, X, 308, 0, Z)," & "310 (BC_2, *, control, 0)," & "311 (BC_7, FEC1_COL_FEC1_COL, bidir, X, 310, 0, Z)," & "312 (BC_2, *, control, 0)," & "313 (BC_7, FEC_MDIO, bidir, X, 312, 0, Z)," & "314 (BC_2, *, control, 0)," & "315 (BC_7, FEC_MDC, bidir, X, 314, 0, Z)," & "316 (BC_2, *, control, 0)," & "317 (BC_7, HDLC1_TXCLK_HDLC1_TXCLK, bidir, X, 316, 0, Z)," & "318 (BC_2, *, control, 0)," & "319 (BC_7, HDLC1_RXCLK, bidir, X, 318, 0, Z)," & "320 (BC_2, *, control, 0)," & "321 (BC_7, HDLC1_TXD_HDLC1_TXD, bidir, X, 320, 0, Z)," & "322 (BC_2, *, control, 0)," & "323 (BC_7, HDLC1_RXD, bidir, X, 322, 0, Z)," & "324 (BC_2, *, control, 0)," & "325 (BC_7, HDLC1_CD_B_HDLC1_CD_B, bidir, X, 324, 0, Z)," & "326 (BC_2, *, control, 0)," & "327 (BC_7, HDLC1_CTS_B_HDLC1_CTS_B, bidir, X, 326, 0, Z)," & "328 (BC_2, *, control, 0)," & "329 (BC_7, HDLC1_RTS_B_HDLC1_RTS_B, bidir, X, 328, 0, Z)," & "330 (BC_2, *, control, 0)," & "331 (BC_7, HDLC2_TXCLK_HDLC2_TXCLK, bidir, X, 330, 0, Z)," & "332 (BC_2, *, control, 0)," & "333 (BC_7, HDLC2_RXCLK_HDLC2_RXCLK, bidir, X, 332, 0, Z)," & "334 (BC_2, *, control, 0)," & "335 (BC_7, HDLC2_TXD_HDLC2_TXD, bidir, X, 334, 0, Z)," & "336 (BC_2, *, control, 0)," & "337 (BC_7, HDLC2_RXD_HDLC2_RXD, bidir, X, 336, 0, Z)," & "338 (BC_2, *, control, 0)," & "339 (BC_7, HDLC2_CD_B_HDLC2_CD_B, bidir, X, 338, 0, Z)," & "340 (BC_2, *, control, 0)," & "341 (BC_7, HDLC2_CTS_B_HDLC2_CTS_B, bidir, X, 340, 0, Z)," & "342 (BC_2, *, control, 0)," & "343 (BC_7, HDLC2_RTS_B_HDLC2_RTS_B, bidir, X, 342, 0, Z)," & "344 (BC_2, *, internal, X)," & "345 (BC_2, RTC_PIT_CLOCK, input, X)," & "346 (BC_2, *, internal, X)," & "347 (BC_2, PORESET_B, input, X)," & "348 (BC_2, *, control, 0)," & "349 (BC_7, PCI_CLK1, bidir, X, 348, 0, Z)," & "350 (BC_2, *, control, 0)," & "351 (BC_7, HRESET_B, bidir, X, 350, 0, Z)," & "352 (BC_2, *, control, 0)," & "353 (BC_7, PCI_CLK0, bidir, X, 352, 0, Z)," & "354 (BC_2, *, control, 0)," & "355 (BC_7, M66EN_HDLC1_RXD, bidir, X, 354, 0, Z)," & "356 (BC_2, *, control, 0)," & "357 (BC_7, PCI_CLK2, bidir, X, 356, 0, Z)," & "358 (BC_2, *, control, 0)," & "359 (BC_7, PCI_GNT_B2_HDLC1_RXCLK, bidir, X, 358, 0, Z)," & "360 (BC_2, *, internal, X)," & "361 (BC_2, CFG_CLKIN_DIV_B, input, X)," & "362 (BC_2, *, control, 0)," & "363 (BC_7, PCI_GNT_B1_FEC3_TXD3, bidir, X, 362, 0, Z)," & "364 (BC_2, *, control, 0)," & "365 (BC_7, PCI_SYNC_OUT, bidir, X, 364, 0, Z)," & "366 (BC_2, *, control, 0)," & "367 (BC_7, PCI_GNT_B0_FEC3_TXD2, bidir, X, 366, 0, Z)," & "368 (BC_2, *, internal, X)," & "369 (BC_2, PCI_SYNC_IN, input, X)," & "370 (BC_2, *, control, 0)," & "371 (BC_7, PCI_REQ_B2_FEC3_TXD1, bidir, X, 370, 0, Z)," & "372 (BC_2, *, internal, X)," & "373 (BC_2, QE_CLK_IN, input, X)," & "374 (BC_2, *, control, 0)," & "375 (BC_7, PCI_REQ_B1_FEC3_TXD0, bidir, X, 374, 0, Z)," & "376 (BC_2, *, internal, X)," & "377 (BC_2, SYS_CLK_IN, input, X)," & "378 (BC_2, *, internal, X)," & "379 (BC_2, SYS_XTAL_IN, input, X)," & "380 (BC_2, *, control, 0)," & "381 (BC_7, PCI_REQ_B0_FEC3_TX_ER, bidir, X, 380, 0, Z)," & "382 (BC_2, *, control, 0)," & "383 (BC_7, PCI_PERR_B_FEC3_TX_EN, bidir, X, 382, 0, Z)," & "384 (BC_2, *, control, 0)," & "385 (BC_7, PCI_SERR_B_FEC3_TX_CLK, bidir, X, 384, 0, Z)," & "386 (BC_2, *, control, 0)," & "387 (BC_7, PCI_IDSEL_FEC3_RXD3, bidir, X, 386, 0, Z)," & "388 (BC_2, *, control, 0)," & "389 (BC_7, PCI_DEVSEL_B_FEC3_RXD2, bidir, X, 388, 0, Z)," & "390 (BC_2, *, control, 0)," & "391 (BC_7, PCI_STOP_B_FEC3_RXD1, bidir, X, 390, 0, Z)," & "392 (BC_2, *, control, 0)," & "393 (BC_7, PCI_IRDY_B_FEC3_RXD0, bidir, X, 392, 0, Z)," & "394 (BC_2, *, control, 0)," & "395 (BC_7, PCI_TRDY_B_FEC3_RX_ER, bidir, X, 394, 0, Z)," & "396 (BC_2, *, control, 0)," & "397 (BC_7, PCI_FRAME_B_FEC3_RX_DV, bidir, X, 396, 0, Z)," & "398 (BC_2, *, control, 0)," & "399 (BC_7, PCI_PAR_FEC3_RX_CLK, bidir, X, 398, 0, Z)," & "400 (BC_2, *, control, 0)," & "401 (BC_7, PCI_C_BE_B3_FEC3_CRS, bidir, X, 400, 0, Z)," & "402 (BC_2, *, control, 0)," & "403 (BC_7, PCI_C_BE_B2_FEC3_COL, bidir, X, 402, 0, Z)," & "404 (BC_2, *, control, 0)," & "405 (BC_7, PCI_C_BE_B1, bidir, X, 404, 0, Z)," & "406 (BC_2, *, control, 0)," & "407 (BC_7, PCI_C_BE_B0_FEC_MDIO, bidir, X, 406, 0, Z)," & "408 (BC_2, *, control, 0)," & "409 (BC_7, PCI_AD31, bidir, X, 408, 0, Z)," & "410 (BC_2, *, control, 0)," & "411 (BC_7, PCI_AD30_FEC_MDC, bidir, X, 410, 0, Z)," & "412 (BC_2, *, control, 0)," & "413 (BC_7, PCI_AD29, bidir, X, 412, 0, Z)," & "414 (BC_2, *, control, 0)," & "415 (BC_7, PCI_AD28_SPISEL, bidir, X, 414, 0, Z)," & "416 (BC_2, *, control, 0)," & "417 (BC_7, PCI_AD27, bidir, X, 416, 0, Z)," & "418 (BC_2, *, control, 0)," & "419 (BC_7, PCI_AD26_SPICLK, bidir, X, 418, 0, Z)," & "420 (BC_2, *, control, 0)," & "421 (BC_7, PCI_AD25, bidir, X, 420, 0, Z)," & "422 (BC_2, *, control, 0)," & "423 (BC_7, PCI_AD24_SPIMISO, bidir, X, 422, 0, Z)," & "424 (BC_2, *, control, 0)," & "425 (BC_7, PCI_AD23, bidir, X, 424, 0, Z)," & "426 (BC_2, *, control, 0)," & "427 (BC_7, PCI_AD22_SPIMOSI, bidir, X, 426, 0, Z)," & "428 (BC_2, *, control, 0)," & "429 (BC_7, PCI_AD21, bidir, X, 428, 0, Z)," & "430 (BC_2, *, control, 0)," & "431 (BC_7, PCI_AD20_LCLK1, bidir, X, 430, 0, Z)," & "432 (BC_2, *, control, 0)," & "433 (BC_7, PCI_AD19, bidir, X, 432, 0, Z)," & "434 (BC_2, *, control, 0)," & "435 (BC_7, PCI_AD18_SPISEL_BOOT, bidir, X, 434, 0, Z)," & "436 (BC_2, *, control, 0)," & "437 (BC_7, PCI_AD17, bidir, X, 436, 0, Z)," & "438 (BC_2, *, control, 0)," & "439 (BC_7, PCI_AD16_IIC_SCL1, bidir, X, 438, 0, Z)," & "440 (BC_2, *, control, 0)," & "441 (BC_7, PCI_AD15, bidir, X, 440, 0, Z)," & "442 (BC_2, *, control, 0)," & "443 (BC_7, PCI_AD14_IIC_SDA1, bidir, X, 442, 0, Z)," & "444 (BC_2, *, control, 0)," & "445 (BC_7, PCI_AD13, bidir, X, 444, 0, Z)," & "446 (BC_2, *, control, 0)," & "447 (BC_7, PCI_AD12_IRQ_B3, bidir, X, 446, 0, Z)," & "448 (BC_2, *, control, 0)," & "449 (BC_7, PCI_AD11, bidir, X, 448, 0, Z)," & "450 (BC_2, *, control, 0)," & "451 (BC_7, PCI_AD10_IRQ_B2, bidir, X, 450, 0, Z)," & "452 (BC_2, *, control, 0)," & "453 (BC_7, PCI_AD9, bidir, X, 452, 0, Z)," & "454 (BC_2, *, control, 0)," & "455 (BC_7, PCI_AD8_IRQ_B1, bidir, X, 454, 0, Z)," & "456 (BC_2, *, control, 0)," & "457 (BC_7, PCI_AD7, bidir, X, 456, 0, Z)," & "458 (BC_2, *, control, 0)," & "459 (BC_7, PCI_AD6_IRQ_B0_MCP_IN_B, bidir, X, 458, 0, Z)," & "460 (BC_2, *, control, 0)," & "461 (BC_7, PCI_AD5, bidir, X, 460, 0, Z)," & "462 (BC_2, *, control, 0)," & "463 (BC_7, PCI_AD4_UART1_SIN2, bidir, X, 462, 0, Z)," & "464 (BC_2, *, control, 0)," & "465 (BC_7, PCI_AD3, bidir, X, 464, 0, Z)," & "466 (BC_2, *, control, 0)," & "467 (BC_7, PCI_AD2_UART1_SOUT2, bidir, X, 466, 0, Z)," & "468 (BC_2, *, control, 0)," & "469 (BC_7, PCI_AD1, bidir, X, 468, 0, Z)," & "470 (BC_2, *, control, 0)," & "471 (BC_7, PCI_AD0_UART1_SIN1, bidir, X, 470, 0, Z)," & "472 (BC_2, *, control, 0)," & "473 (BC_7, PCI_RESET_OUT_B, bidir, X, 472, 0, Z)," & "474 (BC_2, *, control, 0)," & "475 (BC_7, PCI_INTA_B_UART1_SOUT1, bidir, X, 474, 0, Z)," & "476 (BC_2, *, control, 0)," & "477 (BC_7, IRQ_B3, bidir, X, 476, 0, Z)," & "478 (BC_2, *, control, 0)," & "479 (BC_7, IRQ_B2_LGPL5, bidir, X, 478, 0, Z)," & "480 (BC_2, *, control, 0)," & "481 (BC_7, IRQ_B1, bidir, X, 480, 0, Z)," & "482 (BC_2, *, control, 0)," & "483 (BC_7, IRQ_B0_MCP_IN_B_LGPL4, bidir, X, 482, 0, Z)," & "484 (BC_2, *, control, 0)," & "485 (BC_7, IIC_SCL2, bidir, X, 484, 0, Z)," & "486 (BC_2, *, control, 0)," & "487 (BC_7, IIC_SDA2_LGPL3, bidir, X, 486, 0, Z)," & "488 (BC_2, *, control, 0)," & "489 (BC_7, IIC_SCL1, bidir, X, 488, 0, Z)," & "490 (BC_2, *, control, 0)," & "491 (BC_7, IIC_SDA1_LGPL2, bidir, X, 490, 0, Z)," & "492 (BC_2, *, control, 0)," & "493 (BC_7, SPISEL_BOOT, bidir, X, 492, 0, Z)," & "494 (BC_2, *, control, 0)," & "495 (BC_7, SPISEL, bidir, X, 494, 0, Z)," & "496 (BC_2, *, control, 0)," & "497 (BC_7, SPICLK_LGPL1, bidir, X, 496, 0, Z)," & "498 (BC_2, *, control, 0)," & "499 (BC_7, SPIMISO, bidir, X, 498, 0, Z)," & "500 (BC_2, *, control, 0)," & "501 (BC_7, SPIMOSI_LGPL0, bidir, X, 500, 0, Z)," & "502 (BC_2, *, control, 0)," & "503 (BC_7, GPIO_15, bidir, X, 502, 0, Z)," & "504 (BC_2, *, control, 0)," & "505 (BC_7, GPIO_14_LALE, bidir, X, 504, 0, Z)," & "506 (BC_2, *, control, 0)," & "507 (BC_7, GPIO_13, bidir, X, 506, 0, Z)," & "508 (BC_2, *, control, 0)," & "509 (BC_7, GPIO_12_LBCTL, bidir, X, 508, 0, Z)," & "510 (BC_2, *, control, 0)," & "511 (BC_7, GPIO_11, bidir, X, 510, 0, Z)," & "512 (BC_2, *, control, 0)," & "513 (BC_7, GPIO_10_LWE_B1, bidir, X, 512, 0, Z)," & "514 (BC_2, *, control, 0)," & "515 (BC_7, GPIO_9, bidir, X, 514, 0, Z)," & "516 (BC_2, *, control, 0)," & "517 (BC_7, GPIO_8_LWE_B0, bidir, X, 516, 0, Z)," & "518 (BC_2, *, control, 0)," & "519 (BC_7, LALE, bidir, X, 518, 0, Z)," & "520 (BC_2, *, control, 0)," & "521 (BC_7, LGPL5, bidir, X, 520, 0, Z)," & "522 (BC_2, *, control, 0)," & "523 (BC_7, LGPL4, bidir, X, 522, 0, Z)," & "524 (BC_2, *, control, 0)," & "525 (BC_7, LGPL3, bidir, X, 524, 0, Z)," & "526 (BC_2, *, control, 0)," & "527 (BC_7, LGPL2, bidir, X, 526, 0, Z)," & "528 (BC_2, *, control, 0)," & "529 (BC_7, LGPL1, bidir, X, 528, 0, Z)," & "530 (BC_2, *, control, 0)," & "531 (BC_7, LGPL0, bidir, X, 530, 0, Z)," & "532 (BC_2, *, control, 0)," & "533 (BC_7, LBCTL, bidir, X, 532, 0, Z)," & "534 (BC_2, *, control, 0)," & "535 (BC_7, LWE_B1, bidir, X, 534, 0, Z)," & "536 (BC_2, *, control, 0)," & "537 (BC_7, LWE_B0, bidir, X, 536, 0, Z)," & "538 (BC_2, *, control, 0)," & "539 (BC_7, LCS_B3_LCS_B3, bidir, X, 538, 0, Z)," & "540 (BC_2, *, control, 0)," & "541 (BC_7, LCS_B2_LCS_B2, bidir, X, 540, 0, Z)," & "542 (BC_2, *, control, 0)," & "543 (BC_7, LCLK0_LCLK0, bidir, X, 542, 0, Z)," & "544 (BC_2, *, control, 0)," & "545 (BC_7, LCS_B1_LCS_B1, bidir, X, 544, 0, Z)," & "546 (BC_2, *, control, 0)," & "547 (BC_7, LCS_B0_LCS_B0, bidir, X, 546, 0, Z)," & "548 (BC_2, *, control, 0)," & "549 (BC_7, LA25_LA25, bidir, X, 548, 0, Z)," & "550 (BC_2, *, control, 0)," & "551 (BC_7, LA24_LA24, bidir, X, 550, 0, Z)," & "552 (BC_2, *, control, 0)," & "553 (BC_7, LA23_LA23, bidir, X, 552, 0, Z)," & "554 (BC_2, *, control, 0)," & "555 (BC_7, LA22_LA22, bidir, X, 554, 0, Z)," & "556 (BC_2, *, control, 0)," & "557 (BC_7, LA21_LA21, bidir, X, 556, 0, Z)," & "558 (BC_2, *, control, 0)," & "559 (BC_7, LA20_LA20, bidir, X, 558, 0, Z)," & "560 (BC_2, *, control, 0)," & "561 (BC_7, LA19_LA19, bidir, X, 560, 0, Z)," & "562 (BC_2, *, control, 0)," & "563 (BC_7, LA18_LA18, bidir, X, 562, 0, Z)," & "564 (BC_2, *, control, 0)," & "565 (BC_7, LA17_LA17, bidir, X, 564, 0, Z)," & "566 (BC_2, *, control, 0)," & "567 (BC_7, LA16_LA16, bidir, X, 566, 0, Z)," & "568 (BC_2, *, control, 0)," & "569 (BC_7, LAD15_LAD15, bidir, X, 568, 0, Z)," & "570 (BC_2, *, control, 0)," & "571 (BC_7, LAD14_LAD14, bidir, X, 570, 0, Z)," & "572 (BC_2, *, control, 0)," & "573 (BC_7, LAD13_LAD13, bidir, X, 572, 0, Z)," & "574 (BC_2, *, control, 0)," & "575 (BC_7, LAD12_LAD12, bidir, X, 574, 0, Z)," & "576 (BC_2, *, control, 0)," & "577 (BC_7, LAD11_LAD11, bidir, X, 576, 0, Z)," & "578 (BC_2, *, control, 0)," & "579 (BC_7, LAD10_LAD10, bidir, X, 578, 0, Z)," & "580 (BC_2, *, control, 0)," & "581 (BC_7, LAD9_LAD9, bidir, X, 580, 0, Z)," & "582 (BC_2, *, control, 0)," & "583 (BC_7, LAD8_LAD8, bidir, X, 582, 0, Z)," & "584 (BC_2, *, control, 0)," & "585 (BC_7, LAD7_LAD7, bidir, X, 584, 0, Z)," & "586 (BC_2, *, control, 0)," & "587 (BC_7, LAD6_LAD6, bidir, X, 586, 0, Z)," & "588 (BC_2, *, control, 0)," & "589 (BC_7, LAD5_LAD5, bidir, X, 588, 0, Z)," & "590 (BC_2, *, control, 0)," & "591 (BC_7, LAD4_LAD4, bidir, X, 590, 0, Z)," & "592 (BC_2, *, control, 0)," & "593 (BC_7, LAD3_LAD3, bidir, X, 592, 0, Z)," & "594 (BC_2, *, control, 0)," & "595 (BC_7, LAD2_LAD2, bidir, X, 594, 0, Z)," & "596 (BC_2, *, control, 0)," & "597 (BC_7, LAD1_LAD1, bidir, X, 596, 0, Z)"; end MPC8309;