-- ***************************************************************************** -- BSDL file for design IDT82v2048E -- Created by Synopsys Version 2002.05-SP2 (Nov 15, 2002) -- Company: IDT -- Date: Fri Aug 29 16:34:48 2003 -- ***************************************************************************** entity IDT82v2048E is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "IDT82V2048EDR"); -- This section declares all the ports in the design. port ( IC : in bit; INT_nMOT : in bit; MCLK : in bit; MCLKS : in bit; P_nS : in bit; RST : in bit; SCLK : in bit; SCLKE : in bit; SDI_R_nW_nWR : in bit; TCK : in bit; TCLK1 : in bit; TCLK2 : in bit; TCLK3 : in bit; TCLK4 : in bit; TCLK5 : in bit; TCLK6 : in bit; TCLK7 : in bit; TCLK8 : in bit; TDI : in bit; TDN1 : in bit; TDN2 : in bit; TDN3 : in bit; TDN4 : in bit; TDN5 : in bit; TDN6 : in bit; TDN7 : in bit; TDN8 : in bit; TDP1 : in bit; TDP2 : in bit; TDP3 : in bit; TDP4 : in bit; TDP5 : in bit; TDP6 : in bit; TDP7 : in bit; TDP8 : in bit; THZ : in bit; TMS : in bit; TRST : in bit; nCS : in bit; nDS_nRD : in bit; A : in bit_vector (0 to 7); GPIO0 : inout bit; GPIO1 : inout bit; D : inout bit_vector (0 to 7); INT : out bit; SDO : out bit; TDO : out bit; LOS1 : buffer bit; LOS2 : buffer bit; LOS3 : buffer bit; LOS4 : buffer bit; LOS5 : buffer bit; LOS6 : buffer bit; LOS7 : buffer bit; LOS8 : buffer bit; RCLK1 : buffer bit; RCLK2 : buffer bit; RCLK3 : buffer bit; RCLK4 : buffer bit; RCLK5 : buffer bit; RCLK6 : buffer bit; RCLK7 : buffer bit; RCLK8 : buffer bit; RDN1 : buffer bit; RDN2 : buffer bit; RDN3 : buffer bit; RDN4 : buffer bit; RDN5 : buffer bit; RDN6 : buffer bit; RDN7 : buffer bit; RDN8 : buffer bit; RDP1 : buffer bit; RDP2 : buffer bit; RDP3 : buffer bit; RDP4 : buffer bit; RDP5 : buffer bit; RDP6 : buffer bit; RDP7 : buffer bit; RDP8 : buffer bit; GNDA : linkage bit_vector (1 to 2); GNDD : linkage bit_vector (1 to 2); GNDIO : linkage bit_vector (1 to 5); GNDR1 : linkage bit_vector (1 to 1); GNDR2 : linkage bit_vector (1 to 1); GNDR3 : linkage bit_vector (1 to 1); GNDR4 : linkage bit_vector (1 to 1); GNDR5 : linkage bit_vector (1 to 1); GNDR6 : linkage bit_vector (1 to 1); GNDR7 : linkage bit_vector (1 to 1); GNDR8 : linkage bit_vector (1 to 1); GNDT1 : linkage bit_vector (1 to 2); GNDT2 : linkage bit_vector (1 to 2); GNDT3 : linkage bit_vector (1 to 2); GNDT4 : linkage bit_vector (1 to 2); GNDT5 : linkage bit_vector (1 to 2); GNDT6 : linkage bit_vector (1 to 2); GNDT7 : linkage bit_vector (1 to 2); GNDT8 : linkage bit_vector (1 to 2); NC : linkage bit_vector (1 to 13); VDDA : linkage bit_vector (1 to 2); VDDD : linkage bit_vector (1 to 2); VDDIO : linkage bit_vector (1 to 5); VDDR1 : linkage bit_vector (1 to 1); VDDR2 : linkage bit_vector (1 to 1); VDDR3 : linkage bit_vector (1 to 1); VDDR4 : linkage bit_vector (1 to 1); VDDR5 : linkage bit_vector (1 to 1); VDDR6 : linkage bit_vector (1 to 1); VDDR7 : linkage bit_vector (1 to 1); VDDR8 : linkage bit_vector (1 to 1); VDDT1 : linkage bit_vector (1 to 2); VDDT2 : linkage bit_vector (1 to 2); VDDT3 : linkage bit_vector (1 to 2); VDDT4 : linkage bit_vector (1 to 2); VDDT5 : linkage bit_vector (1 to 2); VDDT6 : linkage bit_vector (1 to 2); VDDT7 : linkage bit_vector (1 to 2); VDDT8 : linkage bit_vector (1 to 2) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of IDT82v2048E: entity is "STD_1149_1_1993"; attribute PIN_MAP of IDT82v2048E: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is -- extracted from the port-to-pin map file that was read in using the -- "read_pin_map" command. constant IDT82V2048EDR: PIN_MAP_STRING := "IC : 13," & "INT_nMOT : 12," & "MCLK : 17," & "MCLKS : 56," & "P_nS : 14," & "RST : 51," & "SCLK : 46," & "SCLKE : 11," & "SDI_R_nW_nWR : 48," & "TCK : 208," & "TCLK1 : 156," & "TCLK2 : 150," & "TCLK3 : 144," & "TCLK4 : 138," & "TCLK5 : 129," & "TCLK6 : 122," & "TCLK7 : 116," & "TCLK8 : 110," & "TDI : 206," & "TDN1 : 154," & "TDN2 : 148," & "TDN3 : 142," & "TDN4 : 136," & "TDN5 : 126," & "TDN6 : 120," & "TDN7 : 114," & "TDN8 : 108," & "TDP1 : 155," & "TDP2 : 149," & "TDP3 : 143," & "TDP4 : 137," & "TDP5 : 127," & "TDP6 : 121," & "TDP7 : 115," & "TDP8 : 109," & "THZ : 10," & "TMS : 205," & "TRST : 204," & "nCS : 45," & "nDS_nRD : 47," & "A : (44, 43, 42, 41, 40, 39, 38, 37)," & "GPIO0 : 54," & "GPIO1 : 53," & "D : (31, 30, 29, 28, 27, 26, 25, 24)," & "INT : 50," & "SDO : 49," & "TDO : 207," & "LOS1 : 1," & "LOS2 : 3," & "LOS3 : 4," & "LOS4 : 5," & "LOS5 : 6," & "LOS6 : 7," & "LOS7 : 8," & "LOS8 : 9," & "RCLK1 : 153," & "RCLK2 : 147," & "RCLK3 : 141," & "RCLK4 : 135," & "RCLK5 : 125," & "RCLK6 : 119," & "RCLK7 : 113," & "RCLK8 : 107," & "RDN1 : 151," & "RDN2 : 145," & "RDN3 : 139," & "RDN4 : 132," & "RDN5 : 123," & "RDN6 : 117," & "RDN7 : 111," & "RDN8 : 105," & "RDP1 : 152," & "RDP2 : 146," & "RDP3 : 140," & "RDP4 : 134," & "RDP5 : 124," & "RDP6 : 118," & "RDP7 : 112," & "RDP8 : 106," & "GNDA : (57, 203)," & "GNDD : (19, 131)," & "GNDIO : (20, 35, 104, 130, 157)," & "GNDR1 : (167)," & "GNDR2 : (174)," & "GNDR3 : (187)," & "GNDR4 : (194)," & "GNDR5 : (67)," & "GNDR6 : (74)," & "GNDR7 : (87)," & "GNDR8 : (94)," & "GNDT1 : (165, 166)," & "GNDT2 : (175, 176)," & "GNDT3 : (185, 186)," & "GNDT4 : (195, 196)," & "GNDT5 : (65, 66)," & "GNDT6 : (75, 76)," & "GNDT7 : (85, 86)," & "GNDT8 : (95, 96)," & "NC : (2, 16, 18, 21, 23, 32, 36, 52, 101, 102, 159, 160, " & "202)," & "VDDA : (60, 201)," & "VDDD : (15, 133)," & "VDDIO : (22, 33, 103, 128, 158)," & "VDDR1 : (170)," & "VDDR2 : (171)," & "VDDR3 : (190)," & "VDDR4 : (191)," & "VDDR5 : (70)," & "VDDR6 : (71)," & "VDDR7 : (90)," & "VDDR8 : (91)," & "VDDT1 : (161, 162)," & "VDDT2 : (179, 180)," & "VDDT3 : (181, 182)," & "VDDT4 : (199, 200)," & "VDDT5 : (61, 62)," & "VDDT6 : (79, 80)," & "VDDT7 : (81, 82)," & "VDDT8 : (99, 100)"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters in -- the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of IDT82v2048E: entity is 3; -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. attribute INSTRUCTION_OPCODE of IDT82v2048E: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "USER1 (011)," & "USER2 (101)," & "USER3 (110)," & "IDCODE (001)," & "USER4 (100)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of IDT82v2048E: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture-DR -- state. attribute IDCODE_REGISTER of IDT82v2048E: entity is "0000" & -- 4-bit version number "0000010011010010" & -- 16-bit part number "00010110011" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. attribute REGISTER_ACCESS of IDT82v2048E: entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST, SAMPLE, USER1, USER2, USER3)," & "DEVICE_ID (IDCODE)," & "UTDR1[2] (USER4)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of IDT82v2048E: entity is 93; -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_REGISTER of IDT82v2048E: entity is -- -- num cell port function safe [ccell disval rslt] -- "92 (BC_1, LOS1, output2, X), " & "91 (BC_1, LOS2, output2, X), " & "90 (BC_1, LOS3, output2, X), " & "89 (BC_1, LOS4, output2, X), " & "88 (BC_1, LOS5, output2, X), " & "87 (BC_1, LOS6, output2, X), " & "86 (BC_1, LOS7, output2, X), " & "85 (BC_1, LOS8, output2, X), " & "84 (BC_3, THZ, input, X), " & "83 (BC_3, SCLKE, input, X), " & "82 (BC_3, INT_nMOT, input, X), " & "81 (BC_3, IC, input, X), " & "80 (BC_3, P_nS, input, X), " & "79 (BC_3, MCLK, input, X), " & "78 (BC_7, D(7), bidir, X, 70, 1, Z), " & "77 (BC_7, D(6), bidir, X, 70, 1, Z), " & "76 (BC_7, D(5), bidir, X, 70, 1, Z), " & "75 (BC_7, D(4), bidir, X, 70, 1, Z), " & "74 (BC_7, D(3), bidir, X, 70, 1, Z), " & "73 (BC_7, D(2), bidir, X, 70, 1, Z), " & "72 (BC_7, D(1), bidir, X, 70, 1, Z), " & "71 (BC_7, D(0), bidir, X, 70, 1, Z), " & "70 (BC_1, *, control, 1), " & "69 (BC_3, A(7), input, X), " & "68 (BC_3, A(6), input, X), " & "67 (BC_3, A(5), input, X), " & "66 (BC_3, A(4), input, X), " & "65 (BC_3, A(3), input, X), " & "64 (BC_3, A(2), input, X), " & "63 (BC_3, A(1), input, X), " & "62 (BC_3, A(0), input, X), " & "61 (BC_3, nCS, input, X), " & "60 (BC_3, SCLK, input, X), " & "59 (BC_3, nDS_nRD, input, X), " & "58 (BC_3, SDI_R_nW_nWR, input, X), " & "57 (BC_1, SDO, output3, X, 56, 1, Z), " & "56 (BC_1, *, control, 1), " & "55 (BC_1, INT, output3, X, 54, 1, Z), " & "54 (BC_1, *, control, 1), " & "53 (BC_3, RST, input, X), " & "52 (BC_7, GPIO1, bidir, X, 51, 1, Z), " & "51 (BC_1, *, control, 1), " & "50 (BC_7, GPIO0, bidir, X, 49, 1, Z), " & "49 (BC_1, *, control, 1), " & "48 (BC_3, MCLKS, input, X), " & "47 (BC_1, RDN8, output2, X), " & "46 (BC_1, RDP8, output2, X), " & "45 (BC_1, RCLK8, output2, X), " & "44 (BC_3, TDN8, input, X), " & "43 (BC_3, TDP8, input, X), " & "42 (BC_3, TCLK8, input, X), " & "41 (BC_1, RDN7, output2, X), " & "40 (BC_1, RDP7, output2, X), " & "39 (BC_1, RCLK7, output2, X), " & "38 (BC_3, TDN7, input, X), " & "37 (BC_3, TDP7, input, X), " & "36 (BC_3, TCLK7, input, X), " & "35 (BC_1, RDN6, output2, X), " & "34 (BC_1, RDP6, output2, X), " & "33 (BC_1, RCLK6, output2, X), " & "32 (BC_3, TDN6, input, X), " & "31 (BC_3, TDP6, input, X), " & "30 (BC_3, TCLK6, input, X), " & "29 (BC_1, RDN5, output2, X), " & "28 (BC_1, RDP5, output2, X), " & "27 (BC_1, RCLK5, output2, X), " & "26 (BC_3, TDN5, input, X), " & "25 (BC_3, TDP5, input, X), " & "24 (BC_3, TCLK5, input, X), " & "23 (BC_1, RDN4, output2, X), " & "22 (BC_1, RDP4, output2, X), " & "21 (BC_1, RCLK4, output2, X), " & "20 (BC_3, TDN4, input, X), " & "19 (BC_3, TDP4, input, X), " & "18 (BC_3, TCLK4, input, X), " & "17 (BC_1, RDN3, output2, X), " & "16 (BC_1, RDP3, output2, X), " & "15 (BC_1, RCLK3, output2, X), " & "14 (BC_3, TDN3, input, X), " & "13 (BC_3, TDP3, input, X), " & "12 (BC_3, TCLK3, input, X), " & "11 (BC_1, RDN2, output2, X), " & "10 (BC_1, RDP2, output2, X), " & "9 (BC_1, RCLK2, output2, X), " & "8 (BC_3, TDN2, input, X), " & "7 (BC_3, TDP2, input, X), " & "6 (BC_3, TCLK2, input, X), " & "5 (BC_1, RDN1, output2, X), " & "4 (BC_1, RDP1, output2, X), " & "3 (BC_1, RCLK1, output2, X), " & "2 (BC_3, TDN1, input, X), " & "1 (BC_3, TDP1, input, X), " & "0 (BC_3, TCLK1, input, X) "; end IDT82v2048E;