-- Generated by Intel Corportion on 09/11/00 -- Chip Version LXT388LE_B2 entity LXT388 is generic (PHYSICAL_PIN_MAP : string := "LXT388"); port ( -- Port List RTIP : linkage bit_vector( 3 downto 0 ); RRING : linkage bit_vector( 3 downto 0 ); TTIP : linkage bit_vector( 3 downto 0 ); TRING : linkage bit_vector( 3 downto 0 ); TVCC : linkage bit_vector( 3 downto 0 ); TGND : linkage bit_vector( 3 downto 0 ); VCC : linkage bit_vector( 6 downto 0 ); GND : linkage bit_vector( 6 downto 0 ); NC : linkage bit; AT1 : linkage bit; AT2 : linkage bit; LOOP0 : inout bit; LOOP1 : inout bit; LOOP2 : inout bit; LOOP3 : inout bit; LOOP4 : inout bit; LOOP5 : inout bit; LOOP6 : inout bit; LOOP7 : inout bit; TCLK1 : in bit; TPOS1 : in bit; TNEG1 : in bit; RCLK1 : out bit; RPOS1 : out bit; RNEG1 : out bit; LOS1 : buffer bit; TCLK0 : in bit; TPOS0 : in bit; TNEG0 : in bit; RCLK0 : out bit; RPOS0 : out bit; RNEG0 : out bit; LOS0 : buffer bit; MUX : in bit; LOS3 : buffer bit; RNEG3 : out bit; RPOS3 : out bit; RCLK3 : out bit; TNEG3 : in bit; TPOS3 : in bit; TCLK3 : in bit; LOS2 : buffer bit; RNEG2 : out bit; RPOS2 : out bit; RCLK2 : out bit; TNEG2 : in bit; TPOS2 : in bit; TCLK2 : in bit; INT : buffer bit; ACK : out bit; WRB : in bit; RDB : in bit; ALE : in bit; CSB : in bit; IMB : in bit; OE : in bit; CLKE : in bit; MCLK : in bit; MODE : in bit; A4 : in bit; A3 : in bit; A2 : in bit; A1 : in bit; A0 : in bit; TRST : in bit; TDO : out bit; TCK : in bit; TMS : in bit; TDI : in bit; RESET : in bit ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of LXT388: entity is "STD_1149_1_1993"; -- Pin mappings attribute PIN_MAP of LXT388: entity is PHYSICAL_PIN_MAP; constant LXT388: PIN_MAP_STRING:= "RTIP : (30, 37, 42, 49), " & "RRING : (31, 36, 43, 48), " & "TTIP : (27, 34, 39, 46), " & "TRING : (28, 33, 40, 45), " & "TVCC : (26, 35, 38, 47), " & "TGND : (29, 32, 41, 44), " & "VCC : (4, 6, 8, 9, 67, 68, 75 ), " & "GND : (5, 7, 10, 11, 65, 66, 74), " & "NC : 50 , " & "AT1 : 77 , " & "AT2 : 76 , " & "IMB : 1 , " & "RDB : 2 , " & "WRB : 3 , " & "TCLK1 : 12 , " & "TPOS1 : 13 , " & "TNEG1 : 14 , " & "RCLK1 : 15 , " & "RPOS1 : 16 , " & "RNEG1 : 17 , " & "LOS1 : 18 , " & "TCLK0 : 19 , " & "TPOS0 : 20 , " & "TNEG0 : 21 , " & "RCLK0 : 22 , " & "RPOS0 : 23 , " & "RNEG0 : 24 , " & "LOS0 : 25 , " & "LOS3 : 51 , " & "RNEG3 : 52 , " & "RPOS3 : 53 , " & "RCLK3 : 54 , " & "TNEG3 : 55 , " & "TPOS3 : 56 , " & "TCLK3 : 57 , " & "LOS2 : 58 , " & "RNEG2 : 59 , " & "RPOS2 : 60 , " & "RCLK2 : 61 , " & "TNEG2 : 62 , " & "TPOS2 : 63 , " & "TCLK2 : 64 , " & "MCLK : 78 , " & "MODE : 79 , " & "INT : 80 , " & "ACK : 81 , " & "ALE : 82 , " & "OE : 83 , " & "CLKE : 84 , " & "A0 : 85 , " & "A1 : 86 , " & "A2 : 87 , " & "A3 : 88 , " & "A4 : 89 , " & "LOOP0 : 90 , " & "LOOP1 : 91 , " & "LOOP2 : 92 , " & "LOOP3 : 93 , " & "LOOP4 : 94 , " & "LOOP5 : 95 , " & "LOOP6 : 96 , " & "LOOP7 : 97 , " & "CSB : 98 , " & "MUX : 99 , " & "RESET : 100 , " & "TRST : 72 , " & "TDO : 73 , " & "TCK : 69 , " & "TMS : 71 , " & "TDI : 70 " ; -- IEEE 1149.1 pin definition attribute TAP_SCAN_RESET of TRST: signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (5.0e6, BOTH); -- IEEE 1149.1 instruction register attribute INSTRUCTION_LENGTH of LXT388: entity is 3; attribute INSTRUCTION_OPCODE of LXT388: entity is "EXTEST (000)," & "INTEST (010)," & "SAMPLE (100)," & -- was 001 "IDCODE (110)," & -- was 011 "BYPASS (111)" ; attribute INSTRUCTION_CAPTURE of LXT388: entity is "X01"; attribute IDCODE_REGISTER of LXT388: entity is "0010" & -- version "0000000110000010" & -- part number "00001111110" & -- manufacturer's identity "1"; -- required by 1149.1 -- Boundary scan definition -- Cell 0 is closest to TDO attribute BOUNDARY_LENGTH of LXT388: entity is 68; attribute BOUNDARY_REGISTER of LXT388: entity is -- num cell signalName function safe ccell disval rslt " 67 (BC_1 , LOS0 , output2 , X )," & " 66 (BC_1 , RNEG0 , output3 , X, 65, 1, Z )," & " 65 (BC_1 , * , control , 1 )," & " 64 (BC_1 , RPOS0 , output3 , X, 65, 1, Z )," & " 63 (BC_1 , RCLK0 , output3 , X, 65, 1, Z )," & " 62 (BC_1 , TNEG0 , input , X )," & " 61 (BC_1 , TPOS0 , input , X )," & " 60 (BC_1 , TCLK0 , input , X )," & " 59 (BC_1 , LOS1 , output2 , X )," & " 58 (BC_1 , RNEG1 , output3 , X, 57, 1, Z )," & " 57 (BC_1 , * , control , 1 )," & " 56 (BC_1 , RPOS1 , output3 , X, 57, 1, Z )," & " 55 (BC_1 , RCLK1 , output3 , X, 57, 1, Z )," & " 54 (BC_1 , TNEG1 , input , X )," & " 53 (BC_1 , TPOS1 , input , X )," & " 52 (BC_1 , TCLK1 , input , X )," & " 51 (BC_1 , WRB , input , X )," & " 50 (BC_1 , RDB , input , X )," & " 49 (BC_1 , IMB , input , X )," & " 48 (BC_1 , RESET , input , X )," & " 47 (BC_1 , MUX , input , X )," & " 46 (BC_1 , CSB , input , X )," & " 45 (BC_1 , LOOP7 , output3 , X, 44, 1, Z )," & " 44 (BC_1 , * , control , 1 )," & " 43 (BC_1 , LOOP7 , input , X )," & " 42 (BC_1 , LOOP6 , output3 , X, 44, 1, Z )," & " 41 (BC_1 , LOOP6 , input , X )," & " 40 (BC_1 , LOOP5 , output3 , X, 44, 1, Z )," & " 39 (BC_1 , LOOP5 , input , X )," & " 38 (BC_1 , LOOP4 , output3 , X, 44, 1, Z )," & " 37 (BC_1 , LOOP4 , input , X )," & " 36 (BC_1 , LOOP3 , output3 , X, 44, 1, Z )," & " 35 (BC_1 , LOOP3 , input , X )," & " 34 (BC_1 , LOOP2 , output3 , X, 44, 1, Z )," & " 33 (BC_1 , LOOP2 , input , X )," & " 32 (BC_1 , LOOP1 , output3 , X, 44, 1, Z )," & " 31 (BC_1 , LOOP1 , input , X )," & " 30 (BC_1 , LOOP0 , output3 , X, 44, 1, Z )," & " 29 (BC_1 , LOOP0 , input , X )," & " 28 (BC_1 , A4 , input , X )," & " 27 (BC_1 , A3 , input , X )," & " 26 (BC_1 , A2 , input , X )," & " 25 (BC_1 , A1 , input , X )," & " 24 (BC_1 , A0 , input , X )," & " 23 (BC_1 , CLKE , input , X )," & " 22 (BC_1 , OE , input , X )," & " 21 (BC_1 , ALE , input , X )," & " 20 (BC_1 , ACK , output3 , X, 19, 1, Z )," & " 19 (BC_1 , * , control , 1 )," & " 18 (BC_1 , INT , output2 , X )," & " 17 (BC_1 , MODE , input , X )," & " 16 (BC_1 , MCLK , input , X )," & " 15 (BC_1 , TCLK2 , input , X )," & " 14 (BC_1 , TPOS2 , input , X )," & " 13 (BC_1 , TNEG2 , input , X )," & " 12 (BC_1 , RCLK2 , output3 , X, 10, 1, Z )," & " 11 (BC_1 , RPOS2 , output3 , X, 10, 1, Z )," & " 10 (BC_1 , * , control , 1 )," & " 9 (BC_1 , RNEG2 , output3 , X, 10, 1, Z )," & " 8 (BC_1 , LOS2 , output2 , X )," & " 7 (BC_1 , TCLK3 , input , X )," & " 6 (BC_1 , TPOS3 , input , X )," & " 5 (BC_1 , TNEG3 , input , X )," & " 4 (BC_1 , RCLK3 , output3 , X, 2, 1, Z )," & " 3 (BC_1 , RPOS3 , output3 , X, 2, 1, Z )," & " 2 (BC_1 , * , control , 1 )," & " 1 (BC_1 , RNEG3 , output3 , X, 2, 1, Z )," & " 0 (BC_1 , LOS3 , output2 , X )"; end LXT388;