-------------------------------------------------------- -- BSDL for ADSP_BF535 Digital Signal Processor -- -- -- Revision: 0.0 -- Date: 2001/03/28 -- -- Revision: 1.0 -- Date: 2002/06/28 -- -- -------------------------------------------------------- entity ADSP_21535 is generic (PHYSICAL_PIN_MAP : string:="UNDEFINED"); port( ADDR: out bit_vector(2 to 25); DATA: inout bit_vector(0 to 31); EMU_B: out bit; BYPASS: in bit; SLEEP: out bit; BMODE: in bit_vector(0 to 2); PCI_INTD: in bit; PCI_INTC: in bit; PCI_INTB: in bit; PCI_INTA: inout bit; PCI_CLK: in bit; PCI_LOCK: in bit; PCI_SERR: inout bit; PCI_PAR: inout bit; PCI_PERR: inout bit; PCI_STOP: inout bit; PCI_DEVSEL: inout bit; PCI_TRDY: inout bit; PCI_FRAME: inout bit; PCI_IDSEL: in bit; PCI_GNT: in bit; PCI_REQ: out bit; PCI_RST: inout bit; PCI_IRDY: inout bit; PCI_CBE: inout bit_vector(0 to 3); PCI_AD: inout bit_vector(0 to 31); SCK1: inout bit; MISO1: inout bit; MOSI1: inout bit; SCK0: inout bit; MISO0: inout bit; MOSI0: inout bit; DT1: out bit; TFS1: inout bit; TSCLK1: inout bit; DR1: in bit; RFS1: inout bit; RSCLK1: inout bit; DT0: out bit; TFS0: inout bit; TSCLK0: inout bit; DR0: in bit; RFS0: inout bit; RSCLK0: inout bit; PF: inout bit_vector(0 to 15); ARDY: in bit; SCAS_B: out bit; SMS_B: out bit_vector(0 to 3); SWE_B: out bit; SRAS_B: out bit; SA10: out bit; SCKE: out bit; SCLK0: buffer bit; CLKOUT_SCLK1: buffer bit; AWE_B: out bit; ARE_B: out bit; AOE_B: out bit; AMS_B: out bit_vector(0 to 3); ABE_B_SDQM: out bit_vector(0 to 3); TMR: inout bit_vector(0 to 2); RX0: in bit; TX0: out bit; RX1: in bit; TX1: out bit; USB_CLK: in bit; XVER_DATA: in bit; RESET_B: in bit; DPLS: in bit; DMNS: in bit; TXDPLS: out bit; TXDMNS: out bit; TXEN: out bit; SUSPEND: out bit; NMI: in bit; TCK: in bit; TMS: in bit; TDI: in bit; TDO: out bit; TRST_B: in bit; CLKIN1: linkage bit; XTALI: linkage bit; XTALO: linkage bit; GND: linkage bit_vector(0 to 25); NC: linkage bit_vector(0 to 3); VDDEXT: linkage bit_vector(0 to 9); VDDINT: linkage bit_vector(0 to 12); VDDPCIEXT: linkage bit_vector(0 to 4); VDDPLL: linkage bit; VDDRTC: linkage bit; VSSPLL: linkage bit; VSSRTC: linkage bit); use STD_1149_1_1990.all; attribute PIN_MAP of ADSP_21535: entity is PHYSICAL_PIN_MAP; constant PBGA_PACKAGE: PIN_MAP_STRING:= "ADDR: (A6,B6,D6,C6,A5,B5,A4,C5,D5,B4,A1,C4,D4," & "A3,B3,A2,C3,D3,B2,C2,E3,C1,F3,D2)," & "DATA: (N2,M3,T1,P2,N3,R2,P3,U1,U2,T2,V2,V3," & "R4,U3,T3,T4,U4,V4,V5,R5,T5,U5,V6,R6," & "U6,T6,V7,V8,U7,R7,T7,V9)," & "EMU_B: A13," & "BYPASS: C12," & "SLEEP: D12," & "BMODE: (B14,A14,B13)," & "PCI_INTD: D13," & "PCI_INTC: A15," & "PCI_INTB: B15," & "PCI_INTA: C14," & "PCI_CLK: D14," & "PCI_LOCK: A16," & "PCI_SERR: B16," & "PCI_PAR: C15," & "PCI_PERR: D15," & "PCI_STOP: A17," & "PCI_DEVSEL: C16," & "PCI_TRDY: B17," & "PCI_FRAME: C17," & "PCI_IDSEL: B18," & "PCI_GNT: C18," & "PCI_REQ: D16," & "PCI_RST: D18," & "PCI_IRDY: E15," & "PCI_CBE: (F16,F15,E16,D17)," & "PCI_AD: (E17,E18,G16,F17,F18,G18,G17,H18,J18,H17,K18,H16,L18," & "J17,M18,K17,J16,K16,N18,P18,L17,L16,R18,T18," & "M17,M16,N17,P17,P15,N16,R17,P16)," & "SCK1: R16," & "MISO1: U18," & "MOSI1: T17," & "SCK0: U17," & "MISO0: T16," & "MOSI0: U16," & "DT1: V17," & "TFS1: R15," & "TSCLK1: T15," & "DR1: U15," & "RFS1: V16," & "RSCLK1: U14," & "DT0: R14," & "TFS0: T14," & "TSCLK0: V15," & "DR0: V14," & "RFS0: U13," & "RSCLK0: R13," & "PF: (U8,R8,T8,V10,U9,R9,T9,R11,T11,U11,V12,T12,R12," & "U12,V13,T13)," & "ARDY: R1," & "SCAS_B: L3," & "SMS_B: (M2,P1,N1,K3)," & "SWE_B: J3," & "SRAS_B: L2," & "SA10: M1," & "SCKE: L1," & "SCLK0: K1," & "CLKOUT_SCLK1: H1," & "AWE_B: G1," & "ARE_B: F1," & "AOE_B: E1," & "AMS_B: (F2,D1,H3,G2)," & "ABE_B_SDQM: (E2,B1,G3,H7)," & "TMR: (B7,C7,D7)," & "RX0: A7," & "TX0: A8," & "RX1: B8," & "TX1: C8," & "USB_CLK: G7," & "XVER_DATA: A9," & "RESET_B: B9," & "DPLS: C9," & "DMNS: D8," & "TXDPLS: B10," & "TXDMNS: G10," & "TXEN: C10," & "SUSPEND: A11," & "NMI: B11," & "TCK: D10," & "TRST_B: B12," & "TDO: D11," & "TDI: C11," & "TMS: A12," & "CLKIN1: D9," & "XTALI: R10," & "XTALO: T10," & "GND: (C13,H2,H8,H10,H11,J7,J8,J9," & "J10,J11,J12,K2,K7,K8,K9,K10,K11,K12," & "L7,L8,L9,L10,L11,M7,M9,M10)," & "NC: (A18,R3,V1,V18)," & "VDDEXT: (E4,G4,G8,J1,J2,J4,K4,L4,M4,P4)," & "VDDINT: (F4,G11,G12,G15,H4,H9,H12,L12,M8,M11,M12,N4,N15)," & "VDDPCIEXT: (H15,J15,K15,L15,M15)," & "VDDPLL: G9," & "VDDRTC: U10," & "VSSPLL: A10," & "VSSRTC: V11"; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_21535: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_21535: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (10000)," & "IDCODE (00010)," & "MEMTEST (00001,00111,01001,01011,01101)," & "REPAIR (01010,10011,01100,10101)," & "CLK_ADJ (10001)," & "EMULATION (00100,10100,01000,11110)"; attribute INSTRUCTION_CAPTURE of ADSP_21535: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_21535: entity is "EMULATION," & "REPAIR," & "CLK_ADJ," & "MEMTEST"; attribute IDCODE_REGISTER of ADSP_21535: entity is "0000" & -- Version "0100000000000001" & -- Part number "00001100101" & -- ADI manufacturing code "1"; -- Required bit attribute BOUNDARY_CELLS of ADSP_21535: entity is "BC_1, BC_2, BC_3, BC_4"; -- BC_1: output, control; BC_2: input; BC_3: internal; BC_4: clock; attribute BOUNDARY_LENGTH of ADSP_21535: entity is 469; attribute BOUNDARY_REGISTER of ADSP_21535: entity is --num cell port function safe [ccell disval rslt ] " 0 ( BC_2 , NMI , input , X ) , " & " 1 ( BC_1 , SUSPEND , output3 , X , 2 , 0 , Z ) , " & " 2 ( BC_1 , * , control , 0 ) , " & " 3 ( BC_1 , TXEN , output3 , X , 4 , 0 , Z ) , " & " 4 ( BC_1 , * , control , 0 ) , " & " 5 ( BC_1 , TXDMNS , output3 , X , 6 , 0 , Z ) , " & " 6 ( BC_1 , * , control , 0 ) , " & " 7 ( BC_1 , TXDPLS , output3 , X , 8 , 0 , Z ) , " & " 8 ( BC_1 , * , control , 0 ) , " & " 9 ( BC_2 , DMNS , input , X ) , " & " 10 ( BC_2 , DPLS , input , X ) , " & " 11 ( BC_2 , RESET_B , input , X ) , " & " 12 ( BC_2 , XVER_DATA , input , X ) , " & " 13 ( BC_2 , USB_CLK , input , X ) , " & " 14 ( BC_1 , TX1 , output3 , X , 15 , 0 , Z ) , " & " 15 ( BC_1 , * , control , 0 ) , " & " 16 ( BC_2 , RX1 , input , X ) , " & " 17 ( BC_1 , TX0 , output3 , X , 18 , 0 , Z ) , " & " 18 ( BC_1 , * , control , 0 ) , " & " 19 ( BC_2 , RX0 , input , X ) , " & " 20 ( BC_1 , TMR(2) , output3 , X , 21 , 0 , Z ) , " & " 21 ( BC_1 , * , control , 0 ) , " & " 22 ( BC_2 , TMR(2) , input , X ) , " & " 23 ( BC_1 , TMR(1) , output3 , X , 24 , 0 , Z ) , " & " 24 ( BC_1 , * , control , 0 ) , " & " 25 ( BC_2 , TMR(1) , input , X ) , " & " 26 ( BC_1 , TMR(0) , output3 , X , 27 , 0 , Z ) , " & " 27 ( BC_1 , * , control , 0 ) , " & " 28 ( BC_2 , TMR(0) , input , X ) , " & " 29 ( BC_1 , ADDR(2) , output3 , X , 30 , 0 , Z ) , " & " 30 ( BC_1 , * , control , 0 ) , " & " 31 ( BC_1 , ADDR(3) , output3 , X , 32 , 0 , Z ) , " & " 32 ( BC_1 , * , control , 0 ) , " & " 33 ( BC_1 , ADDR(4) , output3 , X , 34 , 0 , Z ) , " & " 34 ( BC_1 , * , control , 0 ) , " & " 35 ( BC_1 , ADDR(5) , output3 , X , 36 , 0 , Z ) , " & " 36 ( BC_1 , * , control , 0 ) , " & " 37 ( BC_1 , ADDR(6) , output3 , X , 38 , 0 , Z ) , " & " 38 ( BC_1 , * , control , 0 ) , " & " 39 ( BC_1 , ADDR(7) , output3 , X , 40 , 0 , Z ) , " & " 40 ( BC_1 , * , control , 0 ) , " & " 41 ( BC_1 , ADDR(8) , output3 , X , 42 , 0 , Z ) , " & " 42 ( BC_1 , * , control , 0 ) , " & " 43 ( BC_1 , ADDR(9) , output3 , X , 44 , 0 , Z ) , " & " 44 ( BC_1 , * , control , 0 ) , " & " 45 ( BC_1 , ADDR(10) , output3 , X , 46 , 0 , Z ) , " & " 46 ( BC_1 , * , control , 0 ) , " & " 47 ( BC_1 , ADDR(11) , output3 , X , 48 , 0 , Z ) , " & " 48 ( BC_1 , * , control , 0 ) , " & " 49 ( BC_1 , ADDR(12) , output3 , X , 50 , 0 , Z ) , " & " 50 ( BC_1 , * , control , 0 ) , " & " 51 ( BC_1 , ADDR(13) , output3 , X , 52 , 0 , Z ) , " & " 52 ( BC_1 , * , control , 0 ) , " & " 53 ( BC_1 , ADDR(14) , output3 , X , 54 , 0 , Z ) , " & " 54 ( BC_1 , * , control , 0 ) , " & " 55 ( BC_1 , ADDR(15) , output3 , X , 56 , 0 , Z ) , " & " 56 ( BC_1 , * , control , 0 ) , " & " 57 ( BC_1 , ADDR(16) , output3 , X , 58 , 0 , Z ) , " & " 58 ( BC_1 , * , control , 0 ) , " & " 59 ( BC_1 , ADDR(17) , output3 , X , 60 , 0 , Z ) , " & " 60 ( BC_1 , * , control , 0 ) , " & " 61 ( BC_1 , ADDR(18) , output3 , X , 62 , 0 , Z ) , " & " 62 ( BC_1 , * , control , 0 ) , " & " 63 ( BC_1 , ADDR(19) , output3 , X , 64 , 0 , Z ) , " & " 64 ( BC_1 , * , control , 0 ) , " & " 65 ( BC_1 , ADDR(20) , output3 , X , 66 , 0 , Z ) , " & " 66 ( BC_1 , * , control , 0 ) , " & " 67 ( BC_1 , ADDR(21) , output3 , X , 68 , 0 , Z ) , " & " 68 ( BC_1 , * , control , 0 ) , " & " 69 ( BC_1 , ADDR(22) , output3 , X , 70 , 0 , Z ) , " & " 70 ( BC_1 , * , control , 0 ) , " & " 71 ( BC_1 , ADDR(23) , output3 , X , 72 , 0 , Z ) , " & " 72 ( BC_1 , * , control , 0 ) , " & " 73 ( BC_1 , ADDR(24) , output3 , X , 74 , 0 , Z ) , " & " 74 ( BC_1 , * , control , 0 ) , " & " 75 ( BC_1 , ADDR(25) , output3 , X , 76 , 0 , Z ) , " & " 76 ( BC_1 , * , control , 0 ) , " & " 77 ( BC_1 , ABE_B_SDQM(0) , output3 , X , 78 , 0 , Z ) , " & " 78 ( BC_1 , * , control , 0 ) , " & " 79 ( BC_1 , ABE_B_SDQM(1) , output3 , X , 80 , 0 , Z ) , " & " 80 ( BC_1 , * , control , 0 ) , " & " 81 ( BC_1 , ABE_B_SDQM(2) , output3 , X , 82 , 0 , Z ) , " & " 82 ( BC_1 , * , control , 0 ) , " & " 83 ( BC_1 , ABE_B_SDQM(3) , output3 , X , 84 , 0 , Z ) , " & " 84 ( BC_1 , * , control , 0 ) , " & " 85 ( BC_1 , AMS_B(0) , output3 , X , 86 , 0 , Z ) , " & " 86 ( BC_1 , * , control , 0 ) , " & " 87 ( BC_1 , AMS_B(1) , output3 , X , 88 , 0 , Z ) , " & " 88 ( BC_1 , * , control , 0 ) , " & " 89 ( BC_1 , AMS_B(2) , output3 , X , 90 , 0 , Z ) , " & " 90 ( BC_1 , * , control , 0 ) , " & " 91 ( BC_1 , AMS_B(3) , output3 , X , 92 , 0 , Z ) , " & " 92 ( BC_1 , * , control , 0 ) , " & " 93 ( BC_1 , AOE_B , output3 , X , 94 , 0 , Z ) , " & " 94 ( BC_1 , * , control , 0 ) , " & " 95 ( BC_1 , ARE_B , output3 , X , 96 , 0 , Z ) , " & " 96 ( BC_1 , * , control , 0 ) , " & " 97 ( BC_1 , AWE_B , output3 , X , 98 , 0 , Z ) , " & " 98 ( BC_1 , * , control , 0 ) , " & " 99 ( BC_1 , CLKOUT_SCLK1 , output2 , X ) , " & " 100 ( BC_1 , * , internal , 1 ) , " & " 101 ( BC_1 , SCLK0 , output2 , X ) , " & " 102 ( BC_1 , * , internal , 1 ) , " & " 103 ( BC_1 , SCKE , output3 , X , 104 , 0 , Z ) , " & " 104 ( BC_1 , * , control , 0 ) , " & " 105 ( BC_1 , SA10 , output3 , X , 106 , 0 , Z ) , " & " 106 ( BC_1 , * , control , 0 ) , " & " 107 ( BC_1 , SRAS_B , output3 , X , 108 , 0 , Z ) , " & " 108 ( BC_1 , * , control , 0 ) , " & " 109 ( BC_1 , SWE_B , output3 , X , 110 , 0 , Z ) , " & " 110 ( BC_1 , * , control , 0 ) , " & " 111 ( BC_1 , SMS_B(3) , output3 , X , 112 , 0 , Z ) , " & " 112 ( BC_1 , * , control , 0 ) , " & " 113 ( BC_1 , SMS_B(2) , output3 , X , 114 , 0 , Z ) , " & " 114 ( BC_1 , * , control , 0 ) , " & " 115 ( BC_1 , SMS_B(1) , output3 , X , 116 , 0 , Z ) , " & " 116 ( BC_1 , * , control , 0 ) , " & " 117 ( BC_1 , SMS_B(0) , output3 , X , 118 , 0 , Z ) , " & " 118 ( BC_1 , * , control , 0 ) , " & " 119 ( BC_1 , SCAS_B , output3 , X , 120 , 0 , Z ) , " & " 120 ( BC_1 , * , control , 0 ) , " & " 121 ( BC_2 , ARDY , input , X ) , " & " 122 ( BC_1 , DATA(0) , output3 , X , 123 , 0 , Z ) , " & " 123 ( BC_1 , * , control , 0 ) , " & " 124 ( BC_2 , DATA(0) , input , X ) , " & " 125 ( BC_1 , DATA(1) , output3 , X , 126 , 0 , Z ) , " & " 126 ( BC_1 , * , control , 0 ) , " & " 127 ( BC_2 , DATA(1) , input , X ) , " & " 128 ( BC_1 , DATA(2) , output3 , X , 129 , 0 , Z ) , " & " 129 ( BC_1 , * , control , 0 ) , " & " 130 ( BC_2 , DATA(2) , input , X ) , " & " 131 ( BC_1 , DATA(3) , output3 , X , 132 , 0 , Z ) , " & " 132 ( BC_1 , * , control , 0 ) , " & " 133 ( BC_2 , DATA(3) , input , X ) , " & " 134 ( BC_1 , DATA(4) , output3 , X , 135 , 0 , Z ) , " & " 135 ( BC_1 , * , control , 0 ) , " & " 136 ( BC_2 , DATA(4) , input , X ) , " & " 137 ( BC_1 , DATA(5) , output3 , X , 138 , 0 , Z ) , " & " 138 ( BC_1 , * , control , 0 ) , " & " 139 ( BC_2 , DATA(5) , input , X ) , " & " 140 ( BC_1 , DATA(6) , output3 , X , 141 , 0 , Z ) , " & " 141 ( BC_1 , * , control , 0 ) , " & " 142 ( BC_2 , DATA(6) , input , X ) , " & " 143 ( BC_1 , DATA(7) , output3 , X , 144 , 0 , Z ) , " & " 144 ( BC_1 , * , control , 0 ) , " & " 145 ( BC_2 , DATA(7) , input , X ) , " & " 146 ( BC_1 , DATA(8) , output3 , X , 147 , 0 , Z ) , " & " 147 ( BC_1 , * , control , 0 ) , " & " 148 ( BC_2 , DATA(8) , input , X ) , " & " 149 ( BC_1 , DATA(9) , output3 , X , 150 , 0 , Z ) , " & " 150 ( BC_1 , * , control , 0 ) , " & " 151 ( BC_2 , DATA(9) , input , X ) , " & " 152 ( BC_1 , DATA(10) , output3 , X , 153 , 0 , Z ) , " & " 153 ( BC_1 , * , control , 0 ) , " & " 154 ( BC_2 , DATA(10) , input , X ) , " & " 155 ( BC_1 , DATA(11) , output3 , X , 156 , 0 , Z ) , " & " 156 ( BC_1 , * , control , 0 ) , " & " 157 ( BC_2 , DATA(11) , input , X ) , " & " 158 ( BC_1 , DATA(12) , output3 , X , 159 , 0 , Z ) , " & " 159 ( BC_1 , * , control , 0 ) , " & " 160 ( BC_2 , DATA(12) , input , X ) , " & " 161 ( BC_1 , DATA(13) , output3 , X , 162 , 0 , Z ) , " & " 162 ( BC_1 , * , control , 0 ) , " & " 163 ( BC_2 , DATA(13) , input , X ) , " & " 164 ( BC_1 , DATA(14) , output3 , X , 165 , 0 , Z ) , " & " 165 ( BC_1 , * , control , 0 ) , " & " 166 ( BC_2 , DATA(14) , input , X ) , " & " 167 ( BC_1 , DATA(15) , output3 , X , 168 , 0 , Z ) , " & " 168 ( BC_1 , * , control , 0 ) , " & " 169 ( BC_2 , DATA(15) , input , X ) , " & " 170 ( BC_1 , DATA(16) , output3 , X , 171 , 0 , Z ) , " & " 171 ( BC_1 , * , control , 0 ) , " & " 172 ( BC_2 , DATA(16) , input , X ) , " & " 173 ( BC_1 , DATA(17) , output3 , X , 174 , 0 , Z ) , " & " 174 ( BC_1 , * , control , 0 ) , " & " 175 ( BC_2 , DATA(17) , input , X ) , " & " 176 ( BC_1 , DATA(18) , output3 , X , 177 , 0 , Z ) , " & " 177 ( BC_1 , * , control , 0 ) , " & " 178 ( BC_2 , DATA(18) , input , X ) , " & " 179 ( BC_1 , DATA(19) , output3 , X , 180 , 0 , Z ) , " & " 180 ( BC_1 , * , control , 0 ) , " & " 181 ( BC_2 , DATA(19) , input , X ) , " & " 182 ( BC_1 , DATA(20) , output3 , X , 183 , 0 , Z ) , " & " 183 ( BC_1 , * , control , 0 ) , " & " 184 ( BC_2 , DATA(20) , input , X ) , " & " 185 ( BC_1 , DATA(21) , output3 , X , 186 , 0 , Z ) , " & " 186 ( BC_1 , * , control , 0 ) , " & " 187 ( BC_2 , DATA(21) , input , X ) , " & " 188 ( BC_1 , DATA(22) , output3 , X , 189 , 0 , Z ) , " & " 189 ( BC_1 , * , control , 0 ) , " & " 190 ( BC_2 , DATA(22) , input , X ) , " & " 191 ( BC_1 , DATA(23) , output3 , X , 192 , 0 , Z ) , " & " 192 ( BC_1 , * , control , 0 ) , " & " 193 ( BC_2 , DATA(23) , input , X ) , " & " 194 ( BC_1 , DATA(24) , output3 , X , 195 , 0 , Z ) , " & " 195 ( BC_1 , * , control , 0 ) , " & " 196 ( BC_2 , DATA(24) , input , X ) , " & " 197 ( BC_1 , DATA(25) , output3 , X , 198 , 0 , Z ) , " & " 198 ( BC_1 , * , control , 0 ) , " & " 199 ( BC_2 , DATA(25) , input , X ) , " & " 200 ( BC_1 , DATA(26) , output3 , X , 201 , 0 , Z ) , " & " 201 ( BC_1 , * , control , 0 ) , " & " 202 ( BC_2 , DATA(26) , input , X ) , " & " 203 ( BC_1 , DATA(27) , output3 , X , 204 , 0 , Z ) , " & " 204 ( BC_1 , * , control , 0 ) , " & " 205 ( BC_2 , DATA(27) , input , X ) , " & " 206 ( BC_1 , DATA(28) , output3 , X , 207 , 0 , Z ) , " & " 207 ( BC_1 , * , control , 0 ) , " & " 208 ( BC_2 , DATA(28) , input , X ) , " & " 209 ( BC_1 , DATA(29) , output3 , X , 210 , 0 , Z ) , " & " 210 ( BC_1 , * , control , 0 ) , " & " 211 ( BC_2 , DATA(29) , input , X ) , " & " 212 ( BC_1 , DATA(30) , output3 , X , 213 , 0 , Z ) , " & " 213 ( BC_1 , * , control , 0 ) , " & " 214 ( BC_2 , DATA(30) , input , X ) , " & " 215 ( BC_1 , DATA(31) , output3 , X , 216 , 0 , Z ) , " & " 216 ( BC_1 , * , control , 0 ) , " & " 217 ( BC_2 , DATA(31) , input , X ) , " & " 218 ( BC_1 , PF(0) , output3 , X , 219 , 0 , Z ) , " & " 219 ( BC_1 , * , control , 0 ) , " & " 220 ( BC_2 , PF(0) , input , X ) , " & " 221 ( BC_1 , PF(1) , output3 , X , 222 , 0 , Z ) , " & " 222 ( BC_1 , * , control , 0 ) , " & " 223 ( BC_2 , PF(1) , input , X ) , " & " 224 ( BC_1 , PF(2) , output3 , X , 225 , 0 , Z ) , " & " 225 ( BC_1 , * , control , 0 ) , " & " 226 ( BC_2 , PF(2) , input , X ) , " & " 227 ( BC_1 , PF(3) , output3 , X , 228 , 0 , Z ) , " & " 228 ( BC_1 , * , control , 0 ) , " & " 229 ( BC_2 , PF(3) , input , X ) , " & " 230 ( BC_1 , PF(4) , output3 , X , 231 , 0 , Z ) , " & " 231 ( BC_1 , * , control , 0 ) , " & " 232 ( BC_2 , PF(4) , input , X ) , " & " 233 ( BC_1 , PF(5) , output3 , X , 234 , 0 , Z ) , " & " 234 ( BC_1 , * , control , 0 ) , " & " 235 ( BC_2 , PF(5) , input , X ) , " & " 236 ( BC_1 , PF(6) , output3 , X , 237 , 0 , Z ) , " & " 237 ( BC_1 , * , control , 0 ) , " & " 238 ( BC_2 , PF(6) , input , X ) , " & " 239 ( BC_1 , PF(7) , output3 , X , 240 , 0 , Z ) , " & " 240 ( BC_1 , * , control , 0 ) , " & " 241 ( BC_2 , PF(7) , input , X ) , " & " 242 ( BC_1 , PF(8) , output3 , X , 243 , 0 , Z ) , " & " 243 ( BC_1 , * , control , 0 ) , " & " 244 ( BC_2 , PF(8) , input , X ) , " & " 245 ( BC_1 , PF(9) , output3 , X , 246 , 0 , Z ) , " & " 246 ( BC_1 , * , control , 0 ) , " & " 247 ( BC_2 , PF(9) , input , X ) , " & " 248 ( BC_1 , PF(10) , output3 , X , 249 , 0 , Z ) , " & " 249 ( BC_1 , * , control , 0 ) , " & " 250 ( BC_2 , PF(10) , input , X ) , " & " 251 ( BC_1 , PF(11) , output3 , X , 252 , 0 , Z ) , " & " 252 ( BC_1 , * , control , 0 ) , " & " 253 ( BC_2 , PF(11) , input , X ) , " & " 254 ( BC_1 , PF(12) , output3 , X , 255 , 0 , Z ) , " & " 255 ( BC_1 , * , control , 0 ) , " & " 256 ( BC_2 , PF(12) , input , X ) , " & " 257 ( BC_1 , PF(13) , output3 , X , 258 , 0 , Z ) , " & " 258 ( BC_1 , * , control , 0 ) , " & " 259 ( BC_2 , PF(13) , input , X ) , " & " 260 ( BC_1 , PF(14) , output3 , X , 261 , 0 , Z ) , " & " 261 ( BC_1 , * , control , 0 ) , " & " 262 ( BC_2 , PF(14) , input , X ) , " & " 263 ( BC_1 , PF(15) , output3 , X , 264 , 0 , Z ) , " & " 264 ( BC_1 , * , control , 0 ) , " & " 265 ( BC_2 , PF(15) , input , X ) , " & " 266 ( BC_1 , RSCLK0 , output3 , X , 267 , 0 , Z ) , " & " 267 ( BC_1 , * , control , 0 ) , " & " 268 ( BC_2 , RSCLK0 , input , X ) , " & " 269 ( BC_1 , RFS0 , output3 , X , 270 , 0 , Z ) , " & " 270 ( BC_1 , * , control , 0 ) , " & " 271 ( BC_2 , RFS0 , input , X ) , " & " 272 ( BC_2 , DR0 , input , X ) , " & " 273 ( BC_1 , TSCLK0 , output3 , X , 274 , 0 , Z ) , " & " 274 ( BC_1 , * , control , 0 ) , " & " 275 ( BC_2 , TSCLK0 , input , X ) , " & " 276 ( BC_1 , TFS0 , output3 , X , 277 , 0 , Z ) , " & " 277 ( BC_1 , * , control , 0 ) , " & " 278 ( BC_2 , TFS0 , input , X ) , " & " 279 ( BC_1 , DT0 , output3 , X , 280 , 0 , Z ) , " & " 280 ( BC_1 , * , control , 0 ) , " & " 281 ( BC_1 , RSCLK1 , output3 , X , 282 , 0 , Z ) , " & " 282 ( BC_1 , * , control , 0 ) , " & " 283 ( BC_2 , RSCLK1 , input , X ) , " & " 284 ( BC_1 , RFS1 , output3 , X , 285 , 0 , Z ) , " & " 285 ( BC_1 , * , control , 0 ) , " & " 286 ( BC_2 , RFS1 , input , X ) , " & " 287 ( BC_2 , DR1 , input , X ) , " & " 288 ( BC_1 , TSCLK1 , output3 , X , 289 , 0 , Z ) , " & " 289 ( BC_1 , * , control , 0 ) , " & " 290 ( BC_2 , TSCLK1 , input , X ) , " & " 291 ( BC_1 , TFS1 , output3 , X , 292 , 0 , Z ) , " & " 292 ( BC_1 , * , control , 0 ) , " & " 293 ( BC_2 , TFS1 , input , X ) , " & " 294 ( BC_1 , DT1 , output3 , X , 295 , 0 , Z ) , " & " 295 ( BC_1 , * , control , 0 ) , " & " 296 ( BC_1 , MOSI0 , output3 , X , 297 , 0 , Z ) , " & " 297 ( BC_1 , * , control , 0 ) , " & " 298 ( BC_2 , MOSI0 , input , X ) , " & " 299 ( BC_1 , MISO0 , output3 , X , 300 , 0 , Z ) , " & " 300 ( BC_1 , * , control , 0 ) , " & " 301 ( BC_2 , MISO0 , input , X ) , " & " 302 ( BC_1 , SCK0 , output3 , X , 303 , 0 , Z ) , " & " 303 ( BC_1 , * , control , 0 ) , " & " 304 ( BC_2 , SCK0 , input , X ) , " & " 305 ( BC_1 , MOSI1 , output3 , X , 306 , 0 , Z ) , " & " 306 ( BC_1 , * , control , 0 ) , " & " 307 ( BC_2 , MOSI1 , input , X ) , " & " 308 ( BC_1 , MISO1 , output3 , X , 309 , 0 , Z ) , " & " 309 ( BC_1 , * , control , 0 ) , " & " 310 ( BC_2 , MISO1 , input , X ) , " & " 311 ( BC_1 , SCK1 , output3 , X , 312 , 0 , Z ) , " & " 312 ( BC_1 , * , control , 0 ) , " & " 313 ( BC_2 , SCK1 , input , X ) , " & " 314 ( BC_1 , PCI_AD(31) , output3 , X , 315 , 0 , Z ) , " & " 315 ( BC_1 , * , control , 0 ) , " & " 316 ( BC_2 , PCI_AD(31) , input , X ) , " & " 317 ( BC_1 , PCI_AD(30) , output3 , X , 318 , 0 , Z ) , " & " 318 ( BC_1 , * , control , 0 ) , " & " 319 ( BC_2 , PCI_AD(30) , input , X ) , " & " 320 ( BC_1 , PCI_AD(29) , output3 , X , 321 , 0 , Z ) , " & " 321 ( BC_1 , * , control , 0 ) , " & " 322 ( BC_2 , PCI_AD(29) , input , X ) , " & " 323 ( BC_1 , PCI_AD(28) , output3 , X , 324 , 0 , Z ) , " & " 324 ( BC_1 , * , control , 0 ) , " & " 325 ( BC_2 , PCI_AD(28) , input , X ) , " & " 326 ( BC_1 , PCI_AD(27) , output3 , X , 327 , 0 , Z ) , " & " 327 ( BC_1 , * , control , 0 ) , " & " 328 ( BC_2 , PCI_AD(27) , input , X ) , " & " 329 ( BC_1 , PCI_AD(26) , output3 , X , 330 , 0 , Z ) , " & " 330 ( BC_1 , * , control , 0 ) , " & " 331 ( BC_2 , PCI_AD(26) , input , X ) , " & " 332 ( BC_1 , PCI_AD(25) , output3 , X , 333 , 0 , Z ) , " & " 333 ( BC_1 , * , control , 0 ) , " & " 334 ( BC_2 , PCI_AD(25) , input , X ) , " & " 335 ( BC_1 , PCI_AD(24) , output3 , X , 336 , 0 , Z ) , " & " 336 ( BC_1 , * , control , 0 ) , " & " 337 ( BC_2 , PCI_AD(24) , input , X ) , " & " 338 ( BC_1 , PCI_AD(23) , output3 , X , 339 , 0 , Z ) , " & " 339 ( BC_1 , * , control , 0 ) , " & " 340 ( BC_2 , PCI_AD(23) , input , X ) , " & " 341 ( BC_1 , PCI_AD(22) , output3 , X , 342 , 0 , Z ) , " & " 342 ( BC_1 , * , control , 0 ) , " & " 343 ( BC_2 , PCI_AD(22) , input , X ) , " & " 344 ( BC_1 , PCI_AD(21) , output3 , X , 345 , 0 , Z ) , " & " 345 ( BC_1 , * , control , 0 ) , " & " 346 ( BC_2 , PCI_AD(21) , input , X ) , " & " 347 ( BC_1 , PCI_AD(20) , output3 , X , 348 , 0 , Z ) , " & " 348 ( BC_1 , * , control , 0 ) , " & " 349 ( BC_2 , PCI_AD(20) , input , X ) , " & " 350 ( BC_1 , PCI_AD(19) , output3 , X , 351 , 0 , Z ) , " & " 351 ( BC_1 , * , control , 0 ) , " & " 352 ( BC_2 , PCI_AD(19) , input , X ) , " & " 353 ( BC_1 , PCI_AD(18) , output3 , X , 354 , 0 , Z ) , " & " 354 ( BC_1 , * , control , 0 ) , " & " 355 ( BC_2 , PCI_AD(18) , input , X ) , " & " 356 ( BC_1 , PCI_AD(17) , output3 , X , 357 , 0 , Z ) , " & " 357 ( BC_1 , * , control , 0 ) , " & " 358 ( BC_2 , PCI_AD(17) , input , X ) , " & " 359 ( BC_1 , PCI_AD(16) , output3 , X , 360 , 0 , Z ) , " & " 360 ( BC_1 , * , control , 0 ) , " & " 361 ( BC_2 , PCI_AD(16) , input , X ) , " & " 362 ( BC_1 , PCI_AD(15) , output3 , X , 363 , 0 , Z ) , " & " 363 ( BC_1 , * , control , 0 ) , " & " 364 ( BC_2 , PCI_AD(15) , input , X ) , " & " 365 ( BC_1 , PCI_AD(14) , output3 , X , 366 , 0 , Z ) , " & " 366 ( BC_1 , * , control , 0 ) , " & " 367 ( BC_2 , PCI_AD(14) , input , X ) , " & " 368 ( BC_1 , PCI_AD(13) , output3 , X , 369 , 0 , Z ) , " & " 369 ( BC_1 , * , control , 0 ) , " & " 370 ( BC_2 , PCI_AD(13) , input , X ) , " & " 371 ( BC_1 , PCI_AD(12) , output3 , X , 372 , 0 , Z ) , " & " 372 ( BC_1 , * , control , 0 ) , " & " 373 ( BC_2 , PCI_AD(12) , input , X ) , " & " 374 ( BC_1 , PCI_AD(11) , output3 , X , 375 , 0 , Z ) , " & " 375 ( BC_1 , * , control , 0 ) , " & " 376 ( BC_2 , PCI_AD(11) , input , X ) , " & " 377 ( BC_1 , PCI_AD(10) , output3 , X , 378 , 0 , Z ) , " & " 378 ( BC_1 , * , control , 0 ) , " & " 379 ( BC_2 , PCI_AD(10) , input , X ) , " & " 380 ( BC_1 , PCI_AD(9) , output3 , X , 381 , 0 , Z ) , " & " 381 ( BC_1 , * , control , 0 ) , " & " 382 ( BC_2 , PCI_AD(9) , input , X ) , " & " 383 ( BC_1 , PCI_AD(8) , output3 , X , 384 , 0 , Z ) , " & " 384 ( BC_1 , * , control , 0 ) , " & " 385 ( BC_2 , PCI_AD(8) , input , X ) , " & " 386 ( BC_1 , PCI_AD(7) , output3 , X , 387 , 0 , Z ) , " & " 387 ( BC_1 , * , control , 0 ) , " & " 388 ( BC_2 , PCI_AD(7) , input , X ) , " & " 389 ( BC_1 , PCI_AD(6) , output3 , X , 390 , 0 , Z ) , " & " 390 ( BC_1 , * , control , 0 ) , " & " 391 ( BC_2 , PCI_AD(6) , input , X ) , " & " 392 ( BC_1 , PCI_AD(5) , output3 , X , 393 , 0 , Z ) , " & " 393 ( BC_1 , * , control , 0 ) , " & " 394 ( BC_2 , PCI_AD(5) , input , X ) , " & " 395 ( BC_1 , PCI_AD(4) , output3 , X , 396 , 0 , Z ) , " & " 396 ( BC_1 , * , control , 0 ) , " & " 397 ( BC_2 , PCI_AD(4) , input , X ) , " & " 398 ( BC_1 , PCI_AD(3) , output3 , X , 399 , 0 , Z ) , " & " 399 ( BC_1 , * , control , 0 ) , " & " 400 ( BC_2 , PCI_AD(3) , input , X ) , " & " 401 ( BC_1 , PCI_AD(2) , output3 , X , 402 , 0 , Z ) , " & " 402 ( BC_1 , * , control , 0 ) , " & " 403 ( BC_2 , PCI_AD(2) , input , X ) , " & " 404 ( BC_1 , PCI_AD(1) , output3 , X , 405 , 0 , Z ) , " & " 405 ( BC_1 , * , control , 0 ) , " & " 406 ( BC_2 , PCI_AD(1) , input , X ) , " & " 407 ( BC_1 , PCI_AD(0) , output3 , X , 408 , 0 , Z ) , " & " 408 ( BC_1 , * , control , 0 ) , " & " 409 ( BC_2 , PCI_AD(0) , input , X ) , " & " 410 ( BC_1 , PCI_CBE(0) , output3 , X , 411 , 0 , Z ) , " & " 411 ( BC_1 , * , control , 0 ) , " & " 412 ( BC_2 , PCI_CBE(0) , input , X ) , " & " 413 ( BC_1 , PCI_CBE(1) , output3 , X , 414 , 0 , Z ) , " & " 414 ( BC_1 , * , control , 0 ) , " & " 415 ( BC_2 , PCI_CBE(1) , input , X ) , " & " 416 ( BC_1 , PCI_CBE(2) , output3 , X , 417 , 0 , Z ) , " & " 417 ( BC_1 , * , control , 0 ) , " & " 418 ( BC_2 , PCI_CBE(2) , input , X ) , " & " 419 ( BC_1 , PCI_CBE(3) , output3 , X , 420 , 0 , Z ) , " & " 420 ( BC_1 , * , control , 0 ) , " & " 421 ( BC_2 , PCI_CBE(3) , input , X ) , " & " 422 ( BC_1 , PCI_IRDY , output3 , X , 423 , 0 , Z ) , " & " 423 ( BC_1 , * , control , 0 ) , " & " 424 ( BC_2 , PCI_IRDY , input , X ) , " & " 425 ( BC_1 , PCI_RST , output3 , X , 426 , 0 , Z ) , " & " 426 ( BC_1 , * , control , 0 ) , " & " 427 ( BC_2 , PCI_RST , input , X ) , " & " 428 ( BC_1 , PCI_REQ , output3 , X , 429 , 0 , Z ) , " & " 429 ( BC_1 , * , control , 0 ) , " & " 430 ( BC_2 , PCI_GNT , input , X ) , " & " 431 ( BC_2 , PCI_IDSEL , input , X ) , " & " 432 ( BC_1 , PCI_FRAME , output3 , X , 433 , 0 , Z ) , " & " 433 ( BC_1 , * , control , 0 ) , " & " 434 ( BC_2 , PCI_FRAME , input , X ) , " & " 435 ( BC_1 , PCI_TRDY , output3 , X , 436 , 0 , Z ) , " & " 436 ( BC_1 , * , control , 0 ) , " & " 437 ( BC_2 , PCI_TRDY , input , X ) , " & " 438 ( BC_1 , PCI_DEVSEL , output3 , X , 439 , 0 , Z ) , " & " 439 ( BC_1 , * , control , 0 ) , " & " 440 ( BC_2 , PCI_DEVSEL , input , X ) , " & " 441 ( BC_1 , PCI_STOP , output3 , X , 442 , 0 , Z ) , " & " 442 ( BC_1 , * , control , 0 ) , " & " 443 ( BC_2 , PCI_STOP , input , X ) , " & " 444 ( BC_1 , PCI_PERR , output3 , X , 445 , 0 , Z ) , " & " 445 ( BC_1 , * , control , 0 ) , " & " 446 ( BC_2 , PCI_PERR , input , X ) , " & " 447 ( BC_1 , PCI_PAR , output3 , X , 448 , 0 , Z ) , " & " 448 ( BC_1 , * , control , 0 ) , " & " 449 ( BC_2 , PCI_PAR , input , X ) , " & " 450 ( BC_1 , PCI_SERR , output3 , X , 451 , 0 , Z ) , " & " 451 ( BC_1 , * , control , 0 ) , " & " 452 ( BC_2 , PCI_SERR , input , X ) , " & " 453 ( BC_2 , PCI_LOCK , input , X ) , " & " 454 ( BC_2 , PCI_CLK , input , X ) , " & " 455 ( BC_1 , PCI_INTA , output3 , X , 456 , 0 , Z ) , " & " 456 ( BC_1 , * , control , 0 ) , " & " 457 ( BC_2 , PCI_INTA , input , X ) , " & " 458 ( BC_2 , PCI_INTB , input , X ) , " & " 459 ( BC_2 , PCI_INTC , input , X ) , " & " 460 ( BC_2 , PCI_INTD , input , X ) , " & " 461 ( BC_2 , BMODE(0) , input , X ) , " & " 462 ( BC_2 , BMODE(1) , input , X ) , " & " 463 ( BC_2 , BMODE(2) , input , X ) , " & " 464 ( BC_1 , SLEEP , output3 , X , 465 , 0 , Z ) , " & " 465 ( BC_1 , * , control , 0 ) , " & " 466 ( BC_2 , BYPASS , input , X ) , " & " 467 ( BC_1 , EMU_B , output3 , X , 468 , 0 , Z ) , " & " 468 ( BC_1 , * , control , 0 ) " ; end ADSP_21535;