-- Company: Integrated Device Technology, Inc. -- Title: PowerSpan II Single PCI 420 HSBGA BSDL -- BSDL Version 1994 -- File No.: 35A101A_BS001_04 -- Security level: Public Release status: Formal Issue -- Group ownership: RnD Revision Date: Oct. 3, 2002 -- Generated by : Ken Pham -- Released by : Ken Pham -- Revision history: -- status rev no Date Reviser/Group Description -- -------- ------ -------- ------------------ ------------------------------------ -- formal 01 Oct.2/01 DFT Dept Initial (1.0) -- formal 02 Apr.2/02 DFT Dept update signal names (1.1) -- formal 03 Oct.3/02 F.Lu/Apps Add comment (1.2) -- formal 04 Sep.9/09 Apps Updated with IDT formatting -- HP BSDL Syntax Checker -> Pass -- Important Note before begin interconnect test: -- The PO_RST signal is an input pin only during normal operation of the -- device. This pin is defined as inout (bi-directional) in this BSDL file -- below. Some automatic JTAG pattern generation toolsets will drive -- the PO_RST net logic low as a part of boundary scan to fully test -- interconnectivity. In most applications the power-on reset (PO_RST net) -- is shared by multiple devices. Please ensure that the JTAG behavior -- of other component(s) on the same PO_RST net will not be influenced -- by the assertion of PO_RST. If you do experience problems, -- please constrain the pattern generator to keep PO_RST net high -- during the boundary scan test. entity pspan is generic (PHYSICAL_PIN_MAP : string := "HSBGA_420_35_SINGLE_PCI"); port ( -- Port List TDI : in bit; PB_A : inout bit_vector( 0 to 31 ); ES : inout bit; PB_RST_DIR : inout bit; PB_BR2_b : inout bit; PB_DBG3_b : inout bit; PB_TT : inout bit_vector( 0 to 4 ); PB_BR3_b : inout bit; INT_b : inout bit_vector( 0 to 5 ); PB_TS_b : inout bit; HEALTHY_b : inout bit; PB_TBST_b : inout bit; PB_AACK_b : inout bit; PB_TSIZ : inout bit_vector( 0 to 3 ); PB_ARTRY_b : inout bit; PB_BG1_b : inout bit; I2C_SCLK : inout bit; PB_AP : inout bit_vector( 0 to 3 ); PB_DVAL_b : inout bit; PB_TEA_b : inout bit; PB_TA_b : inout bit; PB_D : inout bit_vector( 0 to 63 ); LED_b : inout bit; I2C_SDA : inout bit; PB_BG3_b : inout bit; TRST_b : in bit; PB_BG2_b : inout bit; PB_CLK : inout bit; PB_TEST1 : linkage bit; PB_TEST2 : linkage bit; PB_DBB_b : inout bit; PB_ABB_b : inout bit; PB_FAST : inout bit; PB_RSTCONF_b : inout bit; PO_RST_b : inout bit; PB_RST_b : inout bit; PB_DP : inout bit_vector( 0 to 7 ); PCI_GNT_b : inout bit_vector( 5 to 7 ); P1_AD : inout bit_vector( 0 to 63 ); PCI_REQ_b : inout bit_vector( 5 to 7 ); P1_RST_b : inout bit; P1_CBE : inout bit_vector( 0 to 7 ); P1_IRDY_b : inout bit; P1_FRAME_b : inout bit; P1_PERR_b : inout bit; P1_STOP_b : inout bit; P1_DEVSEL_b : inout bit; P1_TRDY_b : inout bit; P1_INTA_b : inout bit; P1_PAR : inout bit; P1_GNT_b : inout bit_vector( 1 to 4 ); P1_REQ_b : inout bit_vector( 1 to 4 ); P1_64EN_b : inout bit; P1_CLK : inout bit; P1_ACK64_b : inout bit; P1_REQ64_b : inout bit; P2_TEST1 : linkage bit; P1_TEST1 : linkage bit; P1_TEST2 : linkage bit; ENUM_b : inout bit; P1_PAR64 : inout bit; P1_IDSEL : inout bit; P1_M66EN : inout bit; P1_SERR_b : inout bit; PB_CI_b : inout bit; PB_DBG1_b : inout bit; P1_RST_DIR : inout bit; PB_GBL_b : inout bit; PB_BR1_b : inout bit; TMS : in bit; PB_DBG2_b : inout bit; TCK : in bit; TDO : out bit; TE : in bit; PB_VDDA : linkage bit ; PB_AVSS : linkage bit ; PB_DVDD : linkage bit ; PB_DVSS : linkage bit ; VDD25 : linkage bit_vector ( 1 to 22 ); VDD33 : linkage bit_vector ( 1 to 24 ); VSS : linkage bit_vector ( 1 to 20 ); VSS_IO : linkage bit_vector ( 1 to 60 ); NC : linkage bit_vector ( 1 to 16 ); P1_AVSS : linkage bit ; P1_DVDD : linkage bit ; P1_DVSS : linkage bit ; P1_VDDA : linkage bit ); use STD_1149_1_1994.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of pspan: entity is "STD_1149_1_1993"; --Pin mappings attribute PIN_MAP of pspan: entity is PHYSICAL_PIN_MAP; constant HSBGA_420_35_SINGLE_PCI: PIN_MAP_STRING := "ENUM_b : B21 , " & "ES : E4 , " & "HEALTHY_b : J1 , " & "I2C_SCLK : N1 , " & "I2C_SDA : AF9 , " & "INT_b : (AF18 , " & -- INT_[0] "AF3 , " & -- INT_[1] "AE3 , " & -- INT_[2] "AD1 , " & -- INT_[3] "J4 , " & -- INT_[4] "AB1) , " & -- INT_[5] "TCK : A5 , " & "TDI : A3 , " & "TDO : A4 , " & "TMS : D7 , " & "TRST_b : AC1 , " & "LED_b : AC7 , " & "NC : (AB26 , " & "AC5 , " & "AD25 , " & "AE17 , " & "AE18 , " & "AE26 , " & "AE6 , " & "AF22 , " & "AF23 , " & "AF24 , " & "B22 , " & "C14 , " & "F3 , " & "P2 , " & "U23 , " & "V2) , " & "P1_64EN_b : B24 , " & "P1_ACK64_b : F23 , " & "P1_AD : (F24 , " & -- P1_AD[0] "G24 , " & -- P1_AD[1] "M26 , " & -- P1_AD[2] "G26 , " & -- P1_AD[3] "G25 , " & -- P1_AD[4] "M25 , " & -- P1_AD[5] "G23 , " & -- P1_AD[6] "J24 , " & -- P1_AD[7] "H23 , " & -- P1_AD[8] "H24 , " & -- P1_AD[9] "K25 , " & -- P1_AD[10] "K24 , " & -- P1_AD[11] "K23 , " & -- P1_AD[12] "K26 , " & -- P1_AD[13] "M24 , " & -- P1_AD[14] "M23 , " & -- P1_AD[15] "R26 , " & -- P1_AD[16] "P23 , " & -- P1_AD[17] "P24 , " & -- P1_AD[18] "P25 , " & -- P1_AD[19] "T25 , " & -- P1_AD[20] "R24 , " & -- P1_AD[21] "R25 , " & -- P1_AD[22] "U24 , " & -- P1_AD[23] "T23 , " & -- P1_AD[24] "U25 , " & -- P1_AD[25] "V24 , " & -- P1_AD[26] "V23 , " & -- P1_AD[27] "W25 , " & -- P1_AD[28] "W24 , " & -- P1_AD[29] "W23 , " & -- P1_AD[30] "AC26 , " & -- P1_AD[31] "B12 , " & -- P1_AD[32] "B11 , " & -- P1_AD[33] "A12 , " & -- P1_AD[34] "D12 , " & -- P1_AD[35] "D25 , " & -- P1_AD[36] "C12 , " & -- P1_AD[37] "E24 , " & -- P1_AD[38] "B13 , " & -- P1_AD[39] "A13 , " & -- P1_AD[40] "B14 , " & -- P1_AD[41] "D24 , " & -- P1_AD[42] "D13 , " & -- P1_AD[43] "A14 , " & -- P1_AD[44] "D14 , " & -- P1_AD[45] "C23 , " & -- P1_AD[46] "A15 , " & -- P1_AD[47] "B15 , " & -- P1_AD[48] "B16 , " & -- P1_AD[49] "A17 , " & -- P1_AD[50] "A18 , " & -- P1_AD[51] "B17 , " & -- P1_AD[52] "C16 , " & -- P1_AD[53] "D16 , " & -- P1_AD[54] "E25 , " & -- P1_AD[55] "B19 , " & -- P1_AD[56] "C17 , " & -- P1_AD[57] "D17 , " & -- P1_AD[58] "A20 , " & -- P1_AD[59] "C18 , " & -- P1_AD[60] "C19 , " & -- P1_AD[61] "E23 , " & -- P1_AD[62] "D18) , " & -- P1_AD[63] "P1_AVSS : D23 , " & "P1_CBE : (J23 , " & -- P1_CBE[0] "L25 , " & -- P1_CBE[1] "N24 , " & -- P1_CBE[2] "T24 , " & -- P1_CBE[3] "D20 , " & -- P1_CBE[4] "C21 , " & -- P1_CBE[5] "C20 , " & -- P1_CBE[6] "A23) , " & -- P1_CBE[7] "P1_CLK : A25 , " & "P1_DEVSEL_b : Y24 , " & "P1_DVDD : K22 , " & "P1_DVSS : E22 , " & "P1_FRAME_b : N23 , " & "P1_GNT_b : (B23 , " & -- P1_GNT_[1] "D22 , " & -- P1_GNT_[2] "A24 , " & -- P1_GNT_[3] "J25) , " & -- P1_GNT_[4] "PCI_GNT_b : (H25 , " & -- PCI_GNT_[5] "J26 , " & -- PCI_GNT_[6] "AB23) , " & -- PCI_GNT_[7] "P1_IDSEL : B20 , " & "P1_INTA_b : L23 , " & "P1_IRDY_b : P26 , " & "P1_M66EN : D15 , " & "P1_PAR : L24 , " & "P1_PAR64 : D19 , " & "P1_PERR_b : N25 , " & "P1_REQ64_b : F25 , " & "P1_REQ_b : (C22 , " & -- P1_REQ_[1] "D26 , " & -- P1_REQ_[2] "B18 , " & -- P1_REQ_[3] "A19) , " & -- P1_REQ_[4] "P1_RST_DIR : A8 , " & "P1_RST_b : AC25 , " & "P1_SERR_b : C15 , " & "P1_STOP_b : N26 , " & "P1_TEST1 : R23 , " & "P1_TEST2 : H26 , " & "P1_TRDY_b : Y25 , " & "P1_VDDA : A22 , " & "P2_TEST1 : AD16 , " & "PB_AACK_b : K1 , " & "PB_ABB_b : AF8 , " & "PB_AP : (P4 , " & -- PB_AP[0] "P1 , " & -- PB_AP[1] "N4 , " & -- PB_AP[2] "N3) , " & -- PB_AP[3] "PB_ARTRY_b : L2 , " & "PB_AVSS : AC4 , " & "PB_A : (J3 , " & -- PB_A[0] "G2 , " & -- PB_A[1] "H4 , " & -- PB_A[2] "G4 , " & -- PB_A[3] "H3 , " & -- PB_A[4] "G3 , " & -- PB_A[5] "F4 , " & -- PB_A[6] "D3 , " & -- PB_A[7] "D1 , " & -- PB_A[8] "E3 , " & -- PB_A[9] "C2 , " & -- PB_A[10] "D2 , " & -- PB_A[11] "D5 , " & -- PB_A[12] "B3 , " & -- PB_A[13] "D6 , " & -- PB_A[14] "C5 , " & -- PB_A[15] "C6 , " & -- PB_A[16] "C4 , " & -- PB_A[17] "B6 , " & -- PB_A[18] "B4 , " & -- PB_A[19] "B5 , " & -- PB_A[20] "B7 , " & -- PB_A[21] "C7 , " & -- PB_A[22] "D8 , " & -- PB_A[23] "D9 , " & -- PB_A[24] "C8 , " & -- PB_A[25] "B8 , " & -- PB_A[26] "C10 , " & -- PB_A[27] "D10 , " & -- PB_A[28] "C9 , " & -- PB_A[29] "A7 , " & -- PB_A[30] "D11) , " & -- PB_A[31] "PB_BG1_b : L4 , " & "PB_BG2_b : AF2 , " & "PB_BG3_b : V1 , " & "PB_BR1_b : B10 , " & "PB_BR2_b : F2 , " & "PB_BR3_b : H1 , " & "PB_CI_b : C25 , " & "PB_CLK : AF5 , " & "PB_DBB_b : AE5 , " & "PB_DBG1_b : A10 , " & "PB_DBG2_b : B9 , " & "PB_DBG3_b : E1 , " & "PB_DP : (AE20 , " & -- PB_DP[0] "AD20 , " & -- PB_DP[1] "AD18 , " & -- PB_DP[2] "AC18 , " & -- PB_DP[3] "AD19 , " & -- PB_DP[4] "AC20 , " & -- PB_DP[5] "AC17 , " & -- PB_DP[6] "AD17) , " & -- PB_DP[7] "PB_DVAL_b : AF7 , " & "PB_DVDD : AB10 , " & "PB_DVSS : AD3 , " & "PB_D : (AD21 , " & -- PB_D[0] "AC14 , " & -- PB_D[1] "AD12 , " & -- PB_D[2] "AC6 , " & -- PB_D[3] "AF20 , " & -- PB_D[4] "V4 , " & -- PB_D[5] "T2 , " & -- PB_D[6] "R4 , " & -- PB_D[7] "AC22 , " & -- PB_D[8] "AD14 , " & -- PB_D[9] "AE11 , " & -- PB_D[10] "AD7 , " & -- PB_D[11] "AA4 , " & -- PB_D[12] "Y4 , " & -- PB_D[13] "AD6 , " & -- PB_D[14] "AE7 , " & -- PB_D[15] "AF17 , " & -- PB_D[16] "AE14 , " & -- PB_D[17] "AC11 , " & -- PB_D[18] "AC9 , " & -- PB_D[19] "Y2 , " & -- PB_D[20] "U4 , " & -- PB_D[21] "R3 , " & -- PB_D[22] "T4 , " & -- PB_D[23] "AC16 , " & -- PB_D[24] "AF14 , " & -- PB_D[25] "AF10 , " & -- PB_D[26] "AC10 , " & -- PB_D[27] "AA3 , " & -- PB_D[28] "V3 , " & -- PB_D[29] "U1 , " & -- PB_D[30] "AD4 , " & -- PB_D[31] "AE21 , " & -- PB_D[32] "AD13 , " & -- PB_D[33] "AD11 , " & -- PB_D[34] "AB4 , " & -- PB_D[35] "AA2 , " & -- PB_D[36] "AD2 , " & -- PB_D[37] "AD5 , " & -- PB_D[38] "AE4 , " & -- PB_D[39] "AE16 , " & -- PB_D[40] "AC13 , " & -- PB_D[41] "AD9 , " & -- PB_D[42] "AB3 , " & -- PB_D[43] "AB2 , " & -- PB_D[44] "W3 , " & -- PB_D[45] "U3 , " & -- PB_D[46] "R2 , " & -- PB_D[47] "AD15 , " & -- PB_D[48] "AF12 , " & -- PB_D[49] "AD10 , " & -- PB_D[50] "AD8 , " & -- PB_D[51] "Y1 , " & -- PB_D[52] "AC2 , " & -- PB_D[53] "U2 , " & -- PB_D[54] "T3 , " & -- PB_D[55] "AE15 , " & -- PB_D[56] "AC12 , " & -- PB_D[57] "AE10 , " & -- PB_D[58] "AE8 , " & -- PB_D[59] "W4 , " & -- PB_D[60] "AF4 , " & -- PB_D[61] "W1 , " & -- PB_D[62] "AC19) , " & -- PB_D[63] "PB_FAST : AC15 , " & "PB_GBL_b : C11 , " & "PB_RSTCONF_b : AE13 , " & "PB_RST_DIR : C1 , " & "PB_RST_b : AF15 , " & "PB_TA_b : P3 , " & "PB_TBST_b : M3 , " & "PB_TEA_b : AC3 , " & "PB_TEST1 : Y3 , " & "PB_TEST2 : W2 , " & "PB_TSIZ : (N2 , " & -- PB_TSIZ[0] "M2 , " & -- PB_TSIZ[1] "M4 , " & -- PB_TSIZ[2] "L3) , " & -- PB_TSIZ[3] "PB_TS_b : M1 , " & "PB_TT : (K3 , " & -- PB_TT[0] "K4 , " & -- PB_TT[1] "H2 , " & -- PB_TT[2] "G1 , " & -- PB_TT[3] "K2) , " & -- PB_TT[4] "PB_VDDA : AE9 , " & "PCI_REQ_b : (C26 , " & -- PCI_REQ_[5] "E26 , " & -- PCI_REQ_[6] "W26) , " & -- PCI_REQ_[7] "PO_RST_b : AF13 , " & "TE : B1 , " & "VDD25 : (AB11, AB12, AB15, AB16, AB17, E10, E11, E12, E15, E16 , " & "E17, K5, L22, L5, M22, M5, R22, R5, T22, T5 , " & "U22, U5) , " & "VDD33 : (AA22, AA5, AB19, AB20, AB21, AB6, AB7, AB8, E19, E20 , " & "E21, E6, E7, E8, F22, F5, G22, G5, H22, H5 , " & "W22, W5, Y22, Y5) , " & "VSS : (AA23, AA24, AB18, AB22, AB5, AB9, AC21, AC23, AC8, AD22 , " & "D21, D4, E18, E5, E9, J22, J5, V22, V5, Y23) , " & "VSS_IO : (A1, A11, A16, A2, A21, A26, A6, A9, AA1, AA25 , " & "AA26, AB13, AB14, AB24, AB25, AC24, AD23, AD24, AD26, AE1 , " & "AE12, AE19, AE2, AE22, AE23, AE24, AE25, AF1, AF11, AF16 , " & "AF19, AF21, AF25, AF26, AF6, B2, B25, B26, C13, C24 , " & "C3, E13, E14, E2, F1, F26, J2, L1, L26, N22 , " & "N5, P22, P5, R1, T1, T26, U26, V25, V26, Y26) " ; attribute TAP_SCAN_RESET of TRST_b: signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (1.0e+07, BOTH); attribute COMPLIANCE_PATTERNS of pspan : entity is "(TE) (0)"; attribute INSTRUCTION_LENGTH of pspan: entity is 29; attribute INSTRUCTION_OPCODE of pspan: entity is "IDCODE (11111111111111111111111111110)," & "BYPASS (11111111111111111111111111111)," & "EXTEST (00000000000000000000000000000, " & "11111111111111111111111101000)," & "SAMPLE (11111111111111111111111111000)," & "HIGHZ (11111111111111111111111001111)," & "CLAMP (11111111111111111111111101111) " ; attribute INSTRUCTION_CAPTURE of pspan: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of pspan: entity is "0001" & -- version "1000001001100001" & -- part number "00010110011" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of pspan: entity is "BYPASS (HIGHZ, CLAMP) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of pspan: entity is 336; attribute BOUNDARY_REGISTER of pspan: entity is -- num cell port function safe [ccell disval rslt] " 335 (BC_2 , * , control , 0 ) ,"& " 334 (BC_2 , * , control , 0 ) ,"& " 333 (LV_BC_7, PB_A(10) , bidir , X, 334, 0 , Z ),"& " 332 (LV_BC_7, PB_A(11) , bidir , X, 334, 0 , Z ),"& " 331 (LV_BC_7, PB_A(9) , bidir , X, 334, 0 , Z ),"& " 330 (BC_2 , * , control , 0 ) ,"& " 329 (LV_BC_7, ES , bidir , X, 330, 0 , Z ),"& " 328 (LV_BC_7, PB_A(7) , bidir , X, 334, 0 , Z ),"& " 327 (LV_BC_7, PB_A(3) , bidir , X, 335, 0 , Z ),"& " 326 (LV_BC_7, PB_A(6) , bidir , X, 335, 0 , Z ),"& " 325 (LV_BC_7, PB_RST_DIR , bidir , X, 330, 0 , Z ),"& " 324 (LV_BC_7, PB_A(8) , bidir , X, 335, 0 , Z ),"& " 323 (LV_BC_7, PB_A(2) , bidir , X, 335, 0 , Z ),"& " 322 (LV_BC_7, PB_A(5) , bidir , X, 335, 0 , Z ),"& " 321 (LV_BC_7, PB_BR2_b , bidir , X, 330, 0 , Z ),"& " 320 (BC_2 , * , control , 0 ) ,"& " 319 (LV_BC_7, PB_DBG3_b , bidir , X, 320, 0 , Z ),"& " 318 (BC_2 , * , control , 0 ) ,"& " 317 (LV_BC_7, PB_TT(3) , bidir , X, 318, 0 , Z ),"& " 316 (LV_BC_7, PB_A(4) , bidir , X, 335, 0 , Z ),"& " 315 (LV_BC_7, PB_TT(0) , bidir , X, 318, 0 , Z ),"& " 314 (LV_BC_7, PB_A(1) , bidir , X, 335, 0 , Z ),"& " 313 (LV_BC_7, PB_A(0) , bidir , X, 335, 0 , Z ),"& " 312 (LV_BC_7, PB_BR3_b , bidir , X, 330, 0 , Z ),"& " 311 (LV_BC_7, PB_TT(2) , bidir , X, 318, 0 , Z ),"& " 310 (BC_2 , * , control , 0 ) ,"& " 309 (LV_BC_7, INT_b(4) , bidir , X, 310, 0 , Z ),"& " 308 (BC_2 , * , control , 0 ) ,"& " 307 (LV_BC_7, PB_TS_b , bidir , X, 308, 0 , Z ),"& " 306 (LV_BC_7, HEALTHY_b , bidir , X, 330, 0 , Z ),"& " 305 (LV_BC_7, PB_TT(1) , bidir , X, 318, 0 , Z ),"& " 304 (BC_2 , * , control , 0 ) ,"& " 303 (LV_BC_7, PB_TBST_b , bidir , X, 304, 0 , Z ),"& " 302 (LV_BC_7, PB_TT(4) , bidir , X, 318, 0 , Z ),"& " 301 (BC_2 , * , control , 0 ) ,"& " 300 (LV_BC_7, PB_AACK_b , bidir , X, 301, 0 , Z ),"& " 299 (BC_2 , * , control , 0 ) ,"& " 298 (LV_BC_7, PB_TSIZ(3) , bidir , X, 299, 0 , Z ),"& " 297 (BC_2 , * , control , 0 ) ,"& " 296 (LV_BC_7, PB_ARTRY_b , bidir , X, 297, 0 , Z ),"& " 295 (BC_2 , * , control , 0 ) ,"& " 294 (LV_BC_7, PB_BG1_b , bidir , X, 295, 0 , Z ),"& " 293 (LV_BC_7, PB_TSIZ(2) , bidir , X, 299, 0 , Z ),"& " 292 (BC_2 , * , control , 0 ) ,"& " 291 (LV_BC_7, I2C_SCLK , bidir , X, 292, 0 , Z ),"& " 290 (LV_BC_7, PB_TSIZ(1) , bidir , X, 299, 0 , Z ),"& " 289 (LV_BC_7, PB_TSIZ(0) , bidir , X, 299, 0 , Z ),"& " 288 (BC_2 , * , control , 0 ) ,"& " 287 (LV_BC_7, PB_AP(3) , bidir , X, 288, 0 , Z ),"& " 286 (LV_BC_7, PB_AP(2) , bidir , X, 288, 0 , Z ),"& " 285 (LV_BC_7, PB_AP(1) , bidir , X, 288, 0 , Z ),"& " 284 (BC_2 , * , control , 0 ) ,"& " 283 (LV_BC_7, PB_DVAL_b , bidir , X, 284, 0 , Z ),"& " 282 (BC_2 , * , control , 0 ) ,"& " 281 (LV_BC_7, PB_TEA_b , bidir , X, 282, 0 , Z ),"& " 280 (BC_2 , * , control , 0 ) ,"& " 279 (LV_BC_7, PB_TA_b , bidir , X, 280, 0 , Z ),"& " 278 (BC_2 , * , control , 0 ) ,"& " 277 (BC_2 , * , control , 0 ) ,"& " 276 (LV_BC_7, PB_D(15) , bidir , X, 225, 0 , Z ),"& " 275 (LV_BC_7, PB_D(30) , bidir , X, 277, 0 , Z ),"& " 274 (BC_2 , * , control , 0 ) ,"& " 273 (LV_BC_7, LED_b , bidir , X, 274, 0 , Z ),"& " 272 (LV_BC_7, PB_D(7) , bidir , X, 277, 0 , Z ),"& " 271 (LV_BC_7, PB_D(22) , bidir , X, 277, 0 , Z ),"& " 270 (LV_BC_7, PB_D(55) , bidir , X, 277, 0 , Z ),"& " 269 (LV_BC_7, PB_D(6) , bidir , X, 277, 0 , Z ),"& " 268 (LV_BC_7, PB_D(31) , bidir , X, 246, 0 , Z ),"& " 267 (LV_BC_7, PB_D(62) , bidir , X, 278, 0 , Z ),"& " 266 (BC_2 , * , control , 0 ) ,"& " 265 (LV_BC_7, I2C_SDA , bidir , X, 266, 0 , Z ),"& " 264 (LV_BC_7, PB_D(21) , bidir , X, 278, 0 , Z ),"& " 263 (LV_BC_7, PB_D(38) , bidir , X, 246, 0 , Z ),"& " 262 (LV_BC_7, PB_AP(0) , bidir , X, 288, 0 , Z ),"& " 261 (LV_BC_7, PB_D(54) , bidir , X, 277, 0 , Z ),"& " 260 (BC_2 , * , control , 0 ) ,"& " 259 (BC_2 , * , control , 0 ) ,"& " 258 (LV_BC_7, PB_D(37) , bidir , X, 260, 0 , Z ),"& " 257 (LV_BC_7, PB_D(39) , bidir , X, 246, 0 , Z ),"& " 256 (LV_BC_7, PB_D(14) , bidir , X, 246, 0 , Z ),"& " 255 (LV_BC_7, PB_D(47) , bidir , X, 277, 0 , Z ),"& " 254 (LV_BC_7, PB_D(5) , bidir , X, 278, 0 , Z ),"& " 253 (LV_BC_7, PB_D(61) , bidir , X, 246, 0 , Z ),"& " 252 (LV_BC_7, PB_D(23) , bidir , X, 277, 0 , Z ),"& " 251 (LV_BC_7, PB_D(29) , bidir , X, 278, 0 , Z ),"& " 250 (LV_BC_7, PB_BG3_b , bidir , X, 295, 0 , Z ),"& " 249 (LV_BC_7, PB_D(46) , bidir , X, 278, 0 , Z ),"& " 248 (LV_BC_7, PB_D(60) , bidir , X, 259, 0 , Z ),"& " 247 (LV_BC_7, PB_D(53) , bidir , X, 259, 0 , Z ),"& " 246 (BC_2 , * , control , 0 ),"& " 245 (LV_BC_7, PB_D(20) , bidir , X, 278, 0 , Z ),"& " 244 (LV_BC_7, PB_D(52) , bidir , X, 278, 0 , Z ),"& " 243 (LV_BC_7, PB_D(45) , bidir , X, 278, 0 , Z ),"& " 242 (BC_2 , * , control , 0 ),"& " 241 (LV_BC_7, INT_b(5) , bidir , X, 242, 0 , Z ),"& " 240 (LV_BC_7, PB_D(36) , bidir , X, 259, 0 , Z ),"& " 239 (LV_BC_7, PB_D(13) , bidir , X, 259, 0 , Z ),"& " 238 (LV_BC_7, PB_D(44) , bidir , X, 259, 0 , Z ),"& " 237 (LV_BC_7, PB_D(28) , bidir , X, 259, 0 , Z ),"& " 236 (LV_BC_7, PB_D(12) , bidir , X, 259, 0 , Z ),"& " 235 (LV_BC_7, PB_D(35) , bidir , X, 260, 0 , Z ),"& " 234 (BC_2 , * , control , 0 ),"& " 233 (LV_BC_7, INT_b(3) , bidir , X, 234, 0 , Z ),"& " 232 (LV_BC_7, PB_BG2_b , bidir , X, 295, 0 , Z ),"& " 231 (LV_BC_7, PB_D(43) , bidir , X, 259, 0 , Z ),"& " 230 (LV_BC_7, PB_D(51) , bidir , X, 225, 0 , Z ),"& " 229 (BC_2 , * , control , 0 ),"& " 228 (LV_BC_7, INT_b(2) , bidir , X, 229, 0 , Z ),"& " 227 (BC_2 , * , control , 0 ),"& " 226 (LV_BC_7, INT_b(1) , bidir , X, 227, 0 , Z ),"& " 225 (BC_2 , * , control , 0 ),"& " 224 (LV_BC_7, PB_D(3) , bidir , X, 246, 0 , Z ),"& " 223 (LV_BC_7, PB_D(11) , bidir , X, 225, 0 , Z ),"& " 222 (BC_2 , * , control , 0 ),"& " 221 (LV_BC_7, PB_CLK , bidir , X, 222, 0 , Z ),"& " 220 (LV_BC_7, PB_D(59) , bidir , X, 225, 0 , Z ),"& " 219 (LV_BC_7, PB_D(4) , bidir , X, 200, 0 , Z ),"& " 218 (BC_2 , * , control , 0 ),"& " 217 (LV_BC_7, PB_D(42) , bidir , X, 225, 0 , Z ),"& " 216 (LV_BC_7, PB_D(19) , bidir , X, 225, 0 , Z ),"& " 215 (LV_BC_7, PB_D(26) , bidir , X, 218, 0 , Z ),"& " 214 (BC_2 , * , control , 0 ),"& " 213 (LV_BC_7, PB_DBB_b , bidir , X, 214, 0 , Z ),"& " 212 (LV_BC_7, PB_D(57) , bidir , X, 218, 0 , Z ),"& " 211 (LV_BC_7, PB_D(50) , bidir , X, 225, 0 , Z ),"& " 210 (LV_BC_7, PB_D(58) , bidir , X, 218, 0 , Z ),"& " 209 (LV_BC_7, PB_D(27) , bidir , X, 225, 0 , Z ),"& " 208 (LV_BC_7, PB_D(34) , bidir , X, 218, 0 , Z ),"& " 207 (BC_2 , * , control , 0 ),"& " 206 (LV_BC_7, INT_b(0) , bidir , X, 207, 0 , Z ),"& " 205 (LV_BC_7, PB_D(18) , bidir , X, 218, 0 , Z ),"& " 204 (LV_BC_7, PB_D(10) , bidir , X, 218, 0 , Z ),"& " 203 (LV_BC_7, PB_D(25) , bidir , X, 202, 0 , Z ),"& " 202 (BC_2 , * , control , 0 ),"& " 201 (LV_BC_7, PB_D(2) , bidir , X, 218, 0 , Z ),"& " 200 (BC_2 , * , control , 0 ),"& " 199 (LV_BC_7, PB_D(1) , bidir , X, 202, 0 , Z ),"& " 198 (BC_2 , * , control , 0 ),"& " 197 (LV_BC_7, PB_ABB_b , bidir , X, 198, 0 , Z ),"& " 196 (LV_BC_7, PB_D(49) , bidir , X, 218, 0 , Z ),"& " 195 (LV_BC_7, PB_FAST , bidir , X, 222, 0 , Z ),"& " 194 (LV_BC_7, PB_RSTCONF_b , bidir , X, 222, 0 , Z ),"& " 193 (LV_BC_7, PB_D(41) , bidir , X, 202, 0 , Z ),"& " 192 (LV_BC_7, PO_RST_b , bidir , X, 222, 0 , Z ),"& " 191 (LV_BC_7, PB_D(17) , bidir , X, 202, 0 , Z ),"& " 190 (LV_BC_7, PB_D(9) , bidir , X, 202, 0 , Z ),"& " 189 (LV_BC_7, PB_D(33) , bidir , X, 202, 0 , Z ),"& " 188 (LV_BC_7, PB_D(56) , bidir , X, 202, 0 , Z ),"& " 187 (LV_BC_7, PB_D(48) , bidir , X, 202, 0 , Z ),"& " 186 (BC_2 , * , control , 0 ),"& " 185 (LV_BC_7, PB_RST_b , bidir , X, 186, 0 , Z ),"& " 184 (LV_BC_7, PB_D(40) , bidir , X, 200, 0 , Z ),"& " 183 (LV_BC_7, PB_D(32) , bidir , X, 200, 0 , Z ),"& " 182 (LV_BC_7, PB_D(16) , bidir , X, 200, 0 , Z ),"& " 181 (LV_BC_7, PB_D(8) , bidir , X, 200, 0 , Z ),"& " 180 (LV_BC_7, PB_D(0) , bidir , X, 200, 0 , Z ),"& " 179 (BC_2 , * , control , 0 ),"& " 178 (LV_BC_7, PB_DP(5) , bidir , X, 179, 0 , Z ),"& " 177 (LV_BC_7, PB_DP(6) , bidir , X, 179, 0 , Z ),"& " 176 (LV_BC_7, PB_DP(2) , bidir , X, 179, 0 , Z ),"& " 175 (LV_BC_7, PB_DP(3) , bidir , X, 179, 0 , Z ),"& " 174 (LV_BC_7, PB_D(63) , bidir , X, 200, 0 , Z ),"& " 173 (LV_BC_7, PB_D(24) , bidir , X, 200, 0 , Z ),"& " 172 (LV_BC_7, PB_DP(0) , bidir , X, 179, 0 , Z ),"& " 171 (LV_BC_7, PB_DP(7) , bidir , X, 179, 0 , Z ),"& " 170 (LV_BC_7, PB_DP(4) , bidir , X, 179, 0 , Z ),"& " 169 (LV_BC_7, PB_DP(1) , bidir , X, 179, 0 , Z ),"& " 168 (BC_2 , * , control , 0 ),"& " 167 (LV_BC_7, PCI_GNT_b(7) , bidir , X, 168, 0 , Z ),"& " 166 (BC_2 , * , control , 0 ),"& " 165 (BC_2 , * , control , 0 ),"& " 164 (LV_BC_7, P1_AD(31) , bidir , X, 165, 0 , Z ),"& " 163 (LV_BC_7, P1_AD(28) , bidir , X, 165, 0 , Z ),"& " 162 (LV_BC_7, PCI_REQ_b(7) , bidir , X, 166, 0 , Z ),"& " 161 (BC_2 , * , control , 0 ),"& " 160 (LV_BC_7, P1_RST_b , bidir , X, 161, 0 , Z ),"& " 159 (LV_BC_7, P1_AD(30) , bidir , X, 165, 0 , Z ),"& " 158 (LV_BC_7, P1_AD(29) , bidir , X, 165, 0 , Z ),"& " 157 (LV_BC_7, P1_AD(27) , bidir , X, 165, 0 , Z ),"& " 156 (LV_BC_7, P1_AD(26) , bidir , X, 165, 0 , Z ),"& " 155 (BC_2 , * , control , 0 ),"& " 154 (LV_BC_7, P1_CBE(3) , bidir , X, 155, 0 , Z ),"& " 153 (LV_BC_7, P1_AD(24) , bidir , X, 165, 0 , Z ),"& " 152 (LV_BC_7, P1_AD(25) , bidir , X, 165, 0 , Z ),"& " 151 (BC_2 , * , control , 0 ),"& " 150 (LV_BC_7, P1_AD(23) , bidir , X, 151, 0 , Z ),"& " 149 (LV_BC_7, P1_AD(20) , bidir , X, 151, 0 , Z ),"& " 148 (LV_BC_7, P1_AD(21) , bidir , X, 151, 0 , Z ),"& " 147 (LV_BC_7, P1_AD(16) , bidir , X, 151, 0 , Z ),"& " 146 (LV_BC_7, P1_AD(17) , bidir , X, 151, 0 , Z ),"& " 145 (LV_BC_7, P1_AD(18) , bidir , X, 151, 0 , Z ),"& " 144 (BC_2 , * , control , 0 ),"& " 143 (LV_BC_7, P1_IRDY_b , bidir , X, 144, 0 , Z ),"& " 142 (BC_2 , * , control , 0 ),"& " 141 (LV_BC_7, P1_FRAME_b , bidir , X, 142, 0 , Z ),"& " 140 (BC_2 , * , control , 0 ),"& " 139 (LV_BC_7, P1_PERR_b , bidir , X, 140, 0 , Z ),"& " 138 (BC_2 , * , control , 0 ),"& " 137 (LV_BC_7, P1_STOP_b , bidir , X, 138, 0 , Z ),"& " 136 (BC_2 , * , control , 0 ),"& " 135 (LV_BC_7, P1_AD(14) , bidir , X, 136, 0 , Z ),"& " 134 (LV_BC_7, P1_AD(22) , bidir , X, 151, 0 , Z ),"& " 133 (LV_BC_7, P1_AD(15) , bidir , X, 136, 0 , Z ),"& " 132 (BC_2 , * , control , 0 ),"& " 131 (LV_BC_7, P1_DEVSEL_b , bidir , X, 132, 0 , Z ),"& " 130 (LV_BC_7, P1_AD(19) , bidir , X, 151, 0 , Z ),"& " 129 (LV_BC_7, P1_AD(13) , bidir , X, 136, 0 , Z ),"& " 128 (BC_2 , * , control , 0 ),"& " 127 (LV_BC_7, PCI_GNT_b(6) , bidir , X, 128, 0 , Z ),"& " 126 (LV_BC_7, P1_CBE(2) , bidir , X, 155, 0 , Z ),"& " 125 (LV_BC_7, P1_CBE(1) , bidir , X, 155, 0 , Z ),"& " 124 (LV_BC_7, P1_AD(10) , bidir , X, 136, 0 , Z ),"& " 123 (BC_2 , * , control , 0 ),"& " 122 (LV_BC_7, P1_TRDY_b , bidir , X, 123, 0 , Z ),"& " 121 (LV_BC_7, P1_AD(11) , bidir , X, 136, 0 , Z ),"& " 120 (BC_2 , * , control , 0 ),"& " 119 (LV_BC_7, P1_INTA_b , bidir , X, 120, 0 , Z ),"& " 118 (BC_2 , * , control , 0 ),"& " 117 (LV_BC_7, P1_PAR , bidir , X, 118, 0 , Z ),"& " 116 (BC_2 , * , control , 0 ),"& " 115 (LV_BC_7, P1_GNT_b(4) , bidir , X, 116, 0 , Z ),"& " 114 (BC_2 , * , control , 0 ),"& " 113 (LV_BC_7, P1_AD(7) , bidir , X, 136, 0 , Z ),"& " 112 (LV_BC_7, P1_AD(12) , bidir , X, 114, 0 , Z ),"& " 111 (LV_BC_7, P1_CBE(0) , bidir , X, 155, 0 , Z ),"& " 110 (LV_BC_7, P1_AD(5) , bidir , X, 136, 0 , Z ),"& " 109 (BC_2 , * , control , 0 ),"& " 108 (LV_BC_7, PCI_GNT_b(5) , bidir , X, 109, 0 , Z ),"& " 107 (LV_BC_7, P1_AD(3) , bidir , X, 114, 0 , Z ),"& " 106 (LV_BC_7, P1_AD(8) , bidir , X, 114, 0 , Z ),"& " 105 (LV_BC_7, P1_AD(9) , bidir , X, 114, 0 , Z ),"& " 104 (LV_BC_7, P1_AD(1) , bidir , X, 114, 0 , Z ),"& " 103 (LV_BC_7, P1_AD(4) , bidir , X, 114, 0 , Z ),"& " 102 (LV_BC_7, P1_AD(6) , bidir , X, 114, 0 , Z ),"& " 101 (LV_BC_7, PCI_REQ_b(6) , bidir , X, 166, 0 , Z ),"& " 100 (LV_BC_7, P1_AD(2) , bidir , X, 136, 0 , Z ),"& " 99 (LV_BC_7, P1_AD(0) , bidir , X, 114, 0 , Z ),"& " 98 (LV_BC_7, P1_REQ_b(2) , bidir , X, 166, 0 , Z ),"& " 97 (BC_2 , * , control , 0 ),"& " 96 (LV_BC_7, PCI_REQ_b(5) , bidir , X, 97 , 0 , Z ),"& " 95 (LV_BC_7, P1_64EN_b , bidir , X, 97 , 0 , Z ),"& " 94 (LV_BC_7, P1_CLK , bidir , X, 97 , 0 , Z ),"& " 93 (BC_2 , * , control , 0 ),"& " 92 (LV_BC_7, P1_GNT_b(1) , bidir , X, 93 , 0 , Z ),"& " 91 (BC_2 , * , control , 0 ),"& " 90 (LV_BC_7, P1_GNT_b(3) , bidir , X, 91 , 0 , Z ),"& " 89 (BC_2 , * , control , 0 ),"& " 88 (LV_BC_7, P1_ACK64_b , bidir , X, 89 , 0 , Z ),"& " 87 (BC_2 , * , control , 0 ),"& " 86 (LV_BC_7, P1_REQ64_b , bidir , X, 87 , 0 , Z ),"& " 85 (BC_2 , * , control , 0 ),"& " 84 (LV_BC_7, P1_REQ_b(1) , bidir , X, 85 , 0 , Z ),"& " 83 (LV_BC_7, P1_GNT_b(2) , bidir , X, 91 , 0 , Z ),"& " 82 (BC_2 , * , control , 0 ),"& " 81 (LV_BC_7, P1_CBE(7) , bidir , X, 82 , 0 , Z ),"& " 80 (LV_BC_7, P1_CBE(5) , bidir , X, 82 , 0 , Z ),"& " 79 (BC_2 , * , control , 0 ),"& " 78 (LV_BC_7, ENUM_b , bidir , X, 79 , 0 , Z ),"& " 77 (LV_BC_7, P1_CBE(4) , bidir , X, 82 , 0 , Z ),"& " 76 (BC_2 , * , control , 0 ),"& " 75 (LV_BC_7, P1_AD(61) , bidir , X, 76 , 0 , Z ),"& " 74 (BC_2 , * , control , 0 ),"& " 73 (LV_BC_7, P1_PAR64 , bidir , X, 74 , 0 , Z ),"& " 72 (LV_BC_7, P1_CBE(6) , bidir , X, 82 , 0 , Z ),"& " 71 (LV_BC_7, P1_AD(63) , bidir , X, 63 , 0 , Z ),"& " 70 (LV_BC_7, P1_AD(60) , bidir , X, 63 , 0 , Z ),"& " 69 (LV_BC_7, P1_AD(58) , bidir , X, 63 , 0 , Z ),"& " 68 (LV_BC_7, P1_AD(62) , bidir , X, 76 , 0 , Z ),"& " 67 (LV_BC_7, P1_IDSEL , bidir , X, 97 , 0 , Z ),"& " 66 (LV_BC_7, P1_REQ_b(3) , bidir , X, 97 , 0 , Z ),"& " 65 (LV_BC_7, P1_AD(59) , bidir , X, 76 , 0 , Z ),"& " 64 (LV_BC_7, P1_REQ_b(4) , bidir , X, 97 , 0 , Z ),"& " 63 (BC_2 , * , control , 0 ),"& " 62 (LV_BC_7, P1_AD(52) , bidir , X, 63 , 0 , Z ),"& " 61 (LV_BC_7, P1_AD(57) , bidir , X, 63 , 0 , Z ),"& " 60 (LV_BC_7, P1_AD(56) , bidir , X, 63 , 0 , Z ),"& " 59 (LV_BC_7, P1_M66EN , bidir , X, 97 , 0 , Z ),"& " 58 (LV_BC_7, P1_AD(55) , bidir , X, 76 , 0 , Z ),"& " 57 (LV_BC_7, P1_AD(54) , bidir , X, 56 , 0 , Z ),"& " 56 (BC_2 , * , control , 0 ),"& " 55 (LV_BC_7, P1_AD(47) , bidir , X, 56 , 0 , Z ),"& " 54 (LV_BC_7, P1_AD(51) , bidir , X, 63 , 0 , Z ),"& " 53 (LV_BC_7, P1_AD(50) , bidir , X, 63 , 0 , Z ),"& " 52 (LV_BC_7, P1_AD(53) , bidir , X, 56 , 0 , Z ),"& " 51 (LV_BC_7, P1_AD(49) , bidir , X, 56 , 0 , Z ),"& " 50 (LV_BC_7, P1_AD(48) , bidir , X, 56 , 0 , Z ),"& " 49 (BC_2 , * , control , 0 ),"& " 48 (LV_BC_7, P1_SERR_b , bidir , X, 49 , 0 , Z ),"& " 47 (LV_BC_7, P1_AD(46) , bidir , X, 76 , 0 , Z ),"& " 46 (LV_BC_7, P1_AD(45) , bidir , X, 56 , 0 , Z ),"& " 45 (LV_BC_7, P1_AD(41) , bidir , X, 56 , 0 , Z ),"& " 44 (LV_BC_7, P1_AD(42) , bidir , X, 76 , 0 , Z ),"& " 43 (LV_BC_7, P1_AD(43) , bidir , X, 42 , 0 , Z ),"& " 42 (BC_2 , * , control , 0 ),"& " 41 (LV_BC_7, P1_AD(38) , bidir , X, 76 , 0 , Z ),"& " 40 (LV_BC_7, P1_AD(39) , bidir , X, 42 , 0 , Z ),"& " 39 (LV_BC_7, P1_AD(34) , bidir , X, 42 , 0 , Z ),"& " 38 (LV_BC_7, P1_AD(35) , bidir , X, 42 , 0 , Z ),"& " 37 (LV_BC_7, P1_AD(36) , bidir , X, 76 , 0 , Z ),"& " 36 (LV_BC_7, P1_AD(32) , bidir , X, 42 , 0 , Z ),"& " 35 (BC_2 , * , control , 0 ),"& " 34 (LV_BC_7, PB_A(31) , bidir , X, 35 , 0 , Z ),"& " 33 (LV_BC_7, P1_AD(33) , bidir , X, 42 , 0 , Z ),"& " 32 (LV_BC_7, PB_A(28) , bidir , X, 35 , 0 , Z ),"& " 31 (BC_2 , * , control , 0 ),"& " 30 (LV_BC_7, PB_CI_b , bidir , X, 31 , 0 , Z ),"& " 29 (LV_BC_7, PB_A(27) , bidir , X, 35 , 0 , Z ),"& " 28 (LV_BC_7, P1_AD(44) , bidir , X, 56 , 0 , Z ),"& " 27 (BC_2 , * , control , 0 ),"& " 26 (LV_BC_7, PB_DBG1_b , bidir , X, 27 , 0 , Z ),"& " 25 (LV_BC_7, PB_A(24) , bidir , X, 13 , 0 , Z ),"& " 24 (LV_BC_7, P1_AD(40) , bidir , X, 42 , 0 , Z ),"& " 23 (LV_BC_7, PB_A(21) , bidir , X, 35 , 0 , Z ),"& " 22 (LV_BC_7, PB_A(26) , bidir , X, 35 , 0 , Z ),"& " 21 (LV_BC_7, P1_AD(37) , bidir , X, 42 , 0 , Z ),"& " 20 (LV_BC_7, PB_A(29) , bidir , X, 35 , 0 , Z ),"& " 19 (LV_BC_7, PB_A(22) , bidir , X, 13 , 0 , Z ),"& " 18 (LV_BC_7, PB_A(25) , bidir , X, 35 , 0 , Z ),"& " 17 (LV_BC_7, P1_RST_DIR , bidir , X, 97 , 0 , Z ),"& " 16 (LV_BC_7, PB_A(18) , bidir , X, 13 , 0 , Z ),"& " 15 (BC_2 , * , control , 0 ),"& " 14 (LV_BC_7, PB_GBL_b , bidir , X, 15 , 0 , Z ),"& " 13 (BC_2 , * , control , 0 ),"& " 12 (LV_BC_7, PB_A(16) , bidir , X, 13 , 0 , Z ),"& " 11 (BC_2 , * , control , 0 ),"& " 10 (LV_BC_7, PB_BR1_b , bidir , X, 11 , 0 , Z ),"& " 9 (LV_BC_7, PB_A(30) , bidir , X, 35 , 0 , Z ),"& " 8 (LV_BC_7, PB_DBG2_b , bidir , X, 27 , 0 , Z ),"& " 7 (LV_BC_7, PB_A(23) , bidir , X, 13 , 0 , Z ),"& " 6 (LV_BC_7, PB_A(14) , bidir , X, 334, 0 , Z ),"& " 5 (LV_BC_7, PB_A(15) , bidir , X, 13 , 0 , Z ),"& " 4 (LV_BC_7, PB_A(19) , bidir , X, 13 , 0 , Z ),"& " 3 (LV_BC_7, PB_A(17) , bidir , X, 334, 0 , Z ),"& " 2 (LV_BC_7, PB_A(20) , bidir , X, 13 , 0 , Z ),"& " 1 (LV_BC_7, PB_A(12) , bidir , X, 334, 0 , Z ),"& " 0 (LV_BC_7, PB_A(13) , bidir , X, 334, 0 , Z ) "; end pspan; -- package LVS_BSCAN_CELLS is -- use STD_1149_1_1994.all; -- constant LV_BC_7: CELL_INFO; -- -- end LVS_BSCAN_CELLS; -- package body LVS_BSCAN_CELLS is -- use STD_1149_1_1994.all; -- constant LV_BC_7: CELL_INFO := -- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO), -- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI), -- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI)); -- -- end LVS_BSCAN_CELLS;