-- Generated by boundaryScanGenerate 3.2 on 11/30/00 17:57:00 -- BSDL Version 1994 -- ********************************************************************** -- -- IMPORTANT NOTICE -- -- This information is for modeling purposes only, and is not guaranteed. -- -- This information is provided "as is" without warranty of any kind. -- It may contain technical inaccuracies or typographical errors. -- -- ZARLINK and MT92220 are trademarks of ZARLINK Semiconductor. ZARLINK -- products, marketed under trademarks, are protected under numerous US -- and foreign patents and pending applications, maskwork rights, and -- copyrights. -- -- ZARLINK reserves the right to make changes to any products and -- services at any time without notice. ZARLINK assumes no -- responsibility or liability arising out of the application or use of -- any information, product, or service described herein except as -- expressly agreed to in writing by ZARLINK Corporation. ZARLINK -- customers are advised to obtain the latest version of device -- specifications before relying on any published information and before -- placing orders for products or services. -- -- ********************************************************************* -- ******************************************************************** -- Modification History: -- -- Last update: TL 2002/10/03 -- ******************************************************************** entity MT92220 is generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME"); port ( -- Port List tdi : in bit; vdd2 : linkage bit_vector( 23 downto 0 ); vdd5a : linkage bit_vector( 10 downto 0 ); ct_c8_a : inout bit; ct_netref1 : inout bit; sclk : out bit; c16n : out bit; tdo : out bit; ct_netref2 : inout bit; manufacturing_tm : in bit; tck : in bit; frcomp : out bit; sclkx2 : out bit; ct_frame_b : inout bit; c2 : out bit; ct_frame_a : inout bit; txa_led : inout bit; c4 : out bit; ct_mc : inout bit; h100pll_pllvss : linkage bit; h100pll_pllvdd : linkage bit; proc_out : linkage bit; ct_d_0 : inout bit; ct_d_1 : inout bit; ct_d_2 : inout bit; ct_d_3 : inout bit; ct_d_4 : inout bit; ct_d_5 : inout bit; ct_d_6 : inout bit; ct_d_7 : inout bit; ct_d_8 : inout bit; ct_d_9 : inout bit; ct_d_10 : inout bit; ct_d_11 : inout bit; ct_d_12 : inout bit; ct_d_13 : inout bit; ct_d_14 : inout bit; ct_d_15 : inout bit; ct_d_16 : inout bit; ct_d_17 : inout bit; ct_d_18 : inout bit; ct_d_19 : inout bit; ct_d_20 : inout bit; ct_d_21 : inout bit; ct_d_22 : inout bit; ct_d_23 : inout bit; ct_d_24 : inout bit; ct_d_25 : inout bit; ct_d_26 : inout bit; ct_d_27 : inout bit; ct_d_28 : inout bit; ct_d_29 : inout bit; ct_d_30 : inout bit; ct_d_31 : inout bit; dis_cap_0 : in bit; dis_cap_1 : in bit; iddtn : in bit; tms : in bit; memc_cas_0 : out bit; memc_cas_1 : out bit; memc_a_0 : out bit; memc_a_1 : out bit; memc_a_2 : out bit; memc_a_3 : out bit; memc_a_4 : out bit; memc_a_5 : out bit; memc_a_6 : out bit; memc_a_7 : out bit; memc_a_8 : out bit; memc_a_9 : out bit; memc_a_10 : out bit; memc_a_11 : out bit; memc_a_12 : out bit; memc_a_13 : out bit; memc_a_14 : out bit; memc_a_15 : out bit; memc_a_16 : out bit; memc_a_17 : out bit; memc_we_0 : out bit; memc_we_1 : out bit; memc_d_0 : inout bit; memc_d_1 : inout bit; memc_d_2 : inout bit; memc_d_3 : inout bit; memc_d_4 : inout bit; memc_d_5 : inout bit; memc_d_6 : inout bit; memc_d_7 : inout bit; memc_d_8 : inout bit; memc_d_9 : inout bit; memc_d_10 : inout bit; memc_d_11 : inout bit; memc_d_12 : inout bit; memc_d_13 : inout bit; memc_d_14 : inout bit; memc_d_15 : inout bit; memc_d_16 : inout bit; memc_d_17 : inout bit; memc_d_18 : inout bit; memc_d_19 : inout bit; memc_d_20 : inout bit; memc_d_21 : inout bit; memc_d_22 : inout bit; memc_d_23 : inout bit; memc_d_24 : inout bit; memc_d_25 : inout bit; memc_d_26 : inout bit; memc_d_27 : inout bit; memc_d_28 : inout bit; memc_d_29 : inout bit; memc_d_30 : inout bit; memc_d_31 : inout bit; memc_p_0 : inout bit; memc_p_1 : inout bit; memc_p_2 : inout bit; memc_p_3 : inout bit; memc_bws_0 : out bit; memc_bws_1 : out bit; memc_bws_2 : out bit; memc_bws_3 : out bit; memc_rw : out bit; mem_clk_net_i : in bit; memc_cs_0 : out bit; memc_cs_1 : out bit; memc_cs_2 : out bit; memc_cs_3 : out bit; mem_clk_net_o : out bit; fc2pll_pllvss : linkage bit; fc2pll_pllvdd : linkage bit; memc_ras : out bit; memb_a_0 : out bit; memb_a_1 : out bit; memb_a_2 : out bit; memb_a_3 : out bit; memb_a_4 : out bit; memb_a_5 : out bit; memb_a_6 : out bit; memb_a_7 : out bit; memb_a_8 : out bit; memb_a_9 : out bit; memb_a_10 : out bit; memb_a_11 : out bit; memb_a_12 : out bit; memb_a_13 : out bit; memb_a_14 : out bit; memb_a_15 : out bit; memb_a_16 : out bit; memb_a_17 : out bit; memb_a_18 : out bit; memb_cs_0 : out bit; memb_cs_1 : out bit; memb_cs_2 : out bit; memb_cs_3 : out bit; mem_oe : out bit; memb_bws_0 : out bit; memb_bws_1 : out bit; memb_d_0 : inout bit; memb_d_1 : inout bit; memb_d_2 : inout bit; memb_d_3 : inout bit; memb_d_4 : inout bit; memb_d_5 : inout bit; memb_d_6 : inout bit; memb_d_7 : inout bit; memb_d_8 : inout bit; memb_d_9 : inout bit; memb_d_10 : inout bit; memb_d_11 : inout bit; memb_d_12 : inout bit; memb_d_13 : inout bit; memb_d_14 : inout bit; memb_d_15 : inout bit; memb_p_0 : inout bit; memb_p_1 : inout bit; memb_rw : out bit; nreset : in bit; trst : in bit; mem_clk_sar_o : out bit; icptn : in bit; mem_clk_sar_i : in bit; mema_a_0 : out bit; mema_a_1 : out bit; mema_a_2 : out bit; mema_a_3 : out bit; mema_a_4 : out bit; mema_a_5 : out bit; mema_a_6 : out bit; mema_a_7 : out bit; mema_a_8 : out bit; mema_a_9 : out bit; mema_a_10 : out bit; mema_a_11 : out bit; mema_a_12 : out bit; mema_a_13 : out bit; mema_a_14 : out bit; mema_a_15 : out bit; mema_a_16 : out bit; mema_a_17 : out bit; mema_a_18 : out bit; mema_cs_0 : out bit; mema_cs_1 : out bit; mema_cs_2 : out bit; mema_cs_3 : out bit; mema_rw : out bit; mema_bws_0 : out bit; mema_bws_1 : out bit; mema_d_0 : inout bit; mema_d_1 : inout bit; mema_d_2 : inout bit; mema_d_3 : inout bit; mema_d_4 : inout bit; mema_d_5 : inout bit; mema_d_6 : inout bit; mema_d_7 : inout bit; mema_d_8 : inout bit; mema_d_9 : inout bit; mema_d_10 : inout bit; mema_d_11 : inout bit; mema_d_12 : inout bit; mema_d_13 : inout bit; mema_d_14 : inout bit; mema_d_15 : inout bit; mema_p_0 : inout bit; mema_p_1 : inout bit; rxa_led : inout bit; fc1pll_pllvdd : linkage bit; fc1pll_pllvss : linkage bit; rxa_addr2 : in bit; rxa_addr4 : in bit; txa_addr1 : in bit; txa_addr4 : inout bit; txa_addr0 : in bit; rxa_addr3 : in bit; rxa_addr0 : in bit; rxa_addr1 : in bit; txa_addr2 : in bit; txa_addr3 : inout bit; cpu_mode_0 : in bit; cpu_mode_1 : in bit; cpu_mode_2 : in bit; cpu_mode_3 : in bit; etha_rx_d_0 : in bit; etha_rx_d_1 : in bit; etha_rx_d_2 : in bit; etha_rx_d_3 : in bit; etha_tx_en : out bit; etha_rx_er : in bit; rxa_alarm : in bit; ethab_tx_d_0 : out bit; ethab_tx_d_1 : out bit; ethab_tx_d_2 : out bit; ethab_tx_d_3 : out bit; etha_rx_clk : in bit; txa_enb : out bit; etha_col : in bit; upclk : in bit; etha_tx_clk : in bit; etha_crs : in bit; etha_rx_dv : in bit; txb_soc : out bit; txb_d_0 : out bit; txb_d_1 : out bit; txb_d_2 : out bit; txb_d_3 : out bit; txb_d_4 : out bit; txb_d_5 : out bit; txb_d_6 : out bit; txb_d_7 : out bit; txb_enb : out bit; txb_clk : inout bit; txb_clav : in bit; txb_prty : out bit; rxb_enb : out bit; rxb_clk : inout bit; rxb_prty : in bit; rxb_d_0 : in bit; rxb_d_1 : in bit; rxb_d_2 : in bit; rxb_d_3 : in bit; rxb_d_4 : in bit; rxb_d_5 : in bit; rxb_d_6 : in bit; rxb_d_7 : in bit; rxb_soc : in bit; rxb_clav : in bit; txa_d_0 : out bit; txa_d_1 : out bit; txa_d_2 : out bit; txa_d_3 : out bit; txa_d_4 : out bit; txa_d_5 : out bit; txa_d_6 : out bit; txa_d_7 : out bit; txa_d_8 : out bit; txa_d_9 : out bit; txa_d_10 : out bit; txa_d_11 : out bit; txa_d_12 : out bit; txa_d_13 : out bit; txa_d_14 : out bit; txa_d_15 : out bit; txa_prty : out bit; txa_clk : inout bit; txa_soc : out bit; vss : linkage bit_vector( 99 downto 0 ); rxa_d_0 : in bit; rxa_d_1 : in bit; rxa_d_2 : in bit; rxa_d_3 : in bit; rxa_d_4 : in bit; rxa_d_5 : in bit; rxa_d_6 : in bit; rxa_d_7 : in bit; rxa_d_8 : in bit; rxa_d_9 : in bit; rxa_d_10 : in bit; rxa_d_11 : in bit; rxa_d_12 : in bit; rxa_d_13 : in bit; rxa_d_14 : in bit; rxa_d_15 : in bit; rxa_clav : in bit; vdd4 : linkage bit_vector( 75 downto 0 ); rxa_clk : inout bit; rxa_enb : out bit; txa_clav : in bit; rxa_soc : in bit; rxa_prty : in bit; cpu_a_0 : in bit; cpu_a_1 : in bit; cpu_a_2 : in bit; cpu_a_3 : in bit; cpu_a_4 : in bit; cpu_a_5 : in bit; cpu_a_6 : in bit; cpu_a_7 : in bit; cpu_a_8 : in bit; cpu_a_9 : in bit; cpu_a_10 : in bit; cpu_a_11 : in bit; cpu_a_12 : in bit; cpu_a_13 : in bit; cpu_a_14 : in bit; cpu_ale : in bit; cpu_a_das : inout bit; cpu_wr_rw : in bit; cpu_cs : inout bit; cpu_rd_ds : in bit; cpu_rdy_ndtack : inout bit; cpu_d_0 : inout bit; cpu_d_1 : inout bit; cpu_d_2 : inout bit; cpu_d_3 : inout bit; cpu_d_4 : inout bit; cpu_d_5 : inout bit; cpu_d_6 : inout bit; cpu_d_7 : inout bit; cpu_d_8 : inout bit; cpu_d_9 : inout bit; cpu_d_10 : inout bit; cpu_d_11 : inout bit; cpu_d_12 : inout bit; cpu_d_13 : inout bit; cpu_d_14 : inout bit; cpu_d_15 : inout bit; cpu_int_0 : out bit; cpu_int_1 : out bit; gpio_0 : inout bit; gpio_1 : inout bit; gpio_2 : inout bit; gpio_3 : inout bit; gpio_4 : inout bit; gpio_5 : inout bit; gpio_6 : inout bit; gpio_7 : inout bit; pll_clk : in bit; c16p : out bit; ct_c8_b : inout bit); use STD_1149_1_1994.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of MT92220: entity is "STD_1149_1_1993"; --Pin mappings attribute PIN_MAP of MT92220: entity is PHYSICAL_PIN_MAP; constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := "tdi : AD01 , " & "vdd2 : (AD03, AH03, AG11, AG15, AG17, AG20, AH27, "& "AG29, AD27, U27, P27, J27, H26, B22, D21, "& "A15, D14, C07, B05, F05, L04, P04, U04, Y03), "& --vdd2[0] - vdd[23] "vdd5a : (AC05, AG06, AG09, AH11, AH15, "& "D17, B11, A06, F04, M04, Y01), "& "ct_c8_a : AD02 , " & "ct_netref1 : AD04 , " & "sclk : AE01 , " & "c16n : AE02 , " & "tdo : AE04 , " & "ct_netref2 : AD05 , " & "manufacturing_tm : AG03 , " & "tck : AF01 , " & "frcomp : AF04 , " & "sclkx2 : AF02 , " & "ct_frame_b : AG01 , " & "c2 : AF05 , " & "ct_frame_a : AG02 , " & "txa_led : AE05 , " & "c4 : AH01 , " & "ct_mc : AH02 , " & "fc1pll_pllvss : AJ03 , " & "fc1pll_pllvdd : AK03 , " & "proc_out : AK04 , " & "ct_d_26 : AJ05 , " & "ct_d_21 : AG05 , " & "ct_d_30 : AK05 , " & "ct_d_28 : AF07 , " & "ct_d_23 : AJ06 , " & "ct_d_25 : AK06 , " & "ct_d_20 : AG07 , " & "ct_d_31 : AJ07 , " & "ct_d_19 : AF08 , " & "ct_d_22 : AK07 , " & "ct_d_29 : AJ08 , " & "ct_d_18 : AH08 , " & "ct_d_27 : AK08 , " & "ct_d_24 : AF09 , " & "ct_d_15 : AJ09 , " & "ct_d_17 : AK09 , " & "ct_d_12 : AF10 , " & "ct_d_10 : AJ10 , " & "ct_d_14 : AF11 , " & "ct_d_6 : AG10 , " & "ct_d_16 : AK10 , " & "ct_d_11 : AJ11 , " & "ct_d_13 : AF12 , " & "ct_d_9 : AK11 , " & "ct_d_2 : AG13 , " & "ct_d_5 : AJ12 , " & "ct_d_8 : AF13 , " & "ct_d_7 : AK12 , " & "ct_d_1 : AJ13 , " & "ct_d_4 : AF14 , " & "ct_d_3 : AK13 , " & "ct_d_0 : AJ14 , " & "dis_cap_0 : AK14 , " & "iddtn : AH16 , " & "tms : AF15 , " & "dis_cap_1 : AJ15 , " & "memc_cas_0 : AG16 , " & "memc_a_8 : AK15 , " & "memc_a_5 : AK16 , " & "memc_a_9 : AJ16 , " & "memc_a_10 : AG18 , " & "memc_a_11 : AF16 , " & "memc_a_4 : AH19 , " & "memc_a_6 : AK17 , " & "memc_we_0 : AG19 , " & "memc_a_1 : AJ17 , " & "memc_a_2 : AK18 , " & "memc_a_7 : AF17 , " & "memc_d_15 : AH20 , " & "memc_a_13 : AJ18 , " & "memc_a_0 : AG21 , " & "memc_a_12 : AK19 , " & "memc_a_3 : AF18 , " & "memc_p_1 : AG22 , " & "memc_d_13 : AJ19 , " & "memc_d_3 : AH23 , " & "memc_d_12 : AK20 , " & "memc_d_10 : AF19 , " & "memc_d_8 : AG23 , " & "memc_d_9 : AJ20 , " & "memc_d_6 : AK21 , " & "memc_d_0 : AH24 , " & "memc_d_14 : AF20 , " & "memc_d_4 : AG24 , " & "memc_d_5 : AJ21 , " & "memc_d_11 : AF21 , " & "memc_d_2 : AK22 , " & "memc_bws_1 : AG25 , " & "memc_d_7 : AJ22 , " & "memc_rw : AF22 , " & "memc_bws_3 : AK23 , " & "mem_clk_net_i : AJ23 , " & "memc_d_1 : AK24 , " & "memc_cs_0 : AG26 , " & "memc_p_0 : AF23 , " & "mem_clk_net_o : AJ24 , " & "memc_a_16 : AK25 , " & "memc_bws_0 : AH28 , " & "memc_bws_2 : AJ25 , " & "memc_a_15 : AF24 , " & "memc_p_2 : AK26 , " & "memc_cs_1 : AK27 , " & "fc2pll_pllvdd : AJ26 , " & "fc2pll_pllvss : AF25 , " & "memc_d_19 : AH29 , " & "memc_d_22 : AH30 , " & "memc_d_17 : AE26 , " & "memc_a_17 : AG30 , " & "memc_d_20 : AD26 , " & "memc_d_26 : AE29 , " & "memc_a_14 : AF27 , " & "memc_d_23 : AE30 , " & "memc_d_16 : AD29 , " & "memc_d_28 : AG28 , " & "memc_d_30 : AC26 , " & "memc_d_27 : AD30 , " & "memc_d_25 : AE27 , " & "memc_d_18 : AC29 , " & "memc_d_21 : AC30 , " & "memc_d_24 : AB26 , " & "memc_cs_2 : AB29 , " & "memc_d_29 : AD28 , " & "memc_ras : AB30 , " & "memb_a_7 : AA26 , " & "memc_we_1 : AC27 , " & "memc_d_31 : AA29 , " & "memb_cs_3 : Y26 , " & "memc_p_3 : AC28 , " & "memc_cs_3 : AA30 , " & "memc_cas_1 : Y29 , " & "memb_cs_1 : AB27 , " & "memb_cs_0 : W26 , " & "memb_a_6 : Y27 , " & "mem_oe : Y30 , " & "memb_bws_0 : AA27 , " & "memb_bws_1 : W29 , " & "memb_a_18 : V26 , " & "memb_a_8 : W30 , " & "memb_cs_2 : Y28 , " & "memb_a_9 : V29 , " & "memb_d_7 : W27 , " & "memb_d_9 : U26 , " & "memb_p_0 : V30 , " & "memb_a_17 : W28 , " & "memb_d_8 : U29 , " & "memb_rw : V27 , " & "memb_d_6 : U30 , " & "memb_d_11 : T26 , " & "memb_d_4 : T29 , " & "memb_d_5 : T27 , " & "memb_d_10 : T30 , " & "nreset : T28 , " & "memb_d_12 : R30 , " & "trst : R28 , " & "memb_d_14 : R29 , " & "memb_p_1 : R26 , " & "memb_d_3 : R27 , " & "memb_d_2 : P30 , " & "memb_d_13 : P29 , " & "memb_d_0 : N30 , " & "memb_a_0 : N27 , " & "memb_a_2 : P26 , " & "memb_a_5 : M28 , " & "memb_a_3 : N29 , " & "memb_d_15 : M30 , " & "memb_d_1 : M27 , " & "memb_a_11 : N26 , " & "memb_a_13 : L28 , " & "memb_a_10 : M29 , " & "memb_a_4 : L30 , " & "memb_a_1 : K27 , " & "memb_a_15 : M26 , " & "mem_clk_sar_o : L29 , " & "icptn : K30 , " & "mem_clk_sar_i : L26 , " & "mema_a_9 : K29 , " & "memb_a_12 : H28 , " & "memb_a_14 : K26 , " & "mema_cs_2 : J30 , " & "mema_rw : H27 , " & "memb_a_16 : J29 , " & "mema_bws_0 : J26 , " & "mema_a_18 : G28 , " & "mema_a_17 : H30 , " & "mema_d_6 : H29 , " & "mema_cs_0 : G27 , " & "mema_d_11 : G30 , " & "mema_a_8 : F27 , " & "mema_p_0 : G29 , " & "mema_cs_1 : F30 , " & "mema_a_7 : D28 , " & "rxa_led : F29 , " & "mema_d_9 : G26 , " & "mema_bws_1 : E27 , " & "mema_a_6 : E30 , " & "mema_d_5 : E29 , " & "mema_d_8 : E26 , " & "mema_d_4 : D30 , " & "mema_d_7 : F26 , " & "mema_d_10 : C30 , " & "h100pll_pllvdd : D29 , " & "h100pll_pllvss : C29 , " & "mema_d_14 : B28 , " & "mema_cs_3 : B26 , " & "mema_p_1 : A28 , " & "mema_d_2 : A26 , " & "mema_a_4 : C28 , " & "mema_d_1 : E24 , " & "mema_a_2 : B25 , " & "mema_a_5 : D26 , " & "mema_d_15 : A25 , " & "mema_d_3 : B24 , " & "mema_a_0 : C27 , " & "mema_a_11 : E23 , " & "mema_a_1 : A24 , " & "mema_a_3 : D25 , " & "mema_d_12 : B23 , " & "mema_d_13 : A23 , " & "mema_a_13 : D24 , " & "mema_d_0 : E22 , " & "mema_a_10 : C24 , " & "mema_a_15 : A22 , " & "rxa_addr2 : E21 , " & "rxa_addr4 : D23 , " & "mema_a_12 : B21 , " & "txa_addr1 : E20 , " & "mema_a_14 : C23 , " & "txa_addr4 : A21 , " & "mema_a_16 : B20 , " & "txa_addr0 : D22 , " & "rxa_addr3 : E19 , " & "rxa_addr0 : A20 , " & "rxa_addr1 : D20 , " & "txa_addr2 : B19 , " & "txa_addr3 : E18 , " & "cpu_mode_0 : A19 , " & "cpu_mode_1 : C20 , " & "cpu_mode_2 : B18 , " & "cpu_mode_3 : D19 , " & "etha_rx_d_2 : E17 , " & "etha_tx_en : A18 , " & "etha_rx_er : C19 , " & "etha_rx_d_3 : B17 , " & "etha_rx_d_1 : A17 , " & "rxa_alarm : D18 , " & "ethab_tx_d_1 : E16 , " & "ethab_tx_d_0 : B16 , " & "ethab_tx_d_3 : D16 , " & "etha_rx_d_0 : A16 , " & "etha_rx_clk : E15 , " & "ethab_tx_d_2 : C16 , " & "txa_enb : B15 , " & "etha_col : D15 , " & "upclk : A14 , " & "etha_tx_clk : B14 , " & "etha_crs : C15 , " & "etha_rx_dv : E14 , " & "txb_soc : A13 , " & "txb_d_6 : D13 , " & "txb_enb : B13 , " & "txb_d_3 : C12 , " & "txb_clk : E13 , " & "txb_d_4 : A12 , " & "txb_d_7 : D12 , " & "txb_d_5 : B12 , " & "txb_d_2 : C11 , " & "txb_clav : E12 , " & "txb_d_0 : A11 , " & "txb_prty : D10 , " & "rxb_enb : E11 , " & "rxb_clk : D11 , " & "rxb_prty : A10 , " & "rxb_d_5 : B10 , " & "rxb_soc : D09 , " & "txb_d_1 : E10 , " & "rxb_d_0 : A09 , " & "rxb_clav : B09 , " & "rxb_d_3 : C08 , " & "rxb_d_2 : E09 , " & "rxb_d_7 : D08 , " & "rxb_d_6 : A08 , " & "txa_d_12 : B08 , " & "txa_d_9 : E08 , " & "txa_d_7 : A07 , " & "rxb_d_4 : D07 , " & "txa_prty : B07 , " & "rxb_d_1 : E07 , " & "txa_d_11 : C04 , " & "txa_clk : D05 , " & "txa_d_13 : B06 , " & "txa_soc : A05 , " & "txa_d_8 : B03 , " & "txa_d_10 : E06 , " & "txa_d_5 : A04 , " & "txa_d_14 : A03 , " & "txa_d_15 : B04 , " & "txa_d_6 : D04 , " & "vss : (A02, A29, AA03, AA28, AB03, AB28, AE03, AE28,"& "AF03, AF28, AG04, AG27, AH05, AH06, AH09, AH10,"& "AH13, AH14, AH17, AH18, AH21, AH22, AH25, AH26,"& "AJ01, AJ02, AJ29, AJ30, AK02, AK29, B01, B02, "& "B29, B30, C03, C05, C06, C09, C10, C13, C14, "& "C17, C18, C21, C22, C25, C26, D27, E03, E28,"& "F03, F28, J03, J28, K03, K28, N03, N13, N14, "& "N15, N16, N17, N18, N28, P03, P13, P14, P15, "& "P16, P17, P18, P28, R13, R14, R15, R16, R17, "& "R18, T13, T14, T15, T16, T17, T18, U03, U13, "& "U14, U15, U16, U17, U18, U28, V03, V13, V14, "& "V15, V16, V17, V18, V28),"& --vss[0] - vss[99] "txa_d_4 : D03 , " & "rxa_d_13 : D01 , " & "rxa_clav : C01 , " & "vdd4 : (AA25, AB06, AC06, AD25, AE08, AE09 , AE12, AE13,"& "AE16, AE17, AE20, AE21, AE24, AE25, F06, F07,"& "F10, F11, F14, F15, F18, F19, F22, F23, G06,"& "H25, J25, K06, L06, M25, N25, P06,R06, T25, U25,"& "V06, W06, Y25, AA06, AD06, AE06, H06, J06, M06, "& "N06, T06, U06, Y06, AE07, AE10, AE11, AE14, AE15,"& "AE18, AE19, AE22, AE23, AB25, AC25, F25, G25, K25,"& "L25, P25, R25, V25, W25, F08, F09, F12, F13, F16,"& "F17, F20, F21, F24), " & --vdd4[0] - vdd4[75] "txa_d_3 : E02 , " & "txa_d_1 : F02 , " & "rxa_d_15 : F01 , " & "rxa_clk : E04 , " & "rxa_enb : G05 , " & "txa_d_2 : G02 , " & "rxa_d_11 : G01 , " & "txa_clav : C02 , " & "rxa_d_14 : H05 , " & "txa_d_0 : H02 , " & "rxa_soc : H01 , " & "rxa_d_9 : G04 , " & "rxa_prty : J05 , " & "rxa_d_4 : J02 , " & "rxa_d_12 : G03 , " & "rxa_d_7 : J01 , " & "rxa_d_1 : K05 , " & "rxa_d_5 : H04 , " & "rxa_d_10 : K02 , " & "cpu_a_12 : K01 , " & "rxa_d_8 : H03 , " & "rxa_d_3 : L05 , " & "rxa_d_6 : L02 , " & "cpu_a_14 : J04 , " & "rxa_d_0 : L01 , " & "rxa_d_2 : M05 , " & "cpu_a_11 : M02 , " & "cpu_a_10 : K04 , " & "cpu_a_5 : M01 , " & "cpu_a_8 : N05 , " & "cpu_a_13 : L03 , " & "cpu_a_7 : N02 , " & "cpu_a_2 : N01 , " & "cpu_a_4 : P05 , " & "cpu_a_6 : M03 , " & "cpu_a_3 : P02 , " & "cpu_a_9 : N04 , " & "cpu_a_1 : P01 , " & "cpu_ale : R02 , " & "cpu_a_das : R01 , " & "cpu_wr_rw : R03 , " & "cpu_a_0 : T01 , " & "cpu_cs : T02 , " & "cpu_rd_ds : R04 , " & "cpu_rdy_ndtack : T05 , " & "cpu_d_12 : T03 , " & "cpu_d_14 : U01 , " & "cpu_d_15 : U02 , " & "cpu_d_13 : T04 , " & "cpu_d_11 : V01 , " & "cpu_d_7 : U05 , " & "cpu_d_9 : V02 , " & "cpu_d_6 : V04 , " & "cpu_d_10 : W01 , " & "cpu_d_4 : W03 , " & "cpu_d_8 : V05 , " & "cpu_d_5 : W02 , " & "cpu_int_1 : W04 , " & "cpu_d_3 : W05 , " & "cpu_d_1 : Y02 , " & "cpu_d_0 : AA04 , " & "gpio_3 : AA01 , " & "cpu_int_0 : Y05 , " & "gpio_7 : Y04 , " & "gpio_1 : AA02 , " & "gpio_4 : AA05 , " & "pll_clk : AB04 , " & "cpu_d_2 : AB01 , " & "c16p : AB02 , " & "gpio_6 : AB05 , " & "gpio_2 : AC03 , " & "ct_c8_b : AC01 , " & "gpio_5 : AC02 , " & "gpio_0 : AC04 " ; attribute TAP_SCAN_RESET of trst : signal is true; attribute TAP_SCAN_IN of tdi : signal is true; attribute TAP_SCAN_MODE of tms : signal is true; attribute TAP_SCAN_OUT of tdo : signal is true; attribute TAP_SCAN_CLOCK of tck : signal is (1.0000000000000000000e+07, BOTH); attribute COMPLIANCE_PATTERNS of MT92220 : entity is "(manufacturing_tm,iddtn,icptn) (001)"; attribute INSTRUCTION_LENGTH of MT92220: entity is 25; attribute INSTRUCTION_OPCODE of MT92220: entity is "IDCODE (1111111111111111111111110)," & "BYPASS (1111111111111111111111111)," & "EXTEST (0000000000000000000000000, 1111111111111111111101000)," & "SAMPLE (1111111111111111111111000)," & "HIGHZ (1111111111111111111001111)," & "CLAMP (1111111111111111111101111) " ; attribute INSTRUCTION_CAPTURE of MT92220: entity is "XXXXXXXXXXXXXXXXXXXXXXX01"; attribute IDCODE_REGISTER of MT92220: entity is "0100" & -- version "0000001111100001" & -- part number "00000110110" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of MT92220: entity is "BYPASS (HIGHZ, CLAMP) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of MT92220: entity is 546; attribute BOUNDARY_REGISTER of MT92220: entity is -- num cell port function safe [ccell disval rslt] " 545 (BC_2 , * , control , 1 ) ,"& " 544 (LV_BC_7 , ct_c8_a , bidir , X , 545 , 1 , Z ),"& " 543 (BC_2 , * , control , 1 ) ,"& " 542 (LV_BC_7 , ct_netref1 , bidir , X , 543 , 1 , Z ),"& " 541 (BC_2 , * , control , 1 ) ,"& " 540 (BC_2 , sclk , output3 , X , 541 , 1 , Z ),"& " 539 (BC_2 , c16n , output3 , X , 541 , 1 , Z ),"& " 538 (BC_2 , * , control , 1 ) ,"& " 537 (LV_BC_7 , ct_netref2 , bidir , X , 538 , 1 , Z ),"& " 536 (BC_2 , frcomp , output3 , X , 541 , 1 , Z ),"& " 535 (BC_2 , sclkx2 , output3 , X , 541 , 1 , Z ),"& " 534 (BC_2 , * , control , 1 ) ,"& " 533 (LV_BC_7 , ct_frame_b , bidir , X , 534 , 1 , Z ),"& " 532 (BC_2 , c2 , output3 , X , 541 , 1 , Z ),"& " 531 (LV_BC_7 , ct_frame_a , bidir , X , 545 , 1 , Z ),"& " 530 (BC_2 , * , control , 1 ) ,"& " 529 (LV_BC_7 , txa_led , bidir , X , 530 , 1 , Z ),"& " 528 (BC_2 , c4 , output3 , X , 541 , 1 , Z ),"& " 527 (BC_2 , * , control , 1 ) ,"& " 526 (LV_BC_7 , ct_mc , bidir , X , 527 , 1 , Z ),"& " 525 (BC_2 , * , control , 1 ) ,"& " 524 (LV_BC_7 , ct_d_26 , bidir , X , 525 , 1 , Z ),"& " 523 (BC_2 , * , control , 1 ) ,"& " 522 (LV_BC_7 , ct_d_21 , bidir , X , 523 , 1 , Z ),"& " 521 (BC_2 , * , control , 1 ) ,"& " 520 (LV_BC_7 , ct_d_30 , bidir , X , 521 , 1 , Z ),"& " 519 (BC_2 , * , control , 1 ) ,"& " 518 (LV_BC_7 , ct_d_28 , bidir , X , 519 , 1 , Z ),"& " 517 (BC_2 , * , control , 1 ) ,"& " 516 (LV_BC_7 , ct_d_23 , bidir , X , 517 , 1 , Z ),"& " 515 (BC_2 , * , control , 1 ) ,"& " 514 (LV_BC_7 , ct_d_25 , bidir , X , 515 , 1 , Z ),"& " 513 (BC_2 , * , control , 1 ) ,"& " 512 (LV_BC_7 , ct_d_20 , bidir , X , 513 , 1 , Z ),"& " 511 (BC_2 , * , control , 1 ) ,"& " 510 (LV_BC_7 , ct_d_31 , bidir , X , 511 , 1 , Z ),"& " 509 (BC_2 , * , control , 1 ) ,"& " 508 (LV_BC_7 , ct_d_19 , bidir , X , 509 , 1 , Z ),"& " 507 (BC_2 , * , control , 1 ) ,"& " 506 (LV_BC_7 , ct_d_22 , bidir , X , 507 , 1 , Z ),"& " 505 (BC_2 , * , control , 1 ) ,"& " 504 (LV_BC_7 , ct_d_29 , bidir , X , 505 , 1 , Z ),"& " 503 (BC_2 , * , control , 1 ) ,"& " 502 (LV_BC_7 , ct_d_18 , bidir , X , 503 , 1 , Z ),"& " 501 (BC_2 , * , control , 1 ) ,"& " 500 (LV_BC_7 , ct_d_27 , bidir , X , 501 , 1 , Z ),"& " 499 (BC_2 , * , control , 1 ) ,"& " 498 (LV_BC_7 , ct_d_24 , bidir , X , 499 , 1 , Z ),"& " 497 (BC_2 , * , control , 1 ) ,"& " 496 (LV_BC_7 , ct_d_15 , bidir , X , 497 , 1 , Z ),"& " 495 (BC_2 , * , control , 1 ) ,"& " 494 (LV_BC_7 , ct_d_17 , bidir , X , 495 , 1 , Z ),"& " 493 (BC_2 , * , control , 1 ) ,"& " 492 (LV_BC_7 , ct_d_12 , bidir , X , 493 , 1 , Z ),"& " 491 (BC_2 , * , control , 1 ) ,"& " 490 (LV_BC_7 , ct_d_10 , bidir , X , 491 , 1 , Z ),"& " 489 (BC_2 , * , control , 1 ) ,"& " 488 (LV_BC_7 , ct_d_14 , bidir , X , 489 , 1 , Z ),"& " 487 (BC_2 , * , control , 1 ) ,"& " 486 (LV_BC_7 , ct_d_6 , bidir , X , 487 , 1 , Z ),"& " 485 (BC_2 , * , control , 1 ) ,"& " 484 (LV_BC_7 , ct_d_16 , bidir , X , 485 , 1 , Z ),"& " 483 (BC_2 , * , control , 1 ) ,"& " 482 (LV_BC_7 , ct_d_11 , bidir , X , 483 , 1 , Z ),"& " 481 (BC_2 , * , control , 1 ) ,"& " 480 (LV_BC_7 , ct_d_13 , bidir , X , 481 , 1 , Z ),"& " 479 (BC_2 , * , control , 1 ) ,"& " 478 (LV_BC_7 , ct_d_9 , bidir , X , 479 , 1 , Z ),"& " 477 (BC_2 , * , control , 1 ) ,"& " 476 (LV_BC_7 , ct_d_2 , bidir , X , 477 , 1 , Z ),"& " 475 (BC_2 , * , control , 1 ) ,"& " 474 (LV_BC_7 , ct_d_5 , bidir , X , 475 , 1 , Z ),"& " 473 (BC_2 , * , control , 1 ) ,"& " 472 (LV_BC_7 , ct_d_8 , bidir , X , 473 , 1 , Z ),"& " 471 (BC_2 , * , control , 1 ) ,"& " 470 (LV_BC_7 , ct_d_7 , bidir , X , 471 , 1 , Z ),"& " 469 (BC_2 , * , control , 1 ) ,"& " 468 (LV_BC_7 , ct_d_1 , bidir , X , 469 , 1 , Z ),"& " 467 (BC_2 , * , control , 1 ) ,"& " 466 (LV_BC_7 , ct_d_4 , bidir , X , 467 , 1 , Z ),"& " 465 (BC_2 , * , control , 1 ) ,"& " 464 (LV_BC_7 , ct_d_3 , bidir , X , 465 , 1 , Z ),"& " 463 (BC_2 , * , control , 1 ) ,"& " 462 (LV_BC_7 , ct_d_0 , bidir , X , 463 , 1 , Z ),"& " 461 (BC_2 , dis_cap_0 , input , X ) ,"& " 460 (BC_2 , dis_cap_1 , input , X ) ,"& " 459 (BC_2 , * , control , 1 ) ,"& " 458 (BC_2 , memc_cas_0 , output3 , X , 459 , 1 , Z ),"& " 457 (BC_2 , memc_a_8 , output3 , X , 459 , 1 , Z ),"& " 456 (BC_2 , memc_a_5 , output3 , X , 459 , 1 , Z ),"& " 455 (BC_2 , memc_a_9 , output3 , X , 459 , 1 , Z ),"& " 454 (BC_2 , memc_a_10 , output3 , X , 459 , 1 , Z ),"& " 453 (BC_2 , * , control , 1 ) ,"& " 452 (BC_2 , memc_a_11 , output3 , X , 453 , 1 , Z ),"& " 451 (BC_2 , memc_a_4 , output3 , X , 453 , 1 , Z ),"& " 450 (BC_2 , memc_a_6 , output3 , X , 453 , 1 , Z ),"& " 449 (BC_2 , memc_we_0 , output3 , X , 453 , 1 , Z ),"& " 448 (BC_2 , memc_a_1 , output3 , X , 453 , 1 , Z ),"& " 447 (BC_2 , memc_a_2 , output3 , X , 453 , 1 , Z ),"& " 446 (BC_2 , * , control , 1 ) ,"& " 445 (BC_2 , memc_a_7 , output3 , X , 446 , 1 , Z ),"& " 444 (BC_2 , * , control , 1 ) ,"& " 443 (LV_BC_7 , memc_d_15 , bidir , X , 444 , 1 , Z ),"& " 442 (BC_2 , memc_a_13 , output3 , X , 446 , 1 , Z ),"& " 441 (BC_2 , memc_a_0 , output3 , X , 446 , 1 , Z ),"& " 440 (BC_2 , memc_a_12 , output3 , X , 446 , 1 , Z ),"& " 439 (BC_2 , memc_a_3 , output3 , X , 446 , 1 , Z ),"& " 438 (BC_2 , * , control , 1 ) ,"& " 437 (LV_BC_7 , memc_p_1 , bidir , X , 438 , 1 , Z ),"& " 436 (BC_2 , * , control , 1 ) ,"& " 435 (LV_BC_7 , memc_d_13 , bidir , X , 436 , 1 , Z ),"& " 434 (BC_2 , * , control , 1 ) ,"& " 433 (LV_BC_7 , memc_d_3 , bidir , X , 434 , 1 , Z ),"& " 432 (BC_2 , * , control , 1 ) ,"& " 431 (LV_BC_7 , memc_d_12 , bidir , X , 432 , 1 , Z ),"& " 430 (BC_2 , * , control , 1 ) ,"& " 429 (LV_BC_7 , memc_d_10 , bidir , X , 430 , 1 , Z ),"& " 428 (BC_2 , * , control , 1 ) ,"& " 427 (LV_BC_7 , memc_d_8 , bidir , X , 428 , 1 , Z ),"& " 426 (BC_2 , * , control , 1 ) ,"& " 425 (LV_BC_7 , memc_d_9 , bidir , X , 426 , 1 , Z ),"& " 424 (BC_2 , * , control , 1 ) ,"& " 423 (LV_BC_7 , memc_d_6 , bidir , X , 424 , 1 , Z ),"& " 422 (BC_2 , * , control , 1 ) ,"& " 421 (LV_BC_7 , memc_d_0 , bidir , X , 422 , 1 , Z ),"& " 420 (BC_2 , * , control , 1 ) ,"& " 419 (LV_BC_7 , memc_d_14 , bidir , X , 420 , 1 , Z ),"& " 418 (BC_2 , * , control , 1 ) ,"& " 417 (LV_BC_7 , memc_d_4 , bidir , X , 418 , 1 , Z ),"& " 416 (BC_2 , * , control , 1 ) ,"& " 415 (LV_BC_7 , memc_d_5 , bidir , X , 416 , 1 , Z ),"& " 414 (BC_2 , * , control , 1 ) ,"& " 413 (LV_BC_7 , memc_d_11 , bidir , X , 414 , 1 , Z ),"& " 412 (BC_2 , * , control , 1 ) ,"& " 411 (LV_BC_7 , memc_d_2 , bidir , X , 412 , 1 , Z ),"& " 410 (BC_2 , * , control , 1 ) ,"& " 409 (BC_2 , memc_bws_1 , output3 , X , 410 , 1 , Z ),"& " 408 (BC_2 , * , control , 1 ) ,"& " 407 (LV_BC_7 , memc_d_7 , bidir , X , 408 , 1 , Z ),"& " 406 (BC_2 , memc_rw , output3 , X , 410 , 1 , Z ),"& " 405 (BC_2 , memc_bws_3 , output3 , X , 410 , 1 , Z ),"& " 404 (BC_4 , mem_clk_net_i , clock , X ) ,"& " 403 (BC_2 , * , control , 1 ) ,"& " 402 (LV_BC_7 , memc_d_1 , bidir , X , 403 , 1 , Z ),"& " 401 (BC_2 , memc_cs_0 , output3 , X , 410 , 1 , Z ),"& " 400 (BC_2 , * , control , 1 ) ,"& " 399 (LV_BC_7 , memc_p_0 , bidir , X , 400 , 1 , Z ),"& " 398 (BC_2 , mem_clk_net_o , output3 , X , 410 , 1 , Z ),"& " 397 (BC_2 , * , control , 1 ) ,"& " 396 (BC_2 , memc_a_16 , output3 , X , 397 , 1 , Z ),"& " 395 (BC_2 , memc_bws_0 , output3 , X , 397 , 1 , Z ),"& " 394 (BC_2 , memc_bws_2 , output3 , X , 397 , 1 , Z ),"& " 393 (BC_2 , memc_a_15 , output3 , X , 397 , 1 , Z ),"& " 392 (BC_2 , * , control , 1 ) ,"& " 391 (LV_BC_7 , memc_p_2 , bidir , X , 392 , 1 , Z ),"& " 390 (BC_2 , memc_cs_1 , output3 , X , 397 , 1 , Z ),"& " 389 (BC_2 , * , control , 1 ) ,"& " 388 (LV_BC_7 , memc_d_19 , bidir , X , 389 , 1 , Z ),"& " 387 (BC_2 , * , control , 1 ) ,"& " 386 (LV_BC_7 , memc_d_22 , bidir , X , 387 , 1 , Z ),"& " 385 (BC_2 , * , control , 1 ) ,"& " 384 (LV_BC_7 , memc_d_17 , bidir , X , 385 , 1 , Z ),"& " 383 (BC_2 , * , control , 1 ) ,"& " 382 (BC_2 , memc_a_17 , output3 , X , 383 , 1 , Z ),"& " 381 (BC_2 , * , control , 1 ) ,"& " 380 (LV_BC_7 , memc_d_20 , bidir , X , 381 , 1 , Z ),"& " 379 (BC_2 , * , control , 1 ) ,"& " 378 (LV_BC_7 , memc_d_26 , bidir , X , 379 , 1 , Z ),"& " 377 (BC_2 , memc_a_14 , output3 , X , 383 , 1 , Z ),"& " 376 (BC_2 , * , control , 1 ) ,"& " 375 (LV_BC_7 , memc_d_23 , bidir , X , 376 , 1 , Z ),"& " 374 (BC_2 , * , control , 1 ) ,"& " 373 (LV_BC_7 , memc_d_16 , bidir , X , 374 , 1 , Z ),"& " 372 (BC_2 , * , control , 1 ) ,"& " 371 (LV_BC_7 , memc_d_28 , bidir , X , 372 , 1 , Z ),"& " 370 (BC_2 , * , control , 1 ) ,"& " 369 (LV_BC_7 , memc_d_30 , bidir , X , 370 , 1 , Z ),"& " 368 (BC_2 , * , control , 1 ) ,"& " 367 (LV_BC_7 , memc_d_27 , bidir , X , 368 , 1 , Z ),"& " 366 (BC_2 , * , control , 1 ) ,"& " 365 (LV_BC_7 , memc_d_25 , bidir , X , 366 , 1 , Z ),"& " 364 (BC_2 , * , control , 1 ) ,"& " 363 (LV_BC_7 , memc_d_18 , bidir , X , 364 , 1 , Z ),"& " 362 (BC_2 , * , control , 1 ) ,"& " 361 (LV_BC_7 , memc_d_21 , bidir , X , 362 , 1 , Z ),"& " 360 (BC_2 , * , control , 1 ) ,"& " 359 (LV_BC_7 , memc_d_24 , bidir , X , 360 , 1 , Z ),"& " 358 (BC_2 , memc_cs_2 , output3 , X , 383 , 1 , Z ),"& " 357 (BC_2 , * , control , 1 ) ,"& " 356 (LV_BC_7 , memc_d_29 , bidir , X , 357 , 1 , Z ),"& " 355 (BC_2 , memc_ras , output3 , X , 383 , 1 , Z ),"& " 354 (BC_2 , memb_a_7 , output3 , X , 383 , 1 , Z ),"& " 353 (BC_2 , memc_we_1 , output3 , X , 383 , 1 , Z ),"& " 352 (BC_2 , * , control , 1 ) ,"& " 351 (LV_BC_7 , memc_d_31 , bidir , X , 352 , 1 , Z ),"& " 350 (BC_2 , memb_cs_3 , output3 , X , 383 , 1 , Z ),"& " 349 (BC_2 , * , control , 1 ) ,"& " 348 (LV_BC_7 , memc_p_3 , bidir , X , 349 , 1 , Z ),"& " 347 (BC_2 , * , control , 1 ) ,"& " 346 (BC_2 , memc_cs_3 , output3 , X , 347 , 1 , Z ),"& " 345 (BC_2 , memc_cas_1 , output3 , X , 347 , 1 , Z ),"& " 344 (BC_2 , memb_cs_1 , output3 , X , 347 , 1 , Z ),"& " 343 (BC_2 , memb_cs_0 , output3 , X , 347 , 1 , Z ),"& " 342 (BC_2 , memb_a_6 , output3 , X , 347 , 1 , Z ),"& " 341 (BC_2 , mem_oe , output3 , X , 347 , 1 , Z ),"& " 340 (BC_2 , memb_bws_0 , output3 , X , 347 , 1 , Z ),"& " 339 (BC_2 , * , control , 1 ) ,"& " 338 (BC_2 , memb_bws_1 , output3 , X , 339 , 1 , Z ),"& " 337 (BC_2 , memb_a_18 , output3 , X , 339 , 1 , Z ),"& " 336 (BC_2 , memb_a_8 , output3 , X , 339 , 1 , Z ),"& " 335 (BC_2 , memb_cs_2 , output3 , X , 339 , 1 , Z ),"& " 334 (BC_2 , memb_a_9 , output3 , X , 339 , 1 , Z ),"& " 333 (BC_2 , * , control , 1 ) ,"& " 332 (LV_BC_7 , memb_d_7 , bidir , X , 333 , 1 , Z ),"& " 331 (BC_2 , * , control , 1 ) ,"& " 330 (LV_BC_7 , memb_d_9 , bidir , X , 331 , 1 , Z ),"& " 329 (BC_2 , * , control , 1 ) ,"& " 328 (LV_BC_7 , memb_p_0 , bidir , X , 329 , 1 , Z ),"& " 327 (BC_2 , memb_a_17 , output3 , X , 339 , 1 , Z ),"& " 326 (BC_2 , * , control , 1 ) ,"& " 325 (LV_BC_7 , memb_d_8 , bidir , X , 326 , 1 , Z ),"& " 324 (BC_2 , memb_rw , output3 , X , 339 , 1 , Z ),"& " 323 (BC_2 , * , control , 1 ) ,"& " 322 (LV_BC_7 , memb_d_6 , bidir , X , 323 , 1 , Z ),"& " 321 (BC_2 , * , control , 1 ) ,"& " 320 (LV_BC_7 , memb_d_11 , bidir , X , 321 , 1 , Z ),"& " 319 (BC_2 , * , control , 1 ) ,"& " 318 (LV_BC_7 , memb_d_4 , bidir , X , 319 , 1 , Z ),"& " 317 (BC_2 , * , control , 1 ) ,"& " 316 (LV_BC_7 , memb_d_5 , bidir , X , 317 , 1 , Z ),"& " 315 (BC_2 , * , control , 1 ) ,"& " 314 (LV_BC_7 , memb_d_10 , bidir , X , 315 , 1 , Z ),"& " 313 (BC_4 , nreset , observe_only , X ),"& " 312 (BC_2 , * , control , 1 ) ,"& " 311 (LV_BC_7 , memb_d_12 , bidir , X , 312 , 1 , Z )," & " 310 (BC_2 , * , control , 1 ) ,"& " 309 (LV_BC_7 , memb_d_14 , bidir , X , 310 , 1 , Z ),"& " 308 (BC_2 , * , control , 1 ) ,"& " 307 (LV_BC_7 , memb_p_1 , bidir , X , 308 , 1 , Z ),"& " 306 (BC_2 , * , control , 1 ) ,"& " 305 (LV_BC_7 , memb_d_3 , bidir , X , 306 , 1 , Z ),"& " 304 (BC_2 , * , control , 1 ) ,"& " 303 (LV_BC_7 , memb_d_2 , bidir , X , 304 , 1 , Z ),"& " 302 (BC_2 , * , control , 1 ) ,"& " 301 (LV_BC_7 , memb_d_13 , bidir , X , 302 , 1 , Z ),"& " 300 (BC_2 , * , control , 1 ) ,"& " 299 (LV_BC_7 , memb_d_0 , bidir , X , 300 , 1 , Z ),"& " 298 (BC_2 , * , control , 1 ) ,"& " 297 (BC_2 , memb_a_0 , output3 , X , 298 , 1 , Z ),"& " 296 (BC_2 , memb_a_2 , output3 , X , 298 , 1 , Z ),"& " 295 (BC_2 , memb_a_5 , output3 , X , 298 , 1 , Z ),"& " 294 (BC_2 , memb_a_3 , output3 , X , 298 , 1 , Z ),"& " 293 (BC_2 , * , control , 1 ) ,"& " 292 (LV_BC_7 , memb_d_15 , bidir , X , 293 , 1 , Z ),"& " 291 (BC_2 , * , control , 1 ) ,"& " 290 (LV_BC_7 , memb_d_1 , bidir , X , 291 , 1 , Z ),"& " 289 (BC_2 , memb_a_11 , output3 , X , 298 , 1 , Z ),"& " 288 (BC_2 , memb_a_13 , output3 , X , 298 , 1 , Z ),"& " 287 (BC_2 , memb_a_10 , output3 , X , 298 , 1 , Z ),"& " 286 (BC_2 , * , control , 1 ) ,"& " 285 (BC_2 , memb_a_4 , output3 , X , 286 , 1 , Z ),"& " 284 (BC_2 , memb_a_1 , output3 , X , 286 , 1 , Z ),"& " 283 (BC_2 , memb_a_15 , output3 , X , 286 , 1 , Z ),"& " 282 (BC_2 , mem_clk_sar_o , output3 , X , 286 , 1 , Z ),"& " 281 (BC_4 , mem_clk_sar_i , clock , X ) ,"& " 280 (BC_2 , mema_a_9 , output3 , X , 286 , 1 , Z ),"& " 279 (BC_2 , memb_a_12 , output3 , X , 286 , 1 , Z ),"& " 278 (BC_2 , * , control , 1 ) ,"& " 277 (BC_2 , memb_a_14 , output3 , X , 278 , 1 , Z ),"& " 276 (BC_2 , mema_cs_2 , output3 , X , 278 , 1 , Z ),"& " 275 (BC_2 , mema_rw , output3 , X , 278 , 1 , Z ),"& " 274 (BC_2 , memb_a_16 , output3 , X , 278 , 1 , Z ),"& " 273 (BC_2 , mema_bws_0 , output3 , X , 278 , 1 , Z ),"& " 272 (BC_2 , mema_a_18 , output3 , X , 278 , 1 , Z ),"& " 271 (BC_2 , mema_a_17 , output3 , X , 278 , 1 , Z ),"& " 270 (BC_2 , * , control , 1 ) ,"& " 269 (LV_BC_7 , mema_d_6 , bidir , X , 270 , 1 , Z ),"& " 268 (BC_2 , * , control , 1 ) ,"& " 267 (BC_2 , mema_cs_0 , output3 , X , 268 , 1 , Z ),"& " 266 (BC_2 , * , control , 1 ) ,"& " 265 (LV_BC_7 , mema_d_11 , bidir , X , 266 , 1 , Z ),"& " 264 (BC_2 , mema_a_8 , output3 , X , 268 , 1 , Z ),"& " 263 (BC_2 , * , control , 1 ) ,"& " 262 (LV_BC_7 , mema_p_0 , bidir , X , 263 , 1 , Z ),"& " 261 (BC_2 , mema_cs_1 , output3 , X , 268 , 1 , Z ),"& " 260 (BC_2 , mema_a_7 , output3 , X , 268 , 1 , Z ),"& " 259 (BC_2 , * , control , 1 ) ,"& " 258 (LV_BC_7 , rxa_led , bidir , X , 259 , 1 , Z ),"& " 257 (BC_2 , * , control , 1 ) ,"& " 256 (LV_BC_7 , mema_d_9 , bidir , X , 257 , 1 , Z ),"& " 255 (BC_2 , mema_bws_1 , output3 , X , 268 , 1 , Z ),"& " 254 (BC_2 , mema_a_6 , output3 , X , 268 , 1 , Z ),"& " 253 (BC_2 , * , control , 1 ) ,"& " 252 (LV_BC_7 , mema_d_5 , bidir , X , 253 , 1 , Z ),"& " 251 (BC_2 , * , control , 1 ) ,"& " 250 (LV_BC_7 , mema_d_8 , bidir , X , 251 , 1 , Z ),"& " 249 (BC_2 , * , control , 1 ) ,"& " 248 (LV_BC_7 , mema_d_4 , bidir , X , 249 , 1 , Z ),"& " 247 (BC_2 , * , control , 1 ) ,"& " 246 (LV_BC_7 , mema_d_7 , bidir , X , 247 , 1 , Z ),"& " 245 (BC_2 , * , control , 1 ) ,"& " 244 (LV_BC_7 , mema_d_10 , bidir , X , 245 , 1 , Z ),"& " 243 (BC_2 , * , control , 1 ) ,"& " 242 (LV_BC_7 , mema_d_14 , bidir , X , 243 , 1 , Z ),"& " 241 (BC_2 , * , control , 1 ) ,"& " 240 (BC_2 , mema_cs_3 , output3 , X , 241 , 1 , Z ),"& " 239 (BC_2 , * , control , 1 ) ,"& " 238 (LV_BC_7 , mema_p_1 , bidir , X , 239 , 1 , Z ),"& " 237 (BC_2 , * , control , 1 ) ,"& " 236 (LV_BC_7 , mema_d_2 , bidir , X , 237 , 1 , Z ),"& " 235 (BC_2 , mema_a_4 , output3 , X , 241 , 1 , Z ),"& " 234 (BC_2 , * , control , 1 ) ,"& " 233 (LV_BC_7 , mema_d_1 , bidir , X , 234 , 1 , Z ),"& " 232 (BC_2 , mema_a_2 , output3 , X , 241 , 1 , Z ),"& " 231 (BC_2 , mema_a_5 , output3 , X , 241 , 1 , Z ),"& " 230 (BC_2 , * , control , 1 ) ,"& " 229 (LV_BC_7 , mema_d_15 , bidir , X , 230 , 1 , Z ),"& " 228 (BC_2 , * , control , 1 ) ,"& " 227 (LV_BC_7 , mema_d_3 , bidir , X , 228 , 1 , Z ),"& " 226 (BC_2 , mema_a_0 , output3 , X , 241 , 1 , Z ),"& " 225 (BC_2 , mema_a_11 , output3 , X , 241 , 1 , Z ),"& " 224 (BC_2 , mema_a_1 , output3 , X , 241 , 1 , Z ),"& " 223 (BC_2 , * , control , 1 ) ,"& " 222 (BC_2 , mema_a_3 , output3 , X , 223 , 1 , Z ),"& " 221 (BC_2 , * , control , 1 ) ,"& " 220 (LV_BC_7 , mema_d_12 , bidir , X , 221 , 1 , Z ),"& " 219 (BC_2 , * , control , 1 ) ,"& " 218 (LV_BC_7 , mema_d_13 , bidir , X , 219 , 1 , Z ),"& " 217 (BC_2 , mema_a_13 , output3 , X , 223 , 1 , Z ),"& " 216 (BC_2 , * , control , 1 ) ,"& " 215 (LV_BC_7 , mema_d_0 , bidir , X , 216 , 1 , Z ),"& " 214 (BC_2 , mema_a_10 , output3 , X , 223 , 1 , Z ),"& " 213 (BC_2 , mema_a_15 , output3 , X , 223 , 1 , Z ),"& " 212 (BC_2 , rxa_addr2 , input , X ) ,"& " 211 (BC_2 , rxa_addr4 , input , X ) ,"& " 210 (BC_2 , mema_a_12 , output3 , X , 223 , 1 , Z ),"& " 209 (BC_2 , txa_addr1 , input , X ) ,"& " 208 (BC_2 , mema_a_14 , output3 , X , 223 , 1 , Z ),"& " 207 (BC_2 , * , control , 1 ) ,"& " 206 (LV_BC_7 , txa_addr4 , bidir , X , 207 , 1 , Z ),"& " 205 (BC_2 , * , control , 1 ) ,"& " 204 (BC_2 , mema_a_16 , output3 , X , 205 , 1 , Z ),"& " 203 (BC_2 , txa_addr0 , input , X ) ,"& " 202 (BC_2 , rxa_addr3 , input , X ) ,"& " 201 (BC_2 , rxa_addr0 , input , X ) ,"& " 200 (BC_2 , rxa_addr1 , input , X ) ,"& " 199 (BC_2 , txa_addr2 , input , X ) ,"& " 198 (BC_2 , * , control , 1 ) ,"& " 197 (LV_BC_7 , txa_addr3 , bidir , X , 198 , 1 , Z ),"& " 196 (BC_2 , cpu_mode_0 , input , X ) ,"& " 195 (BC_2 , cpu_mode_1 , input , X ) ,"& " 194 (BC_2 , cpu_mode_2 , input , X ) ,"& " 193 (BC_2 , cpu_mode_3 , input , X ) ,"& " 192 (BC_2 , etha_rx_d_2 , input , X ) ,"& " 191 (BC_2 , * , control , 1 ) ,"& " 190 (BC_2 , etha_tx_en , output3 , X , 191 , 1 , Z ),"& " 189 (BC_2 , etha_rx_er , input , X ) ,"& " 188 (BC_2 , etha_rx_d_3 , input , X ) ,"& " 187 (BC_2 , etha_rx_d_1 , input , X ) ,"& " 186 (BC_2 , rxa_alarm , input , X ) ,"& " 185 (BC_2 , * , control , 1 ) ,"& " 184 (BC_2 , ethab_tx_d_1 , output3 , X , 185 , 1 , Z ),"& " 183 (BC_2 , * , control , 1 ) ,"& " 182 (BC_2 , ethab_tx_d_0 , output3 , X , 183 , 1 , Z ),"& " 181 (BC_2 , ethab_tx_d_3 , output3 , X , 191 , 1 , Z ),"& " 180 (BC_2 , etha_rx_d_0 , input , X ) ,"& " 179 (BC_2 , etha_rx_clk , input , X ) ,"& " 178 (BC_2 , * , control , 1 ) ,"& " 177 (BC_2 , ethab_tx_d_2 , output3 , X , 178 , 1 , Z ),"& " 176 (BC_2 , * , control , 1 ) ,"& " 175 (BC_2 , txa_enb , output3 , X , 176 , 1 , Z ),"& " 174 (BC_2 , etha_col , input , X ) ,"& " 173 (BC_4 , upclk , clock , X ) ,"& " 172 (BC_2 , etha_tx_clk , input , X ) ,"& " 171 (BC_2 , etha_crs , input , X ) ,"& " 170 (BC_2 , etha_rx_dv , input , X ) ,"& " 169 (BC_2 , * , control , 1 ) ,"& " 168 (BC_2 , txb_soc , output3 , X , 169 , 1 , Z ),"& " 167 (BC_2 , * , control , 1 ) ,"& " 166 (BC_2 , txb_d_6 , output3 , X , 167 , 1 , Z ),"& " 165 (BC_2 , * , control , 1 ) ,"& " 164 (BC_2 , txb_enb , output3 , X , 165 , 1 , Z ),"& " 163 (BC_2 , * , control , 1 ) ,"& " 162 (BC_2 , txb_d_3 , output3 , X , 163 , 1 , Z ),"& " 161 (BC_2 , * , control , 1 ) ,"& " 160 (LV_BC_7 , txb_clk , bidir , X , 161 , 1 , Z ),"& " 159 (BC_2 , * , control , 1 ) ,"& " 158 (BC_2 , txb_d_4 , output3 , X , 159 , 1 , Z ),"& " 157 (BC_2 , * , control , 1 ) ,"& " 156 (BC_2 , txb_d_7 , output3 , X , 157 , 1 , Z ),"& " 155 (BC_2 , * , control , 1 ) ,"& " 154 (BC_2 , txb_d_5 , output3 , X , 155 , 1 , Z ),"& " 153 (BC_2 , * , control , 1 ) ,"& " 152 (BC_2 , txb_d_2 , output3 , X , 153 , 1 , Z ),"& " 151 (BC_2 , txb_clav , input , X ) ,"& " 150 (BC_2 , * , control , 1 ) ,"& " 149 (BC_2 , txb_d_0 , output3 , X , 150 , 1 , Z ),"& " 148 (BC_2 , * , control , 1 ) ,"& " 147 (BC_2 , txb_prty , output3 , X , 148 , 1 , Z ),"& " 146 (BC_2 , * , control , 1 ) ,"& " 145 (BC_2 , rxb_enb , output3 , X , 146 , 1 , Z ),"& " 144 (BC_2 , * , control , 1 ) ,"& " 143 (LV_BC_7 , rxb_clk , bidir , X , 144 , 1 , Z ),"& " 142 (BC_2 , rxb_prty , input , X ) ,"& " 141 (BC_2 , rxb_d_5 , input , X ) ,"& " 140 (BC_2 , rxb_soc , input , X ) ,"& " 139 (BC_2 , * , control , 1 ) ,"& " 138 (BC_2 , txb_d_1 , output3 , X , 139 , 1 , Z ),"& " 137 (BC_2 , rxb_d_0 , input , X ) ,"& " 136 (BC_2 , rxb_clav , input , X ) ,"& " 135 (BC_2 , rxb_d_3 , input , X ) ,"& " 134 (BC_2 , rxb_d_2 , input , X ) ,"& " 133 (BC_2 , rxb_d_7 , input , X ) ,"& " 132 (BC_2 , rxb_d_6 , input , X ) ,"& " 131 (BC_2 , * , control , 1 ) ,"& " 130 (BC_2 , txa_d_12 , output3 , X , 131 , 1 , Z ),"& " 129 (BC_2 , * , control , 1 ) ,"& " 128 (BC_2 , txa_d_9 , output3 , X , 129 , 1 , Z ),"& " 127 (BC_2 , * , control , 1 ) ,"& " 126 (BC_2 , txa_d_7 , output3 , X , 127 , 1 , Z ),"& " 125 (BC_2 , rxb_d_4 , input , X ) ,"& " 124 (BC_2 , * , control , 1 ) ,"& " 123 (BC_2 , txa_prty , output3 , X , 124 , 1 , Z ),"& " 122 (BC_2 , rxb_d_1 , input , X ) ,"& " 121 (BC_2 , * , control , 1 ) ,"& " 120 (BC_2 , txa_d_11 , output3 , X , 121 , 1 , Z ),"& " 119 (BC_2 , * , control , 1 ) ,"& " 118 (LV_BC_7 , txa_clk , bidir , X , 119 , 1 , Z ),"& " 117 (BC_2 , * , control , 1 ) ,"& " 116 (BC_2 , txa_d_13 , output3 , X , 117 , 1 , Z ),"& " 115 (BC_2 , * , control , 1 ) ,"& " 114 (BC_2 , txa_soc , output3 , X , 115 , 1 , Z ),"& " 113 (BC_2 , * , control , 1 ) ,"& " 112 (BC_2 , txa_d_8 , output3 , X , 113 , 1 , Z ),"& " 111 (BC_2 , * , control , 1 ) ,"& " 110 (BC_2 , txa_d_10 , output3 , X , 111 , 1 , Z ),"& " 109 (BC_2 , * , control , 1 ) ,"& " 108 (BC_2 , txa_d_5 , output3 , X , 109 , 1 , Z ),"& " 107 (BC_2 , * , control , 1 ) ,"& " 106 (BC_2 , txa_d_14 , output3 , X , 107 , 1 , Z ),"& " 105 (BC_2 , * , control , 1 ) ,"& " 104 (BC_2 , txa_d_15 , output3 , X , 105 , 1 , Z ),"& " 103 (BC_2 , * , control , 1 ) ,"& " 102 (BC_2 , txa_d_6 , output3 , X , 103 , 1 , Z ),"& " 101 (BC_2 , * , control , 1 ) ,"& " 100 (BC_2 , txa_d_4 , output3 , X , 101 , 1 , Z ),"& " 99 (BC_2 , rxa_d_13 , input , X ) ,"& " 98 (BC_2 , rxa_clav , input , X ) ,"& " 97 (BC_2 , * , control , 1 ) ,"& " 96 (BC_2 , txa_d_3 , output3 , X , 97 , 1 , Z ),"& " 95 (BC_2 , * , control , 1 ) ,"& " 94 (BC_2 , txa_d_1 , output3 , X , 95 , 1 , Z ),"& " 93 (BC_2 , rxa_d_15 , input , X ) ,"& " 92 (BC_2 , * , control , 1 ) ,"& " 91 (LV_BC_7 , rxa_clk , bidir , X , 92 , 1 , Z ),"& " 90 (BC_2 , * , control , 1 ) ,"& " 89 (BC_2 , rxa_enb , output3 , X , 90 , 1 , Z ),"& " 88 (BC_2 , * , control , 1 ) ,"& " 87 (BC_2 , txa_d_2 , output3 , X , 88 , 1 , Z ),"& " 86 (BC_2 , txa_clav , input , X ) ,"& " 85 (BC_2 , rxa_d_11 , input , X ) ,"& " 84 (BC_2 , rxa_d_14 , input , X ) ,"& " 83 (BC_2 , * , control , 1 ) ,"& " 82 (BC_2 , txa_d_0 , output3 , X , 83 , 1 , Z ),"& " 81 (BC_2 , rxa_soc , input , X ) ,"& " 80 (BC_2 , rxa_d_9 , input , X ) ,"& " 79 (BC_2 , rxa_prty , input , X ) ,"& " 78 (BC_2 , rxa_d_4 , input , X ) ,"& " 77 (BC_2 , rxa_d_12 , input , X ) ,"& " 76 (BC_2 , rxa_d_7 , input , X ) ,"& " 75 (BC_2 , rxa_d_1 , input , X ) ,"& " 74 (BC_2 , rxa_d_5 , input , X ) ,"& " 73 (BC_2 , rxa_d_10 , input , X ) ,"& " 72 (BC_2 , cpu_a_12 , input , X ) ,"& " 71 (BC_2 , rxa_d_8 , input , X ) ,"& " 70 (BC_2 , rxa_d_3 , input , X ) ,"& " 69 (BC_2 , rxa_d_6 , input , X ) ,"& " 68 (BC_2 , cpu_a_14 , input , X ) ,"& " 67 (BC_2 , rxa_d_0 , input , X ) ,"& " 66 (BC_2 , rxa_d_2 , input , X ) ,"& " 65 (BC_2 , cpu_a_11 , input , X ) ,"& " 64 (BC_2 , cpu_a_10 , input , X ) ,"& " 63 (BC_2 , cpu_a_5 , input , X ) ,"& " 62 (BC_2 , cpu_a_8 , input , X ) ,"& " 61 (BC_2 , cpu_a_13 , input , X ) ,"& " 60 (BC_2 , cpu_a_7 , input , X ) ,"& " 59 (BC_2 , cpu_a_2 , input , X ) ,"& " 58 (BC_2 , cpu_a_4 , input , X ) ,"& " 57 (BC_2 , cpu_a_6 , input , X ) ,"& " 56 (BC_2 , cpu_a_3 , input , X ) ,"& " 55 (BC_2 , cpu_a_9 , input , X ) ,"& " 54 (BC_2 , cpu_a_1 , input , X ) ,"& " 53 (BC_2 , cpu_ale , input , X ) ,"& " 52 (BC_2 , * , control , 1 ) ,"& " 51 (LV_BC_7 , cpu_a_das , bidir , X , 52 , 1 , Z ),"& " 50 (BC_2 , cpu_wr_rw , input , X ) ,"& " 49 (BC_2 , cpu_a_0 , input , X ) ,"& " 48 (BC_2 , * , control , 1 ) ,"& " 47 (LV_BC_7 , cpu_cs , bidir , X , 48 , 1 , Z ),"& " 46 (BC_2 , cpu_rd_ds , input , X ) ,"& " 45 (BC_2 , * , control , 1 ) ,"& " 44 (LV_BC_7 , cpu_rdy_ndtack , bidir , X , 45 , 1 , Z ),"& " 43 (BC_2 , * , control , 1 ) ,"& " 42 (LV_BC_7 , cpu_d_12 , bidir , X , 43 , 1 , Z ),"& " 41 (LV_BC_7 , cpu_d_14 , bidir , X , 43 , 1 , Z ),"& " 40 (LV_BC_7 , cpu_d_15 , bidir , X , 43 , 1 , Z ),"& " 39 (LV_BC_7 , cpu_d_13 , bidir , X , 43 , 1 , Z ),"& " 38 (BC_2 , * , control , 1 ) ,"& " 37 (LV_BC_7 , cpu_d_11 , bidir , X , 38 , 1 , Z ),"& " 36 (BC_2 , * , control , 1 ) ,"& " 35 (LV_BC_7 , cpu_d_7 , bidir , X , 36 , 1 , Z ),"& " 34 (LV_BC_7 , cpu_d_9 , bidir , X , 38 , 1 , Z ),"& " 33 (LV_BC_7 , cpu_d_6 , bidir , X , 36 , 1 , Z ),"& " 32 (LV_BC_7 , cpu_d_10 , bidir , X , 38 , 1 , Z ),"& " 31 (LV_BC_7 , cpu_d_4 , bidir , X , 36 , 1 , Z ),"& " 30 (LV_BC_7 , cpu_d_8 , bidir , X , 38 , 1 , Z ),"& " 29 (LV_BC_7 , cpu_d_5 , bidir , X , 36 , 1 , Z ),"& " 28 (BC_2 , * , control , 1 ) ,"& " 27 (BC_2 , cpu_int_1 , output3 , X , 28 , 1 , Z ),"& " 26 (LV_BC_7 , cpu_d_3 , bidir , X , 36 , 1 , Z ),"& " 25 (LV_BC_7 , cpu_d_1 , bidir , X , 36 , 1 , Z ),"& " 24 (LV_BC_7 , cpu_d_0 , bidir , X , 36 , 1 , Z ),"& " 23 (BC_2 , * , control , 1 ) ,"& " 22 (LV_BC_7 , gpio_3 , bidir , X , 23 , 1 , Z ),"& " 21 (BC_2 , * , control , 1 ) ,"& " 20 (BC_2 , cpu_int_0 , output3 , X , 21 , 1 , Z ),"& " 19 (BC_2 , * , control , 1 ) ,"& " 18 (LV_BC_7 , gpio_7 , bidir , X , 19 , 1 , Z ),"& " 17 (BC_2 , * , control , 1 ) ,"& " 16 (LV_BC_7 , gpio_1 , bidir , X , 17 , 1 , Z ),"& " 15 (BC_2 , * , control , 1 ) ,"& " 14 (LV_BC_7 , gpio_4 , bidir , X , 15 , 1 , Z ),"& " 13 (BC_4 , pll_clk , clock , X ) ,"& " 12 (LV_BC_7 , cpu_d_2 , bidir , X , 36 , 1 , Z ),"& " 11 (BC_2 , * , control , 1 ) ,"& " 10 (BC_2 , c16p , output3 , X , 11 , 1 , Z ),"& " 9 (BC_2 , * , control , 1 ) ,"& " 8 (LV_BC_7 , gpio_6 , bidir , X , 9 , 1 , Z ),"& " 7 (BC_2 , * , control , 1 ) ,"& " 6 (LV_BC_7 , gpio_2 , bidir , X , 7 , 1 , Z ),"& " 5 (BC_2 , * , control , 1 ) ,"& " 4 (LV_BC_7 , ct_c8_b , bidir , X , 5 , 1 , Z ),"& " 3 (BC_2 , * , control , 1 ) ,"& " 2 (LV_BC_7 , gpio_5 , bidir , X , 3 , 1 , Z ),"& " 1 (BC_2 , * , control , 1 ) ,"& " 0 (LV_BC_7 , gpio_0 , bidir , X , 1 , 1 , Z ) "; end MT92220;