-- ======================================================================= -- Boundary Scan Description Language (BSDL) File -- -- Product: PEX8112 (PLX Technology, Inc.) -- Package: 0.65mm FBGA-161 -- -- ======================================================================= -- **************************************************************** -- This BSDL has been validated for syntax and semantics compliance -- to IEEE 1149.1. Please see Data Book for pin descriptions. -- -- NOTE: Silicon version AA -- -- ======================================================================= -- Revision Control: -- -- Version Date Reason for Change -- ******* ******** *********************************** -- 1.0 05/14/07 Initial version for Silicon rev. AA -- ====================================================================== entity PEX8112AA_FBGA_r1 is -- This section identifies the default device package selected. generic(PHYSICAL_PIN_MAP : string := "FBGA_161"); -- This section declares all the ports in the design. port( REQ3n:inout bit; AD6:inout bit; WAKEOUTn:out bit; AD22:inout bit; AD30:inout bit; VSS_P1:linkage bit; VSS_P0:linkage bit; VSS_R:linkage bit; AD26:inout bit; VSS_RE:linkage bit; TDO:out bit; AD28:inout bit; VSS_C:linkage bit; AD31:inout bit; TMS:in bit; AD2:inout bit; AVDD:linkage bit; IRDYn:inout bit; BUNRI:linkage bit; AD24:inout bit; INTDn:inout bit; PERSTn:inout bit; TMC2:linkage bit; STOPn:inout bit; PCIRSTn:inout bit; GPIO3:inout bit; AD7:inout bit; EERDDATA:in bit; WAKEINn:in bit; IDSEL:inout bit; CBE3n:inout bit; INTAn:inout bit; PERRn:inout bit; AD20:inout bit; AD27:inout bit; VDD_T:linkage bit; TMC:linkage bit; AD21:inout bit; REFCLKT:linkage bit; AD15:inout bit; GPIO1:inout bit; AD13:inout bit; GNT1n:inout bit; EEWRDATA:buffer bit; REFCLKC:linkage bit; TCK:in bit; AD14:inout bit; GNT0n:inout bit; AD16:inout bit; FRAMEn:inout bit; AVSS:linkage bit; INTCn:inout bit; PMEOUTn:out bit; CBE2n:inout bit; AD12:inout bit; VDD_R:linkage bit; SMC:linkage bit; TDI:in bit; AD18:inout bit; INTBn:inout bit; M66EN:inout bit; PMEINn:inout bit; EECLK:buffer bit; SERRn:inout bit; FORWARD:in bit; AD10:inout bit; AD0:inout bit; TXOUTT:linkage bit; PCLKO:inout bit; GPIO0:inout bit; TXOUTC:linkage bit; PWR_OK:buffer bit; TMC1:linkage bit; CBE0n:inout bit; AD29:inout bit; BTON:linkage bit; VSS_T:linkage bit; PCLKO62SELn:inout bit; TRST:in bit; TRDYn:inout bit; VDD_P:linkage bit; AD11:inout bit; REQ2n:inout bit; EXTARB:in bit; PAR:inout bit; AD5:inout bit; GNT3n:inout bit; REQ0n:inout bit; AD1:inout bit; GNT2n:inout bit; AD17:inout bit; GPIO2:inout bit; LOCKn:inout bit; REQ1n:inout bit; AD3:inout bit; RXINC:linkage bit; EECSn:buffer bit; AD8:inout bit; CBE1n:inout bit; AD23:inout bit; AD19:inout bit; PCLKI:inout bit; BAR0ENBn:inout bit; AD9:inout bit; TEST:linkage bit; RXINT:linkage bit; AD25:inout bit; DEVSELn:inout bit; AD4:inout bit; NA:linkage bit_vector(0 to 16); GND:linkage bit_vector(0 to 13); VDD15:linkage bit_vector(0 to 7); VDD33:linkage bit_vector(0 to 3); VDD5:linkage bit_vector(0 to 2); VDDQ:linkage bit_vector(0 to 5) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of PEX8112AA_FBGA_r1 : entity is "STD_1149_1_1993"; attribute PIN_MAP of PEX8112AA_FBGA_r1 : entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. constant FBGA_161 : PIN_MAP_STRING := "REQ3n:H11," & "AD6:F1," & "WAKEOUTn:A11," & "AD22:N8," & "AD30:J11," & "VSS_P1:D8," & "VSS_P0:D7," & "VSS_R:A9," & "AD26:P11," & "VSS_RE:B8," & "TDO:M3," & "AD28:L12," & "VSS_C:D9," & "AD31:L13," & "TMS:N12," & "AD2:D3," & "AVDD:C8," & "IRDYn:P5," & "BUNRI:C9," & "AD24:P9," & "INTDn:E13," & "PERSTn:C12," & "TMC2:M1," & "STOPn:N4," & "PCIRSTn:G14," & "GPIO3:B12," & "AD7:F2," & "EERDDATA:B3," & "WAKEINn:D14," & "IDSEL:N10," & "CBE3n:M9," & "INTAn:F14," & "PERRn:L2," & "AD20:M8," & "AD27:M10," & "VDD_T:D6," & "TMC:D10," & "AD21:P8," & "REFCLKT:B7," & "AD15:K2," & "GPIO1:A12," & "AD13:J1," & "GNT1n:J13," & "EEWRDATA:A3," & "REFCLKC:A7," & "TCK:M2," & "AD14:J3," & "GNT0n:J14," & "AD16:P7," & "FRAMEn:L5," & "AVSS:C6," & "INTCn:E14," & "PMEOUTn:M14," & "CBE2n:P6," & "AD12:H2," & "VDD_R:C7," & "SMC:K3," & "TDI:P3," & "AD18:L6," & "INTBn:F13," & "M66EN:D13," & "PMEINn:L14," & "EECLK:C2," & "SERRn:L1," & "FORWARD:M13," & "AD10:H1," & "AD0:D2," & "TXOUTT:A6," & "PCLKO:H14," & "GPIO0:C10," & "TXOUTC:B5," & "PWR_OK:B11," & "TMC1:D4," & "CBE0n:G1," & "AD29:K12," & "BTON:M11," & "VSS_T:A5," & "PCLKO62SELn:C3," & "NA:(A1,A2,A13,A14,B1,B2,B13,B14,E5,N1," & "N2,N13,N14,P1,P2,P13,P14)," & "TRST:N11," & "TRDYn:M5," & "VDD_P:B6," & "AD11:H3," & "REQ2n:H12," & "EXTARB:M12," & "PAR:J4," & "AD5:E2," & "GNT3n:F12," & "REQ0n:K14," & "AD1:D1," & "GNT2n:G11," & "AD17:N6," & "GPIO2:D11," & "LOCKn:P4," & "REQ1n:K13," & "AD3:E1," & "RXINC:B9," & "EECSn:C5," & "AD8:F3," & "CBE1n:K1," & "AD23:L9," & "AD19:M7," & "PCLKI:E12," & "BAR0ENBn:A10," & "AD9:G4," & "TEST:C4," & "RXINT:A8," & "AD25:P10," & "DEVSELn:M4," & "AD4:E3," & "GND:(A4,C13,D5,D12,E4,E11,F11,J2,K4,K11," & "L4,M6,N9,P12)," & "VDD15:(B10,C1,C14,G2,G13,L3,L11,N7)," & "VDD33:(B4,C11,L10,N3)," & "VDD5:(G3,H13,L7)," & "VDDQ:(F4,G12,H4,J12,L8,N5)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (5.0e6, BOTH); attribute TAP_SCAN_RESET of TRST : signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of PEX8112AA_FBGA_r1 : entity is 5; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of PEX8112AA_FBGA_r1: entity is "EXTEST(00000)," & "SAMPLE(00011)," & -- "CLAMP(01011)," & "NECHIGHZ(00010)," & "IDCODE(00001)," & "NECINTEST(00100)," & "MUXSCAN(01010)," & "SCAN(00101)," & "CSP(01000)," & "COREBYPASS(01001)," & "DELAY(00110)," & "D_SELECT(00111)," & "BYPASS(11111)," & "EFUSE_CUTTING(10100)," & "EFUSE_BYPASS(10101)," & "REDUN_OUT(10110)," & "BIST_RESULT_ENABLE(11000)," & "FB_STATE_ENABLE(11001)"; --ENDOPCODE-- -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of PEX8112AA_FBGA_r1: entity is "00001"; attribute INSTRUCTION_PRIVATE of PEX8112AA_FBGA_r1: entity is "CSP, COREBYPASS, MUXSCAN, SCAN, DELAY, D_SELECT, NECHIGHZ, NECINTEST, EFUSE_CUTTING, EFUSE_BYPASS, REDUN_OUT, BIST_RESULT_ENABLE, FB_STATE_ENABLE"; -- Specifies the bit pattern that is loaded into the DEVICE_ID attribute IDCODE_REGISTER of PEX8112AA_FBGA_r1: entity is "00011000000111010010000000100001"; attribute BOUNDARY_LENGTH of PEX8112AA_FBGA_r1 : entity is 150; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of PEX8112AA_FBGA_r1 : entity is -- -- num cell port function safe [ccell disval rslt] -- "0 ( BC_7, PCLKO62SELn, bidir, X, 1, 0, PULL1 )," & "1 ( BC_2, *, control, 0 )," & "2 ( BC_7, BAR0ENBn, bidir, X, 3, 0, PULL1 )," & "3 ( BC_2, *, control, 0 )," & "4 ( BC_7, M66EN, bidir, X, 5, 0, Z )," & "5 ( BC_2, *, control, 0 )," & "6 ( BC_7, PCLKO, bidir, X, 7, 0, Z )," & "7 ( BC_2, *, control, 0 )," & "8 ( BC_7, GPIO0, bidir, X, 9, 0, PULL1 )," & "9 ( BC_2, *, control, 0 )," & "10 ( BC_7, GPIO1, bidir, X, 11, 0, PULL1 )," & "11 ( BC_2, *, control, 0 )," & "12 ( BC_7, GPIO2, bidir, X, 13, 0, PULL1 )," & "13 ( BC_2, *, control, 0 )," & "14 ( BC_7, GPIO3, bidir, X, 15, 0, PULL1 )," & "15 ( BC_2, *, control, 0 )," & "16 ( BC_7, LOCKn, bidir, X, 17, 0, Z )," & "17 ( BC_2, *, control, 0 )," & "18 ( BC_7, IDSEL, bidir, X, 19, 0, Z )," & "19 ( BC_2, *, control, 0 )," & "20 ( BC_7, PCLKI, bidir, X, 21, 0, Z )," & "21 ( BC_2, *, control, 0 )," & "22 ( BC_7, PMEINn, bidir, X, 23, 0, Z )," & "23 ( BC_2, *, control, 0 )," & "24 ( BC_7, INTDn, bidir, X, 25, 0, Z )," & "25 ( BC_2, *, control, 0 )," & "26 ( BC_7, SERRn, bidir, X, 27, 0, Z )," & "27 ( BC_2, *, control, 0 )," & "28 ( BC_7, PERRn, bidir, X, 29, 0, Z )," & "29 ( BC_2, *, control, 0 )," & "30 ( BC_7, GNT0n, bidir, X, 31, 0, Z )," & "31 ( BC_2, *, control, 0 )," & "32 ( BC_7, GNT1n, bidir, X, 33, 0, Z )," & "33 ( BC_2, *, control, 0 )," & "34 ( BC_7, GNT2n, bidir, X, 35, 0, Z )," & "35 ( BC_2, *, control, 0 )," & "36 ( BC_7, GNT3n, bidir, X, 37, 0, Z )," & "37 ( BC_2, *, control, 0 )," & "38 ( BC_7, REQ0n, bidir, X, 39, 0, Z )," & "39 ( BC_2, *, control, 0 )," & "40 ( BC_7, REQ1n, bidir, X, 41, 0, Z )," & "41 ( BC_2, *, control, 0 )," & "42 ( BC_7, REQ2n, bidir, X, 43, 0, Z )," & "43 ( BC_2, *, control, 0 )," & "44 ( BC_7, REQ3n, bidir, X, 45, 0, Z )," & "45 ( BC_2, *, control, 0 )," & "46 ( BC_7, DEVSELn, bidir, X, 47, 0, Z )," & "47 ( BC_2, *, control, 0 )," & "48 ( BC_7, STOPn, bidir, X, 49, 0, Z )," & "49 ( BC_2, *, control, 0 )," & "50 ( BC_7, TRDYn, bidir, X, 51, 0, Z )," & "51 ( BC_2, *, control, 0 )," & "52 ( BC_7, IRDYn, bidir, X, 53, 0, Z )," & "53 ( BC_2, *, control, 0 )," & "54 ( BC_7, FRAMEn, bidir, X, 55, 0, Z )," & "55 ( BC_2, *, control, 0 )," & "56 ( BC_7, PAR, bidir, X, 57, 0, Z )," & "57 ( BC_2, *, control, 0 )," & "58 ( BC_7, CBE0n, bidir, X, 59, 0, Z )," & "59 ( BC_2, *, control, 0 )," & "60 ( BC_7, CBE1n, bidir, X, 61, 0, Z )," & "61 ( BC_2, *, control, 0 )," & "62 ( BC_7, CBE2n, bidir, X, 63, 0, Z )," & "63 ( BC_2, *, control, 0 )," & "64 ( BC_7, CBE3n, bidir, X, 65, 0, Z )," & "65 ( BC_2, *, control, 0 )," & "66 ( BC_7, AD0, bidir, X, 67, 0, Z )," & "67 ( BC_2, *, control, 0 )," & "68 ( BC_7, AD1, bidir, X, 69, 0, Z )," & "69 ( BC_2, *, control, 0 )," & "70 ( BC_7, AD2, bidir, X, 71, 0, Z )," & "71 ( BC_2, *, control, 0 )," & "72 ( BC_7, AD3, bidir, X, 73, 0, Z )," & "73 ( BC_2, *, control, 0 )," & "74 ( BC_7, AD4, bidir, X, 75, 0, Z )," & "75 ( BC_2, *, control, 0 )," & "76 ( BC_7, AD5, bidir, X, 77, 0, Z )," & "77 ( BC_2, *, control, 0 )," & "78 ( BC_7, AD6, bidir, X, 79, 0, Z )," & "79 ( BC_2, *, control, 0 )," & "80 ( BC_7, AD7, bidir, X, 81, 0, Z )," & "81 ( BC_2, *, control, 0 )," & "82 ( BC_7, AD8, bidir, X, 83, 0, Z )," & "83 ( BC_2, *, control, 0 )," & "84 ( BC_7, AD9, bidir, X, 85, 0, Z )," & "85 ( BC_2, *, control, 0 )," & "86 ( BC_7, AD10, bidir, X, 87, 0, Z )," & "87 ( BC_2, *, control, 0 )," & "88 ( BC_7, AD11, bidir, X, 89, 0, Z )," & "89 ( BC_2, *, control, 0 )," & "90 ( BC_7, AD12, bidir, X, 91, 0, Z )," & "91 ( BC_2, *, control, 0 )," & "92 ( BC_7, AD13, bidir, X, 93, 0, Z )," & "93 ( BC_2, *, control, 0 )," & "94 ( BC_7, AD14, bidir, X, 95, 0, Z )," & "95 ( BC_2, *, control, 0 )," & "96 ( BC_7, AD15, bidir, X, 97, 0, Z )," & "97 ( BC_2, *, control, 0 )," & "98 ( BC_7, AD16, bidir, X, 99, 0, Z )," & "99 ( BC_2, *, control, 0 )," & "100 ( BC_7, AD17, bidir, X, 101, 0, Z )," & "101 ( BC_2, *, control, 0 )," & "102 ( BC_7, AD18, bidir, X, 103, 0, Z )," & "103 ( BC_2, *, control, 0 )," & "104 ( BC_7, AD19, bidir, X, 105, 0, Z )," & "105 ( BC_2, *, control, 0 )," & "106 ( BC_7, AD20, bidir, X, 107, 0, Z )," & "107 ( BC_2, *, control, 0 )," & "108 ( BC_7, AD21, bidir, X, 109, 0, Z )," & "109 ( BC_2, *, control, 0 )," & "110 ( BC_7, AD22, bidir, X, 111, 0, Z )," & "111 ( BC_2, *, control, 0 )," & "112 ( BC_7, AD23, bidir, X, 113, 0, Z )," & "113 ( BC_2, *, control, 0 )," & "114 ( BC_7, AD24, bidir, X, 115, 0, Z )," & "115 ( BC_2, *, control, 0 )," & "116 ( BC_7, AD25, bidir, X, 117, 0, Z )," & "117 ( BC_2, *, control, 0 )," & "118 ( BC_7, AD26, bidir, X, 119, 0, Z )," & "119 ( BC_2, *, control, 0 )," & "120 ( BC_7, AD27, bidir, X, 121, 0, Z )," & "121 ( BC_2, *, control, 0 )," & "122 ( BC_7, AD28, bidir, X, 123, 0, Z )," & "123 ( BC_2, *, control, 0 )," & "124 ( BC_7, AD29, bidir, X, 125, 0, Z )," & "125 ( BC_2, *, control, 0 )," & "126 ( BC_7, AD30, bidir, X, 127, 0, Z )," & "127 ( BC_2, *, control, 0 )," & "128 ( BC_7, AD31, bidir, X, 129, 0, Z )," & "129 ( BC_2, *, control, 0 )," & "130 ( BC_7, PCIRSTn, bidir, X, 131, 0, Z )," & "131 ( BC_2, *, control, 0 )," & "132 ( BC_7, PERSTn, bidir, X, 133, 0, Z )," & "133 ( BC_2, *, control, 0 )," & "134 ( BC_1, PWR_OK, output2, X )," & "135 ( BC_1, EEWRDATA, output2, X )," & "136 ( BC_1, EECLK, output2, X )," & "137 ( BC_1, EECSn, output2, X )," & "138 ( BC_1, PMEOUTn, output2, 1, 138, 1, Weak1 )," & "139 ( BC_1, WAKEOUTn, output2, 1, 139, 1, Weak1 )," & "140 ( BC_4, EXTARB, input, X )," & "141 ( BC_4, FORWARD, input, X )," & "142 ( BC_4, EERDDATA, input, X )," & "143 ( BC_4, WAKEINn, input, X )," & "144 ( BC_7, INTCn, bidir, X, 145, 0, Z )," & "145 ( BC_2, *, control, 0 )," & "146 ( BC_7, INTAn, bidir, X, 147, 0, Z )," & "147 ( BC_2, *, control, 0 )," & "148 ( BC_7, INTBn, bidir, X, 149, 0, Z )," & "149 ( BC_2, *, control, 0 )"; end PEX8112AA_FBGA_r1;