--************************************************************************** --* --* File Name: UPD44164362.BSDL --* Version: 3.0 --* Date: June 12, 2003 --* Model: BSDL --* Simulator: None --* --* Dependencies: None --* --* Company: NEC Electronics Corporation --* Model: UPD44164362 (512K x 36 DDR SRAM CIO 2-Word Burst) --* --* Description: NEC 512K x 36 DDR SRAM 2-Word Burst CIO BSDL model --* --* Disclaimer: NEC Electronics Corporation does not guarantee functionality or accuracy --* of this model. NEC Electronics Corporation assumes no responsiblity --* for any problems arising from the use of this model. --* --* Limitation: IEEE 1149.1 Serial Boundary Scan (JTAG) --* --* Copyright (C) NEC Electronics Corporation 2002, 2003 --* All rights reserved --* --*************************************************************************/ entity UPD44164362 is generic (PHYSICAL_PIN_MAP : string := "FBGA"); port ( A: in bit_vector(0 to 18); CQ_n: buffer bit; R_W_n: in bit; BW2_n: in bit; K_n: in bit; BW1_n: in bit; LD_n: in bit; CQ: buffer bit; BW3_n: in bit; K: in bit; BW0_n: in bit; C: in bit; C_n: in bit; DLL: in bit; DQ: inout bit_vector (0 to 35); TMS: in bit; TDI: in bit; TCK: in bit; TDO: out bit; ZQ: in bit; VREF: linkage bit_vector(0 to 1); Vdd: linkage bit_vector(0 to 9); Vss: linkage bit_vector(0 to 26); VDDQ: linkage bit_vector(0 to 15); NC: linkage bit_vector(0 to 36)); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of UPD44164362 : entity is "STD_1149_1_1993"; attribute PIN_MAP of UPD44164362 : entity is PHYSICAL_PIN_MAP; constant FBGA:PIN_MAP_STRING:= " A: (C6,N6,P7,N7,R7,R8,P8,R9,A9,B8, " & " C7,C5,B4,R3,R4,P4,P5,N5,R5), " & --Address " CQ_n: A1, " & --Negative echo clock " R_W_n: A4, " & --Read/Write " BW2_n: A5, " & --BYTE WRITE " K_n: A6, " & --Input Negative Clock " BW1_n: A7, " & --BYTE WRITE " LD_n: A8, " & --Load " CQ: A11, " & --Positive Echo clock " BW3_n: B5, " & --BYTE WRITE " K: B6, " & --Input Positive Clock " BW0_n: B7, " & --BYTE WRITE " DLL: H1, " & --DLL Disable " C: P6, " & --Out Positive Clock " C_n: R6, " & --Out Negitive Clock " DQ: (P11,M11,L11,K11,J11,F11,E11,C11,B11,P10, " & " N11,M10,K10,J10,G11,E10,D11,C10,B3,D3,E3, " & " F3,G3,K3,L3,N3,P3,B2,C3,D2,F2,G2,J3,L2,M3,N2), " & " TMS: R10, " & --Test Mode Select " TDI: R11, " & --Test Data-In " TCK: R2, " & --Test Clock " TDO: R1, " & --Test Data-Out " ZQ: H11, " & --Input Impedance Match " VREF: (H2,H10), " & --HSTL Input Ref Voltage " VDD: (F5,F7,G5,G7,H5,H7,J5,J7,K5,K7), " & " VSS: (A2,A10,C4,C8,D4,D5,D6,D7,D8,E5,E6,E7,G6,F6, " & " H6,J6,K6,L5,L6,L7,M4,M5,M6,M7,M8,N4,N8), " & " VDDQ: (E4,E8,F4,F8,G4,G8,H3,H4,H8,H9,J4, " & " J8,K4,K8,L4,L8), " & " NC: (A3,B1,B9,B10,C1,C2,C9,D1,D9,D10,E1,E2,E9, " & " F1,F9,F10,G1,G9,G10,J1,J2,J9,K1,K2,K9, " & " L1,L9,L10,M1,M2,M9,N1,N9,N10,P1,P2,P9) " ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute INSTRUCTION_LENGTH of UPD44164362 : entity is 3; attribute INSTRUCTION_OPCODE of UPD44164362 : entity is "EXTEST (000), " & "IDCODE (001), " & "SAMPLEZ (010), " & "RESERV1 (011), " & "SAMPLE (100), " & --Sample/Preload "RESERV2 (101), " & "RESERV3 (110), " & "BYPASS (111) " ; attribute INSTRUCTION_CAPTURE of UPD44164362 : entity is "001"; attribute INSTRUCTION_PRIVATE of UPD44164362 : entity is "RESERV1, RESERV2 ,RESERV3" ; attribute IDCODE_REGISTER of UPD44164362 : entity is "0100" & --Reserved for version number "0000000000010100" & --Device ID "00000010000" & --NEC Vendor ID "1" ; --ID REGISTER PRESENCE INDICATOR attribute REGISTER_ACCESS of UPD44164362 : entity is "BOUNDARY (EXTEST,SAMPLEZ,SAMPLE), " & "BYPASS (BYPASS) " ; attribute BOUNDARY_LENGTH of UPD44164362 : entity is 107; attribute BOUNDARY_REGISTER of UPD44164362 : entity is "0 (BC_4, C_n, input, X), " & "1 (BC_4, C, input, X), " & "2 (BC_4, A(1), input, X), " & "3 (BC_4, A(2), input, X), " & "4 (BC_4, A(3), input, X), " & "5 (BC_4, A(4), input, X), " & "6 (BC_4, A(5), input, X), " & "7 (BC_4, A(6), input, X), " & "8 (BC_4, A(7), input, X), " & "9 (BC_7, DQ(0), bidir, X, 47, 0, Z), " & "10 (BC_7, DQ(9), bidir, X, 47, 0, Z), " & "11 (BC_4, *, internal, X), " & "12 (BC_4, *, internal, X), " & "13 (BC_7, DQ(11), bidir, X, 47, 0, Z), " & "14 (BC_7, DQ(10), bidir, X, 47, 0, Z), " & "15 (BC_4, *, internal, X), " & "16 (BC_4, *, internal, X), " & "17 (BC_7, DQ(2), bidir, X, 47, 0, Z), " & "18 (BC_7, DQ(1), bidir, X, 47, 0, Z), " & "19 (BC_4, *, internal, X), " & "20 (BC_4, *, internal, X), " & "21 (BC_7, DQ(3), bidir, X, 47, 0, Z), " & "22 (BC_7, DQ(12), bidir, X, 47, 0, Z), " & "23 (BC_4, *, internal, X), " & "24 (BC_4, *, internal, X), " & "25 (BC_7, DQ(13), bidir, X, 47, 0, Z), " & "26 (BC_7, DQ(4), bidir, X, 47, 0, Z), " & "27 (BC_4, ZQ, input, X), " & "28 (BC_4, *, internal, X), " & "29 (BC_4, *, internal, X), " & "30 (BC_7, DQ(5), bidir, X, 47, 0, Z), " & "31 (BC_7, DQ(14), bidir, X, 47, 0, Z), " & "32 (BC_4, *, internal, X), " & "33 (BC_4, *, internal, X), " & "34 (BC_7, DQ(6), bidir, X, 47, 0, Z), " & "35 (BC_7, DQ(15), bidir, X, 47, 0, Z), " & "36 (BC_4, *, internal, X), " & "37 (BC_4, *, internal, X), " & "38 (BC_7, DQ(17), bidir, X, 47, 0, Z), " & "39 (BC_7, DQ(16), bidir, X, 47, 0, Z), " & "40 (BC_4, *, internal, X), " & "41 (BC_4, *, internal, X), " & "42 (BC_7, DQ(8), bidir, X, 47, 0, Z), " & "43 (BC_7, DQ(7), bidir, X, 47, 0, Z), " & "44 (BC_4, *, internal, X), " & "45 (BC_4, *, internal, X), " & "46 (BC_9, CQ, output2, X), " & "47 (BC_2, *, controlr, 0), " & "48 (BC_4, A(8), input, X), " & "49 (BC_4, A(9), input, X), " & "50 (BC_4, A(10), input, X), " & "51 (BC_4, A(0), input, X), " & "52 (BC_4, LD_n, input, X), " & "53 (BC_4, BW1_n, input, X), " & "54 (BC_4, BW0_n, input, X), " & "55 (BC_4, K, input, X), " & "56 (BC_4, K_n, input, X), " & "57 (BC_4, BW3_n, input, X), " & "58 (BC_4, BW2_n, input, X), " & "59 (BC_4, R_W_n, input, X), " & "60 (BC_4, A(11), input, X), " & "61 (BC_4, A(12), input, X), " & "62 (BC_4, *, internal, X), " & "63 (BC_4, DLL, input, X), " & "64 (BC_9, CQ_n, output2, X), " & "65 (BC_7, DQ(27), bidir, X, 47, 0, Z), " & "66 (BC_7, DQ(18), bidir, X, 47, 0, Z), " & "67 (BC_4, *, internal, X), " & "68 (BC_4, *, internal, X), " & "69 (BC_7, DQ(19), bidir, X, 47, 0, Z), " & "70 (BC_7, DQ(28), bidir, X, 47, 0, Z), " & "71 (BC_4, *, internal, X), " & "72 (BC_4, *, internal, X), " & "73 (BC_7, DQ(20), bidir, X, 47, 0, Z), " & "74 (BC_7, DQ(29), bidir, X, 47, 0, Z), " & "75 (BC_4, *, internal, X), " & "76 (BC_4, *, internal, X), " & "77 (BC_7, DQ(30), bidir, X, 47, 0, Z), " & "78 (BC_7, DQ(21), bidir, X, 47, 0, Z), " & "79 (BC_4, *, internal, X), " & "80 (BC_4, *, internal, X), " & "81 (BC_7, DQ(22), bidir, X, 47, 0, Z), " & "82 (BC_7, DQ(31), bidir, X, 47, 0, Z), " & "83 (BC_4, *, internal, X), " & "84 (BC_4, *, internal, X), " & "85 (BC_7, DQ(23), bidir, X, 47, 0, Z), " & "86 (BC_7, DQ(32), bidir, X, 47, 0, Z), " & "87 (BC_4, *, internal, X), " & "88 (BC_4, *, internal, X), " & "89 (BC_7, DQ(33), bidir, X, 47, 0, Z), " & "90 (BC_7, DQ(24), bidir, X, 47, 0, Z), " & "91 (BC_4, *, internal, X), " & "92 (BC_4, *, internal, X), " & "93 (BC_7, DQ(25), bidir, X, 47, 0, Z), " & "94 (BC_7, DQ(34), bidir, X, 47, 0, Z), " & "95 (BC_4, *, internal, X), " & "96 (BC_4, *, internal, X), " & "97 (BC_7, DQ(26), bidir, X, 47, 0, Z), " & "98 (BC_7, DQ(35), bidir, X, 47, 0, Z), " & "99 (BC_4, *, internal, X), " & "100 (BC_4, *, internal, X), " & "101 (BC_4, A(13), input, X), " & "102 (BC_4, A(14), input, X), " & "103 (BC_4, A(15), input, X), " & "104 (BC_4, A(16), input, X), " & "105 (BC_4, A(17), input, X), " & "106 (BC_4, A(18), input, X) " ; end UPD44164362;