-- Copyright Intel Corporation 2000 --**************************************************************************** -- Intel Corporation makes no warranty for the use of its products -- and assumes no responsibility for any errors which may appear in -- this document nor does it make a commitment to update the information -- contained herein. --**************************************************************************** -- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1990 -- compliant devices. This language is under consideration by the IEEE for -- formal inclusion within a supplement to the 1149.1-1990 standard. The -- generation of the supplement entails an extensive IEEE review and a formal -- acceptance balloting procedure which may change the resultant form of the -- language. Be aware that this process may extend well into 1993, and at -- this time the IEEE does not endorse or hold an opinion on the language. --**************************************************************************** -- -- SA2 Coyanosa (TM) Processor BSDL Model -- Project code SA2 -- File **NOT** verified electrically -- --------------------------------------------------------- -- -- Author: Stephen D. Wunduke -- -- Rev 1.0 7 August 2000 entity SA2_Processor is generic(PHYSICAL_PIN_MAP : string:= "BGA"); port ( A : out bit_vector(15 downto 0 ); ABORT : in bit; BEN : out bit_vector(7 downto 0 ); NC0 : in bit; CWF : in bit; D : inout bit_vector(63 downto 0 ); DCB : inout bit_vector(7 downto 0 ); DVALID : in bit; HLDA : out bit; HOLD : in bit; LOCK : out bit; NADS : out bit; NFIQ : in bit; NIRQ : in bit; NRESETOUT : out bit; NTRST : in bit; NC1 : in bit; NC2 : in bit; PLLCFG : in bit; PWRSTATUS : out bit_vector(1 downto 0 ); NC4 : out bit; NC3 : out bit; TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; LOWVCC : in bit; LOWVPP : in bit; WRN : out bit; VSS : linkage bit_vector(69 downto 0); VCC : linkage bit_vector(16 downto 0); VCCP : linkage bit_vector(17 downto 0); VCCA : linkage bit ); use STD_1149_1_1990.all; use sa2_cells.all; attribute PIN_MAP of SA2_Processor : entity is PHYSICAL_PIN_MAP; constant BGA:PIN_MAP_STRING := "NC4: P16, " & "A: (U13, U14, P11, R12, U15, T14, R13, P12, U16, R14, U17, P13, " & " T16, R15, T17, R17), " & "D: (T12, U12, R11, U11, R10, T10, U10, P9, " & -- BITS 63 TO 56 " P7, R6, T6, R5, U5, T4, U4, U3, " & -- BITS 55 TO 48 " R1, P2, P1, N3, N1, M3, M2, L4, " & -- BITS 47 TO 40 " J1, H3, H2, H1, G4, G3, G1, F1, " & -- BITS 39 TO 32 " R9, U9, R8, T8, U8, R7, U7, U6, " & -- BITS 31 TO 24 " U2, R4, P5, U1, T2, T1, R3, P3, " & -- BITS 23 TO 16 " M1, L3, L1, K3, K2, K1, J4, J3, " & -- BITS 15 TO 8 " F3, F2, E4, E3, E1, D3, D2, D1), " & -- BITS 7 TO 0 -- -- "DCB: (C7, A6, D7, B6, C6, A5, A4, C5), " & -- BITS 7 TO 0 "BEN: (B10, A10, A9, C9, A8, B8, C8, A7), " & -- BITS 7 TO 0 -- -- "DVALID: B4, " & "NADS: C10, " & "LOCK: A11, " & "WRN: C11, " & "HOLD: D11, " & "NC3: A12, " & "CWF: B12, " & "ABORT: C12, " & "NRESETOUT: A13, " & "PWRSTATUS: (C13, A14), " & "HLDA: B14, " & -- -- "LOWVCC: D16, " & "NIRQ: E15, " & "NFIQ: E17, " & "PLLCFG: H16, " & "NC2: H17, " & "NC1: J17, " & "NC0: J15, " & "LOWVPP: M16, " & -- -- "TCK:L17,"& "TDI:M17,"& "TDO:P17,"& "TMS:P15,"& "NTRST:L15,"& -- -- "VSS: (A1, B2, G2, L2, R2, B3, C3, F4, H4, K4, N4, P4, B5, " & " D5, F5, M5, T5, D6, E6, N6, P6, D8, P8, B9, E9, T9, " & " D10, P10, E11, E12, N12, B13, D13, F13, M13, T13, " & " C14, D14, E14, F14, G14, J14, L14, N14, P14, A15, " & " C15, F15, G15, H15, K15, M15, N15, T15, B16, C16, " & " E16, F16, J16, N16, A17, H8, H9, H10, J8, J9, J10, " & " K8, K9, K10), " & "VCC: (C1, E2, A3, T3, M4, G5, L5, E7, N7, N11, D12, G13, " & " L13, B15, R16, B17, F17), " & "VCCP: (B1, A2, C2, J2, N2, C4, E5, J5, N5, B7, T7, D9, N9, " & " B11, T11, E13, J13, N13), " & "VCCA: K14"; attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Reset of NTRST : signal is true; attribute Tap_Scan_Clock of TCK : signal is (66.0e6, BOTH); attribute Instruction_Length of SA2_Processor: entity is 5; attribute Instruction_Opcode of SA2_Processor: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (00001)," & "IDCODE (11110)," & "CLAMP (00100)," & "HIGHZ (01000)," & "DBGRX (00010)," & "DCSR (01001)," & "DBGTX (10000)," & "Reserved (01011, 00011, 00101, 01111, 00110, 10001, 10011, 10100, 10101, 10110, 10111, " & " 00111, 01010, 01100, 01101, 11000, 11001, 10010, 11010, 11011, 11100, 11101, 01110) "; attribute Instruction_Capture of SA2_Processor: entity is "00001"; attribute Instruction_Private of SA2_Processor: entity is "Reserved" ; attribute Idcode_Register of SA2_Processor: entity is "0000" & --version, "1001001001100011" & --part number "00000001001" & --manufacturers identity "1"; --required by the standard attribute Register_Access of SA2_Processor: entity is "Dbg[36] (DBGRX, DBGTX, DCSR),"& "Bypass (CLAMP, HIGHZ)"; --{*******************************************************************} --{ The first cell, cell 0, is closest to TDO } --{ BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock } --{***************************************************************** attribute Boundary_Cells of SA2_Processor: entity is "BC_4, BC_1, CBSC_1"; attribute Boundary_Length of SA2_Processor: entity is 222; attribute Boundary_Register of SA2_Processor: entity is "0 (BC_4, lowvpp, input, X),"& "1 (BC_4, nc0, input, X),"& "2 (BC_4, nc1, input, X),"& "3 (BC_4, nc2, input, X),"& "4 (BC_4, pllcfg, input, X),"& "5 (BC_4, nfiq, input, X),"& "6 (BC_4, nirq, input, X),"& "7 (BC_4, lowvcc, input, X),"& "8 (BC_1, *, control, 0),"& "9 (BC_1, hlda, output3, X, 8, 0, Z),"& "10 (BC_1, *, control, 0),"& "11 (BC_1, pwrstatus(1), output3, X, 10, 0, Z),"& "12 (BC_1, *, control, 0),"& "13 (BC_1, pwrstatus(0), output3, X, 12, 0, Z),"& "14 (BC_1, *, control, 0),"& "15 (BC_1, nresetout, output3, X, 14, 0, Z),"& "16 (BC_4, abort, input, X),"& "17 (BC_4, cwf, input, X),"& "18 (BC_1, *, control, 0),"& "19 (BC_1, nc3, output3, X, 18, 0, Z),"& "20 (BC_4, hold, input, X),"& "21 (BC_1, *, control, 0),"& "22 (BC_1, wrn, output3, X, 21, 0, Z),"& "23 (BC_1, *, control, 0),"& "24 (BC_1, lock, output3, X, 23, 0, Z),"& "25 (BC_1, *, control, 0),"& "26 (BC_1, nads, output3, X, 25, 0, Z),"& "27 (BC_1, *, control, 0),"& "28 (BC_1, ben(7), output3, X, 27, 0, Z),"& "29 (BC_1, *, control, 0),"& "30 (BC_1, ben(6), output3, X, 29, 0, Z),"& "31 (BC_1, *, control, 0),"& "32 (BC_1, ben(5), output3, X, 31, 0, Z),"& "33 (BC_1, *, control, 0),"& "34 (BC_1, ben(4), output3, X, 33, 0, Z),"& "35 (BC_1, *, control, 0),"& "36 (BC_1, ben(3), output3, X, 35, 0, Z),"& "37 (BC_1, *, control, 0),"& "38 (BC_1, ben(2), output3, X, 37, 0, Z),"& "39 (BC_1, *, control, 0),"& "40 (BC_1, ben(1), output3, X, 39, 0, Z),"& "41 (BC_1, *, control, 0),"& "42 (BC_1, ben(0), output3, X, 41, 0, Z),"& "43 (BC_1, *, control, 0),"& "44 (CBSC_1, dcb(7), bidir, X, 43, 0, Z),"& "45 (BC_1, *, control, 0),"& "46 (CBSC_1, dcb(6), bidir, X, 45, 0, Z),"& "47 (BC_1, *, control, 0),"& "48 (CBSC_1, dcb(5), bidir, X, 47, 0, Z),"& "49 (BC_1, *, control, 0),"& "50 (CBSC_1, dcb(4), bidir, X, 49, 0, Z),"& "51 (BC_1, *, control, 0),"& "52 (CBSC_1, dcb(3), bidir, X, 51, 0, Z),"& "53 (BC_1, *, control, 0),"& "54 (CBSC_1, dcb(2), bidir, X, 53, 0, Z),"& "55 (BC_1, *, control, 0),"& "56 (CBSC_1, dcb(1), bidir, X, 55, 0, Z),"& "57 (BC_1, *, control, 0),"& "58 (CBSC_1, dcb(0), bidir, X, 57, 0, Z),"& "59 (BC_4, dvalid, input, X),"& "60 (BC_1, *, control, 0),"& "61 (CBSC_1, d(2), bidir, X, 60, 0, Z),"& "62 (BC_1, *, control, 0),"& "63 (CBSC_1, d(5), bidir, X, 62, 0, Z),"& "64 (BC_1, *, control, 0),"& "65 (CBSC_1, d(1), bidir, X, 64, 0, Z),"& "66 (BC_1, *, control, 0),"& "67 (CBSC_1, d(4), bidir, X, 66, 0, Z),"& "68 (BC_1, *, control, 0),"& "69 (CBSC_1, d(0), bidir, X, 68, 0, Z),"& "70 (BC_1, *, control, 0),"& "71 (CBSC_1, d(3), bidir, X, 70, 0, Z),"& "72 (BC_1, *, control, 0),"& "73 (CBSC_1, d(7), bidir, X, 72, 0, Z),"& "74 (BC_1, *, control, 0),"& "75 (CBSC_1, d(6), bidir, X, 74, 0, Z),"& "76 (BC_1, *, control, 0),"& "77 (CBSC_1, d(35), bidir, X, 76, 0, Z),"& "78 (BC_1, *, control, 0),"& "79 (CBSC_1, d(32), bidir, X, 78, 0, Z),"& "80 (BC_1, *, control, 0),"& "81 (CBSC_1, d(34), bidir, X, 80, 0, Z),"& "82 (BC_1, *, control, 0),"& "83 (CBSC_1, d(33), bidir, X, 82, 0, Z),"& "84 (BC_1, *, control, 0),"& "85 (CBSC_1, d(38), bidir, X, 84, 0, Z),"& "86 (BC_1, *, control, 0),"& "87 (CBSC_1, d(37), bidir, X, 86, 0, Z),"& "88 (BC_1, *, control, 0),"& "89 (CBSC_1, d(36), bidir, X, 88, 0, Z),"& "90 (BC_1, *, control, 0),"& "91 (CBSC_1, d(39), bidir, X, 90, 0, Z),"& "92 (BC_1, *, control, 0),"& "93 (CBSC_1, d(8), bidir, X, 92, 0, Z),"& "94 (BC_1, *, control, 0),"& "95 (CBSC_1, d(9), bidir, X, 94, 0, Z),"& "96 (BC_1, *, control, 0),"& "97 (CBSC_1, d(10), bidir, X, 96, 0, Z),"& "98 (BC_1, *, control, 0),"& "99 (CBSC_1, d(11), bidir, X, 98, 0, Z),"& "100 (BC_1, *, control, 0),"& "101 (CBSC_1, d(12), bidir, X, 100, 0, Z),"& "102 (BC_1, *, control, 0),"& "103 (CBSC_1, d(13), bidir, X, 102, 0, Z),"& "104 (BC_1, *, control, 0),"& "105 (CBSC_1, d(15), bidir, X, 104, 0, Z),"& "106 (BC_1, *, control, 0),"& "107 (CBSC_1, d(14), bidir, X, 106, 0, Z),"& "108 (BC_1, *, control, 0),"& "109 (CBSC_1, d(41), bidir, X, 108, 0, Z),"& "110 (BC_1, *, control, 0),"& "111 (CBSC_1, d(43), bidir, X, 110, 0, Z),"& "112 (BC_1, *, control, 0),"& "113 (CBSC_1, d(40), bidir, X, 112, 0, Z),"& "114 (BC_1, *, control, 0),"& "115 (CBSC_1, d(42), bidir, X, 114, 0, Z),"& "116 (BC_1, *, control, 0),"& "117 (CBSC_1, d(45), bidir, X, 116, 0, Z),"& "118 (BC_1, *, control, 0),"& "119 (CBSC_1, d(44), bidir, X, 118, 0, Z),"& "120 (BC_1, *, control, 0),"& "121 (CBSC_1, d(46), bidir, X, 120, 0, Z),"& "122 (BC_1, *, control, 0),"& "123 (CBSC_1, d(47), bidir, X, 122, 0, Z),"& "124 (BC_1, *, control, 0),"& "125 (CBSC_1, d(16), bidir, X, 124, 0, Z),"& "126 (BC_1, *, control, 0),"& "127 (CBSC_1, d(18), bidir, X, 126, 0, Z),"& "128 (BC_1, *, control, 0),"& "129 (CBSC_1, d(17), bidir, X, 128, 0, Z),"& "130 (BC_1, *, control, 0),"& "131 (CBSC_1, d(19), bidir, X, 130, 0, Z),"& "132 (BC_1, *, control, 0),"& "133 (CBSC_1, d(20), bidir, X, 132, 0, Z),"& "134 (BC_1, *, control, 0),"& "135 (CBSC_1, d(21), bidir, X, 134, 0, Z),"& "136 (BC_1, *, control, 0),"& "137 (CBSC_1, d(22), bidir, X, 136, 0, Z),"& "138 (BC_1, *, control, 0),"& "139 (CBSC_1, d(23), bidir, X, 138, 0, Z),"& "140 (BC_1, *, control, 0),"& "141 (CBSC_1, d(48), bidir, X, 140, 0, Z),"& "142 (BC_1, *, control, 0),"& "143 (CBSC_1, d(52), bidir, X, 142, 0, Z),"& "144 (BC_1, *, control, 0),"& "145 (CBSC_1, d(50), bidir, X, 144, 0, Z),"& "146 (BC_1, *, control, 0),"& "147 (CBSC_1, d(49), bidir, X, 146, 0, Z),"& "148 (BC_1, *, control, 0),"& "149 (CBSC_1, d(54), bidir, X, 148, 0, Z),"& "150 (BC_1, *, control, 0),"& "151 (CBSC_1, d(51), bidir, X, 150, 0, Z),"& "152 (BC_1, *, control, 0),"& "153 (CBSC_1, d(55), bidir, X, 152, 0, Z),"& "154 (BC_1, *, control, 0),"& "155 (CBSC_1, d(53), bidir, X, 154, 0, Z),"& "156 (BC_1, *, control, 0),"& "157 (CBSC_1, d(26), bidir, X, 156, 0, Z),"& "158 (BC_1, *, control, 0),"& "159 (CBSC_1, d(24), bidir, X, 158, 0, Z),"& "160 (BC_1, *, control, 0),"& "161 (CBSC_1, d(25), bidir, X, 160, 0, Z),"& "162 (BC_1, *, control, 0),"& "163 (CBSC_1, d(29), bidir, X, 162, 0, Z),"& "164 (BC_1, *, control, 0),"& "165 (CBSC_1, d(28), bidir, X, 164, 0, Z),"& "166 (BC_1, *, control, 0),"& "167 (CBSC_1, d(27), bidir, X, 166, 0, Z),"& "168 (BC_1, *, control, 0),"& "169 (CBSC_1, d(30), bidir, X, 168, 0, Z),"& "170 (BC_1, *, control, 0),"& "171 (CBSC_1, d(31), bidir, X, 170, 0, Z),"& "172 (BC_1, *, control, 0),"& "173 (CBSC_1, d(56), bidir, X, 172, 0, Z),"& "174 (BC_1, *, control, 0),"& "175 (CBSC_1, d(57), bidir, X, 174, 0, Z),"& "176 (BC_1, *, control, 0),"& "177 (CBSC_1, d(58), bidir, X, 176, 0, Z),"& "178 (BC_1, *, control, 0),"& "179 (CBSC_1, d(59), bidir, X, 178, 0, Z),"& "180 (BC_1, *, control, 0),"& "181 (CBSC_1, d(60), bidir, X, 180, 0, Z),"& "182 (BC_1, *, control, 0),"& "183 (CBSC_1, d(62), bidir, X, 182, 0, Z),"& "184 (BC_1, *, control, 0),"& "185 (CBSC_1, d(61), bidir, X, 184, 0, Z),"& "186 (BC_1, *, control, 0),"& "187 (CBSC_1, d(63), bidir, X, 186, 0, Z),"& "188 (BC_1, *, control, 0),"& "189 (BC_1, a(15), output3, X, 188, 0, Z),"& "190 (BC_1, *, control, 0),"& "191 (BC_1, a(14), output3, X, 190, 0, Z),"& "192 (BC_1, *, control, 0),"& "193 (BC_1, a(13), output3, X, 192, 0, Z),"& "194 (BC_1, *, control, 0),"& "195 (BC_1, a(12), output3, X, 194, 0, Z),"& "196 (BC_1, *, control, 0),"& "197 (BC_1, a(11), output3, X, 196, 0, Z),"& "198 (BC_1, *, control, 0),"& "199 (BC_1, a(10), output3, X, 198, 0, Z),"& "200 (BC_1, *, control, 0),"& "201 (BC_1, a(9), output3, X, 200, 0, Z),"& "202 (BC_1, *, control, 0),"& "203 (BC_1, a(8), output3, X, 202, 0, Z),"& "204 (BC_1, *, control, 0),"& "205 (BC_1, a(7), output3, X, 204, 0, Z),"& "206 (BC_1, *, control, 0),"& "207 (BC_1, a(6), output3, X, 206, 0, Z),"& "208 (BC_1, *, control, 0),"& "209 (BC_1, a(5), output3, X, 208, 0, Z),"& "210 (BC_1, *, control, 0),"& "211 (BC_1, a(4), output3, X, 210, 0, Z),"& "212 (BC_1, *, control, 0),"& "213 (BC_1, a(3), output3, X, 212, 0, Z),"& "214 (BC_1, *, control, 0),"& "215 (BC_1, a(2), output3, X, 214, 0, Z),"& "216 (BC_1, *, control, 0),"& "217 (BC_1, a(1), output3, X, 216, 0, Z),"& "218 (BC_1, *, control, 0),"& "219 (BC_1, a(0), output3, X, 218, 0, Z),"& "220 (BC_1, *, control, 0),"& "221 (BC_1, nc4, output3, X, 220, 0, Z)"; end SA2_Processor;