-- ******************************************************** -- Document Number: 3591862.BS002.04 -- BSDL file for design CA91L862A (Production) -- Created by Testgen (Aug 13, 1999) -- Company: Integrated Device Technology, Inc. -- Notice: HP Syntax checker -- History: 01 -> Original -- 02 -> VIO modified from "in bit" to "linkage bit" -- 03 -> Add new pins -> new functionality -- 002.01 -> Add new package -- 002.02 -> Rename signals (qspan12 pinout -- compatibility) -- 002.03 -> Remove the VIO pin from the PIN_MAP list -- (Now -- connected to VDD) -- Update the IDCODE rev. number -- 03 -> updated with IDT formatting -- ********************************************************* entity CA91L862A is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP : string := "UNDEFINED"); -- This section declares all the ports in the design. port ( DONE :in bit; BG :in bit; QCLK :in bit; RESETI :in bit; CSPCI :in bit; IDSEL :in bit; CSREG :in bit; RST :in bit; PCLK :in bit; DACK :in bit; IMSEL :in bit; TCK :in bit; ENID :in bit; BM_EN :inout bit; A :inout bit_vector(0 to 31); TRDY :inout bit; PAR :inout bit; D :inout bit_vector(0 to 31); DP :inout bit_vector(0 to 3); FRAME :inout bit; CBE :inout bit_vector(0 to 3); AS :inout bit; DSACK1 :inout bit; SIZ :inout bit_vector(0 to 1); TC :inout bit_vector(0 to 3); SDA :inout bit; TMODE : linkage bit_vector(0 to 1); DEVSEL :inout bit; BB :inout bit; AD :inout bit_vector(0 to 31); STOP :inout bit; TS :inout bit; EXT_REQ :inout bit_vector(1 to 6); RW :inout bit; HALT :inout bit; INT :inout bit; BERR :inout bit; BURST :inout bit; DSACK0 :inout bit; IRDY :inout bit; PERR :inout bit; TMS :in bit; TDI :in bit; TRST :in bit; SERR :inout bit; QINT :inout bit; BDIP :inout bit; PCI_DIS :in bit; HS_SWITCH :in bit; HS_HEALTHY :in bit; PCI_ARB_EN :in bit; REQ :inout bit; GNT :inout bit; TEST1 :linkage bit; TEST2 :linkage bit; TEST3 :linkage bit; TDO :out bit; ENUM :out bit; PME :out bit; RESETO :out bit; BR :out bit; EXT_GNT :out bit_vector(1 to 6); DS :out bit; HS_LED :out bit; DREQ :out bit; SCL :out bit ); use STD_1149_1_1990.all; attribute PIN_MAP of CA91L862A: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant PBGA_27mm : PIN_MAP_STRING := "EXT_GNT : (V5, W5, Y5, V6, U7, W6), " & "EXT_REQ : (Y17, V16, W17, Y18, U16, V17), " & "TEST1 : B15," & "TEST2 : D14," & "DP : (C6, B5, A4, C5), " & "PCI_ARB_EN : B4, " & "BG : M18," & "CSPCI : R20," & "CSREG : T19," & "DACK : K19," & "DONE : K17," & "GNT : U2," & "IDSEL : Y16," & "IMSEL : L1," & "PCLK : W11," & "QCLK : A10," & "RESETI : M3," & "RST : P4," & "TCK : J20," & "TDI : L18," & "TMS : K20," & "TRST : K18," & "TMODE : (M1, L3)," & "TEST3 : C15," & "AS : N20," & "BB : R1," & "BDIP : M17," & "BERR : N19," & "BM_EN : M20," & "BURST : N3," & "DEVSEL : Y11," & "DSACK0 : J4," & "DSACK1 : H1," & "ENID : J18," & "FRAME : W10," & "HALT : T1," & "INT : T18," & "IRDY : V10," & "PAR : Y12," & "PERR : U11," & "QINT : J19," & "RW : G3," & "SDA : J1," & "SERR : U20," & "STOP : V11," & "TRDY : Y10," & "TS : P2," & "A : (G20, G19, F20, F19, E20, G17, C17, B17, A18, " & "B16, C16, C14, B14, A14, C13, B13, D10, A9, C9, D9, B8, C8, " & "A7, B7, A6, C7, E3, E1, F2, G2, H3, H2)," & "AD : (V20, U18, W20, V19, Y20, V18, W18, U14, V14, Y15, " & "W14, Y14, V13, W13, Y13, V12, W9, U9, Y8, W8, V8, Y7, V7, U5, " & "W3, Y2, Y1, W2, W1, U3, V2, T4)," & "CBE : (W15, W12, Y9, W4)," & "D : (F18, E19, E18, E17, C20, D18, B20, B19, C18, A20, " & "B18, A19, D12, C12, B12, B11, C11, A11, B10, C10, B6, D7, A3, " & "C4, D5, B3, A2, C2, B1, D3, C1, E4)," & "SIZ : (J2, J3)," & "TC : (P18, P19, P20, N18)," & "BR : R2," & "DREQ : J17," & "DS : A13," & "REQ : T3," & "RESETO : N1," & "SCL : K3," & "TDO : M19," & "PCI_DIS : M4," & "HS_SWITCH : L4," & "HS_HEALTHY : N2," & "ENUM : K1," & "PME : M2," & "HS_LED : L2 "; constant PBGA_17mm : PIN_MAP_STRING := "EXT_GNT : (R1, R4, T3, P4, R5, T4), " & "EXT_REQ : (T11, R12, N13, P13, T12, R13), " & "TEST1 : B12," & "TEST2 : A14," & "DP : (A5, C5, B5, D4), " & "PCI_ARB_EN : C4, " & "BG : K16," & "CSPCI : P16," & "CSREG : M13," & "DACK : J13," & "DONE : J15," & "GNT : M3," & "IDSEL : N12," & "IMSEL : H4," & "PCLK : P8," & "QCLK : D8," & "RESETI : J4," & "RST : M2," & "TCK : H13," & "TDI : K15," & "TMS : J16," & "TRST : H14," & "TMODE : (J3, H1)," & "TEST3 : C12," & "AS : L16," & "BB : L2," & "BDIP : K14," & "BERR : L15," & "BM_EN : J14," & "BURST : L4," & "DEVSEL : R8," & "DSACK0 : G3," & "DSACK1 : F1," & "ENID : H15," & "FRAME : P7," & "HALT : M1," & "INT : M14," & "IRDY : R7," & "PAR : N10," & "PERR : N9," & "QINT : H16," & "RW : D1," & "SDA : G1," & "SERR : M15," & "STOP : T7," & "TRDY : N8," & "TS : K2," & "A : (G14, G16, G15, F14, F16, E16, C13, B16, C14, " & "A15, D12, C11, D11, A13, A12, B11, A9, D7, B8, C7, A8, A7, " & "B7, D6, C6, A6, C1, E3, E4, E1, F3, F2)," & "AD : (N15, N14, T16, P15, T14, T13, P14, P12, T10, P11, " & "N11, P10, R10, T9, T8, P9, P6, T6, T5, R6, N6, P5, N5, T1, " & "R2, R3, P3, N3, N4, P2, P1, N2)," & "CBE : (R11, R9, N7, T2)," & "D : (F15, E15, E14, D16, D15, F13, E13, D14, C16, C15, " & "B14, B15, D10, A11, D9, B10, C9, A10, B9, C8, B6, D5, A4, " & "A3, B4, A2, B3, C3, B1, D3, D2, C2)," & "SIZ : (G2, F4)," & "TC : (N16, L14, M16, L13)," & "BR : L1," & "DREQ : G13," & "DS : C10," & "REQ : M4," & "RESETO : K1," & "SCL : H3," & "TDO : K13," & "PCI_DIS : K3," & "HS_SWITCH : J2," & "HS_HEALTHY : K4," & "ENUM : G4," & "PME : J1," & "HS_LED : H2 "; attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST : signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of CA91L862A: entity is 2; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of CA91L862A: entity is "BYPASS (11)," & "EXTEST (00)," & "SAMPLE (01)," & "IDCODE (10)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of CA91L862A: entity is "01"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of CA91L862A: entity is "0010" & -- version "1000011000100000" & -- part number "00010110011" & -- manufacturer's identity "1"; -- required by 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of CA91L862A: entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST, SAMPLE)," & "IDCODE (IDCODE)"; attribute BOUNDARY_CELLS of CA91L862A : entity is "BC_1, BC_4"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of CA91L862A: entity is 354; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of CA91L862A: entity is -- -- num cell port function safe [ccell disval rslt] -- "353 (BC_1, DACK, input, X)," & "352 (BC_1, DONE, input, X)," & "351 (BC_1, QINT, output2, 1, 351, 1, Weak1)," & -- open drain output "350 (BC_1, QINT, input, X)," & "349 (BC_1, ENID, input, X)," & "348 (BC_1, DREQ, output3, X, 347, 1, Z)," & "347 (BC_1, *, control, 1)," & "346 (BC_1, *, control, 1)," & "345 (BC_1, A(0), input, X)," & "344 (BC_1, A(0), output3, X, 346, 1, Z)," & "343 (BC_1, A(1), input, X)," & "342 (BC_1, A(1), output3, X, 346, 1, Z)," & "341 (BC_1, A(2), input, X)," & "340 (BC_1, A(2), output3, X, 346, 1, Z)," & "339 (BC_1, A(3), input, X)," & "338 (BC_1, A(3), output3, X, 346, 1, Z)," & "337 (BC_1, A(4), input, X)," & "336 (BC_1, A(4), output3, X, 346, 1, Z)," & "335 (BC_1, A(5), input, X)," & "334 (BC_1, A(5), output3, X, 346, 1, Z)," & "333 (BC_1, *, control, 1)," & "332 (BC_1, D(0), input, X)," & "331 (BC_1, D(0), output3, X, 333, 1, Z)," & "330 (BC_1, D(1), input, X)," & "329 (BC_1, D(1), output3, X, 333, 1, Z)," & "328 (BC_1, D(2), input, X)," & "327 (BC_1, D(2), output3, X, 333, 1, Z)," & "326 (BC_1, D(3), input, X)," & "325 (BC_1, D(3), output3, X, 333, 1, Z)," & "324 (BC_1, D(4), input, X)," & "323 (BC_1, D(4), output3, X, 333, 1, Z)," & "322 (BC_1, D(5), input, X)," & "321 (BC_1, D(5), output3, X, 333, 1, Z)," & "320 (BC_1, D(6), input, X)," & "319 (BC_1, D(6), output3, X, 333, 1, Z)," & "318 (BC_1, D(7), input, X)," & "317 (BC_1, D(7), output3, X, 333, 1, Z)," & "316 (BC_1, *, control, 1)," & "315 (BC_1, D(8), input, X)," & "314 (BC_1, D(8), output3, X, 316, 1, Z)," & "313 (BC_1, D(9), input, X)," & "312 (BC_1, D(9), output3, X, 316, 1, Z)," & "311 (BC_1, D(10), input, X)," & "310 (BC_1, D(10), output3, X, 316, 1, Z)," & "309 (BC_1, D(11), input, X)," & "308 (BC_1, D(11), output3, X, 316, 1, Z)," & "307 (BC_1, A(6), input, X)," & "306 (BC_1, A(6), output3, X, 346, 1, Z)," & "305 (BC_1, A(7), input, X)," & "304 (BC_1, A(7), output3, X, 346, 1, Z)," & "303 (BC_1, *, control, 1)," & "302 (BC_1, A(8), input, X)," & "301 (BC_1, A(8), output3, X, 303, 1, Z)," & "300 (BC_1, A(9), input, X)," & "299 (BC_1, A(9), output3, X, 303, 1, Z)," & "298 (BC_1, A(10), input, X)," & "297 (BC_1, A(10), output3, X, 303, 1, Z)," & "296 (BC_1, A(11), input, X)," & "295 (BC_1, A(11), output3, X, 303, 1, Z)," & "294 (BC_1, A(12), input, X)," & "293 (BC_1, A(12), output3, X, 303, 1, Z)," & "292 (BC_1, A(13), input, X)," & "291 (BC_1, A(13), output3, X, 303, 1, Z)," & "290 (BC_1, A(14), input, X)," & "289 (BC_1, A(14), output3, X, 303, 1, Z)," & "288 (BC_1, A(15), input, X)," & "287 (BC_1, A(15), output3, X, 303, 1, Z)," & "286 (BC_1, *, control, 1)," & "285 (BC_1, DS, output3, X, 286, 1, Z)," & "284 (BC_1, D(12), input, X)," & "283 (BC_1, D(12), output3, X, 316, 1, Z)," & "282 (BC_1, D(13), input, X)," & "281 (BC_1, D(13), output3, X, 316, 1, Z)," & "280 (BC_1, D(14), input, X)," & "279 (BC_1, D(14), output3, X, 316, 1, Z)," & "278 (BC_1, D(15), input, X)," & "277 (BC_1, D(15), output3, X, 316, 1, Z)," & "276 (BC_1, *, control, 1)," & "275 (BC_1, D(16), input, X)," & "274 (BC_1, D(16), output3, X, 276, 1, Z)," & "273 (BC_1, D(17), input, X)," & "272 (BC_1, D(17), output3, X, 276, 1, Z)," & "271 (BC_4, QCLK, input, X)," & "270 (BC_1, D(18), input, X)," & "269 (BC_1, D(18), output3, X, 276, 1, Z)," & "268 (BC_1, D(19), input, X)," & "267 (BC_1, D(19), output3, X, 276, 1, Z)," & "266 (BC_1, *, control, 1)," & "265 (BC_1, A(16), input, X)," & "264 (BC_1, A(16), output3, X, 266, 1, Z)," & "263 (BC_1, A(17), input, X)," & "262 (BC_1, A(17), output3, X, 266, 1, Z)," & "261 (BC_1, A(18), input, X)," & "260 (BC_1, A(18), output3, X, 266, 1, Z)," & "259 (BC_1, A(19), input, X)," & "258 (BC_1, A(19), output3, X, 266, 1, Z)," & "257 (BC_1, A(20), input, X)," & "256 (BC_1, A(20), output3, X, 266, 1, Z)," & "255 (BC_1, A(21), input, X)," & "254 (BC_1, A(21), output3, X, 266, 1, Z)," & "253 (BC_1, A(22), input, X)," & "252 (BC_1, A(22), output3, X, 266, 1, Z)," & "251 (BC_1, A(23), input, X)," & "250 (BC_1, A(23), output3, X, 266, 1, Z)," & "249 (BC_1, *, control, 1)," & "248 (BC_1, A(24), input, X)," & "247 (BC_1, A(24), output3, X, 249, 1, Z)," & "246 (BC_1, A(25), input, X)," & "245 (BC_1, A(25), output3, X, 249, 1, Z)," & "244 (BC_1, D(20), input, X)," & "243 (BC_1, D(20), output3, X, 276, 1, Z)," & "242 (BC_1, D(21), input, X)," & "241 (BC_1, D(21), output3, X, 276, 1, Z)," & "240 (BC_1, D(22), input, X)," & "239 (BC_1, D(22), output3, X, 276, 1, Z)," & "238 (BC_1, D(23), input, X)," & "237 (BC_1, D(23), output3, X, 276, 1, Z)," & "236 (BC_1, *, control, 1)," & "235 (BC_1, D(24), input, X)," & "234 (BC_1, D(24), output3, X, 236, 1, Z)," & "233 (BC_1, D(25), input, X)," & "232 (BC_1, D(25), output3, X, 236, 1, Z)," & "231 (BC_1, D(26), input, X)," & "230 (BC_1, D(26), output3, X, 236, 1, Z)," & "229 (BC_1, D(27), input, X)," & "228 (BC_1, D(27), output3, X, 236, 1, Z)," & "227 (BC_1, D(28), input, X)," & "226 (BC_1, D(28), output3, X, 236, 1, Z)," & "225 (BC_1, D(29), input, X)," & "224 (BC_1, D(29), output3, X, 236, 1, Z)," & "223 (BC_1, D(30), input, X)," & "222 (BC_1, D(30), output3, X, 236, 1, Z)," & "221 (BC_1, D(31), input, X)," & "220 (BC_1, DP(3), input, X)," & "219 (BC_1, DP(2), input, X)," & "218 (BC_1, DP(1), input, X)," & "217 (BC_1, DP(0), input, X)," & "216 (BC_1, D(31), output3, X, 236, 1, Z)," & "215 (BC_1, DP(0), output3, X, 211, 1, Z)," & "214 (BC_1, DP(1), output3, X, 211, 1, Z)," & "213 (BC_1, DP(2), output3, X, 211, 1, Z)," & "212 (BC_1, DP(3), output3, X, 211, 1, Z)," & "211 (BC_1, *, control, 1)," & "210 (BC_1, A(26), input, X)," & "209 (BC_1, A(26), output3, X, 249, 1, Z)," & "208 (BC_1, A(27), input, X)," & "207 (BC_1, A(27), output3, X, 249, 1, Z)," & "206 (BC_1, A(28), input, X)," & "205 (BC_1, A(28), output3, X, 249, 1, Z)," & "204 (BC_1, RW, input, X)," & "203 (BC_1, RW, output3, X, 202, 1, Z)," & "202 (BC_1, *, control, 1)," & "201 (BC_1, A(29), input, X)," & "200 (BC_1, A(29), output3, X, 249, 1, Z)," & "199 (BC_1, A(30), input, X)," & "198 (BC_1, A(30), output3, X, 249, 1, Z)," & "197 (BC_1, A(31), input, X)," & "196 (BC_1, A(31), output3, X, 249, 1, Z)," & "195 (BC_1, DSACK1, input, X)," & "194 (BC_1, DSACK1, output3, X, 193, 1, Z)," & "193 (BC_1, *, control, 1)," & "192 (BC_1, DSACK0, input, X)," & "191 (BC_1, DSACK0, output3, X, 190, 1, Z)," & "190 (BC_1, *, control, 1)," & "189 (BC_1, *, control, 1)," & "188 (BC_1, SIZ(1), input, X)," & "187 (BC_1, SIZ(1), output3, X, 189, 1, Z)," & "186 (BC_1, SIZ(0), input, X)," & "185 (BC_1, SIZ(0), output3, X, 189, 1, Z)," & "184 (BC_1, SDA, input, X)," & "183 (BC_1, SDA, output2, 1, 183, 1, Weak1)," & -- open drain output "182 (BC_1, *, control, 1)," & "181 (BC_1, SCL, output3, X, 182, 1, Z)," & "180 (BC_1, ENUM, output2, 1, 180, 1, Weak1)," & -- open drain output "179 (BC_1, IMSEL, input, X)," & "178 (BC_1, HS_LED, output2, 1, 178, 1, Weak1)," & -- open drain output "177 (BC_1, HS_SWITCH, input, X)," & "176 (BC_1, PME, output2, 1, 176, 1, Weak1)," & -- open drain output "175 (BC_1, RESETI, input, X)," & "174 (BC_1, PCI_DIS, input, X)," & "173 (BC_1, PCI_ARB_EN, input, X)," & "172 (BC_1, RESETO, output2, 1, 172, 1, Weak1)," & -- open drain output "171 (BC_1, HS_HEALTHY, input, X)," & "170 (BC_1, BURST, input, X)," & "169 (BC_1, BURST, output3, X, 168, 1, Z)," & "168 (BC_1, *, control, 1)," & "167 (BC_1, TS, input, X)," & "166 (BC_1, TS, output3, X, 165, 1, Z)," & "165 (BC_1, *, control, 1)," & "164 (BC_1, BB, input, X)," & "163 (BC_1, BB, output3, X, 162, 1, Z)," & "162 (BC_1, *, control, 1)," & "161 (BC_1, BR, output3, X, 347, 1, Z)," & "160 (BC_1, HALT, input, X)," & "159 (BC_1, HALT, output3, X, 158, 1, Z)," & "158 (BC_1, *, control, 1)," & "157 (BC_1, RST, input, X)," & "156 (BC_1, GNT, input, X)," & "155 (BC_1, EXT_REQ(1), input, X)," & "154 (BC_1, EXT_REQ(1), output3, X, 134, 1, Z)," & "153 (BC_1, EXT_REQ(2), input, X)," & "152 (BC_1, EXT_REQ(2), output3, X, 134, 1, Z)," & "151 (BC_1, EXT_REQ(3), input, X)," & "150 (BC_1, EXT_REQ(3), output3, X, 134, 1, Z)," & "149 (BC_1, EXT_REQ(4), input, X)," & "148 (BC_1, EXT_REQ(4), output3, X, 134, 1, Z)," & "147 (BC_1, EXT_REQ(5), input, X)," & "146 (BC_1, EXT_REQ(5), output3, X, 134, 1, Z)," & "145 (BC_1, EXT_REQ(6), input, X)," & "144 (BC_1, EXT_REQ(6), output3, X, 134, 1, Z)," & "143 (BC_1, REQ, input, X)," & "142 (BC_1, REQ, output3, X, 134, 1, Z)," & "141 (BC_1, EXT_GNT(1), output3, X, 132, 1, Z)," & "140 (BC_1, EXT_GNT(2), output3, X, 132, 1, Z)," & "139 (BC_1, EXT_GNT(3), output3, X, 132, 1, Z)," & "138 (BC_1, EXT_GNT(4), output3, X, 132, 1, Z)," & "137 (BC_1, EXT_GNT(5), output3, X, 132, 1, Z)," & "136 (BC_1, EXT_GNT(6), output3, X, 132, 1, Z)," & "135 (BC_1, GNT, output3, X, 133, 1, Z)," & "134 (BC_1, *, control, 1)," & "133 (BC_1, *, control, 1)," & "132 (BC_1, *, control, 1)," & "131 (BC_1, *, control, 1)," & "130 (BC_1, *, control, 1)," & "129 (BC_1, AD(31), input, X)," & "128 (BC_1, AD(31), output3, X, 130, 1, Z)," & "127 (BC_1, AD(30), input, X)," & "126 (BC_1, AD(30), output3, X, 130, 1, Z)," & "125 (BC_1, AD(29), input, X)," & "124 (BC_1, AD(29), output3, X, 130, 1, Z)," & "123 (BC_1, AD(28), input, X)," & "122 (BC_1, AD(28), output3, X, 130, 1, Z)," & "121 (BC_1, AD(27), input, X)," & "120 (BC_1, AD(27), output3, X, 109, 1, Z)," & "119 (BC_1, AD(26), input, X)," & "118 (BC_1, AD(26), output3, X, 109, 1, Z)," & "117 (BC_1, AD(25), input, X)," & "116 (BC_1, AD(25), output3, X, 109, 1, Z)," & "115 (BC_1, AD(24), input, X)," & "114 (BC_1, AD(24), output3, X, 109, 1, Z)," & "113 (BC_1, *, control, 1)," & "112 (BC_1, CBE(3), input, X)," & "111 (BC_1, CBE(3), output3, X, 113, 1, Z)," & "110 (BC_1, *, control, 1)," & "109 (BC_1, *, control, 1)," & "108 (BC_1, AD(23), input, X)," & "107 (BC_1, AD(23), output3, X, 65, 1, Z)," & "106 (BC_1, AD(22), input, X)," & "105 (BC_1, AD(22), output3, X, 65, 1, Z)," & "104 (BC_1, AD(21), input, X)," & "103 (BC_1, AD(21), output3, X, 65, 1, Z)," & "102 (BC_1, AD(20), input, X)," & "101 (BC_1, AD(20), output3, X, 65, 1, Z)," & "100 (BC_1, AD(19), input, X)," & "99 (BC_1, AD(19), output3, X, 45, 1, Z)," & "98 (BC_1, AD(18), input, X)," & "97 (BC_1, AD(18), output3, X, 45, 1, Z)," & "96 (BC_1, AD(17), input, X)," & "95 (BC_1, AD(17), output3, X, 45, 1, Z)," & "94 (BC_1, AD(16), input, X)," & "93 (BC_1, AD(16), output3, X, 45, 1, Z)," & "92 (BC_1, CBE(2), input, X)," & "91 (BC_1, CBE(2), output3, X, 113, 1, Z)," & "90 (BC_1, FRAME, input, X)," & "89 (BC_1, FRAME, output3, X, 88, 1, Z)," & "88 (BC_1, *, control, 1)," & "87 (BC_1, IRDY, input, X)," & "86 (BC_1, IRDY, output3, X, 85, 1, Z)," & "85 (BC_1, *, control, 1)," & "84 (BC_1, TRDY, input, X)," & "83 (BC_1, TRDY, output3, X, 82, 1, Z)," & "82 (BC_1, *, control, 1)," & "81 (BC_1, DEVSEL, input, X)," & "80 (BC_1, DEVSEL, output3, X, 79, 1, Z)," & "79 (BC_1, *, control, 1)," & "78 (BC_4, PCLK, input, X)," & "77 (BC_1, STOP, input, X)," & "76 (BC_1, STOP, output3, X, 75, 1, Z)," & "75 (BC_1, *, control, 1)," & "74 (BC_1, PERR, input, X)," & "73 (BC_1, PERR, output3, X, 72, 1, Z)," & "72 (BC_1, *, control, 1)," & "71 (BC_1, PAR, input, X)," & "70 (BC_1, PAR, output3, X, 69, 1, Z)," & "69 (BC_1, *, control, 1)," & "68 (BC_1, CBE(1), input, X)," & "67 (BC_1, CBE(1), output3, X, 113, 1, Z)," & "66 (BC_1, *, control, 1)," & "65 (BC_1, *, control, 1)," & "64 (BC_1, AD(15), input, X)," & "63 (BC_1, AD(15), output3, X, 131, 1, Z)," & "62 (BC_1, AD(14), input, X)," & "61 (BC_1, AD(14), output3, X, 131, 1, Z)," & "60 (BC_1, AD(13), input, X)," & "59 (BC_1, AD(13), output3, X, 131, 1, Z)," & "58 (BC_1, AD(12), input, X)," & "57 (BC_1, AD(12), output3, X, 131, 1, Z)," & "56 (BC_1, AD(11), input, X)," & "55 (BC_1, AD(11), output3, X, 110, 1, Z)," & "54 (BC_1, AD(10), input, X)," & "53 (BC_1, AD(10), output3, X, 110, 1, Z)," & "52 (BC_1, AD(9), input, X)," & "51 (BC_1, AD(9), output3, X, 110, 1, Z)," & "50 (BC_1, AD(8), input, X)," & "49 (BC_1, AD(8), output3, X, 110, 1, Z)," & "48 (BC_1, CBE(0), input, X)," & "47 (BC_1, CBE(0), output3, X, 113, 1, Z)," & "46 (BC_1, *, control, 1)," & "45 (BC_1, *, control, 1)," & "44 (BC_1, IDSEL, input, X)," & "43 (BC_1, AD(7), input, X)," & "42 (BC_1, AD(7), output3, X, 66, 1, Z)," & "41 (BC_1, AD(6), input, X)," & "40 (BC_1, AD(6), output3, X, 66, 1, Z)," & "39 (BC_1, AD(5), input, X)," & "38 (BC_1, AD(5), output3, X, 66, 1, Z)," & "37 (BC_1, AD(4), input, X)," & "36 (BC_1, AD(4), output3, X, 66, 1, Z)," & "35 (BC_1, AD(3), input, X)," & "34 (BC_1, AD(3), output3, X, 46, 1, Z)," & "33 (BC_1, AD(2), input, X)," & "32 (BC_1, AD(2), output3, X, 46, 1, Z)," & "31 (BC_1, AD(1), input, X)," & "30 (BC_1, AD(1), output3, X, 46, 1, Z)," & "29 (BC_1, AD(0), input, X)," & "28 (BC_1, AD(0), output3, X, 46, 1, Z)," & "27 (BC_1, INT, input, X)," & "26 (BC_1, INT, output2, 1, 26, 1, Weak1)," & -- open drain output "25 (BC_1, SERR, output2, 1, 25, 1, Weak1)," & -- open drain output "24 (BC_1, SERR, input, X)," & "23 (BC_1, CSREG, input, X)," & "22 (BC_1, CSPCI, input, X)," & "21 (BC_1, *, control, 1)," & "20 (BC_1, TC(0), input, X)," & "19 (BC_1, TC(0), output3, X, 21, 1, Z)," & "18 (BC_1, TC(1), input, X)," & "17 (BC_1, TC(1), output3, X, 21, 1, Z)," & "16 (BC_1, TC(2), input, X)," & "15 (BC_1, TC(2), output3, X, 21, 1, Z)," & "14 (BC_1, TC(3), input, X)," & "13 (BC_1, TC(3), output3, X, 21, 1, Z)," & "12 (BC_1, BERR, input, X)," & "11 (BC_1, BERR, output3, X, 10, 1, Z)," & "10 (BC_1, *, control, 1)," & "9 (BC_1, AS, input, X)," & "8 (BC_1, AS, output3, X, 7, 1, Z)," & "7 (BC_1, *, control, 1)," & "6 (BC_1, BDIP, input, X)," & "5 (BC_1, BDIP, output3, X, 4, 1, Z)," & "4 (BC_1, *, control, 1)," & "3 (BC_1, BG, input, X)," & "2 (BC_1, BM_EN, input, X)," & "1 (BC_1, BM_EN, output3, X, 0, 1, Z)," & "0 (BC_1, *, control, 1)"; end CA91L862A;