------------------------------------------------------------------------------- -- BSDL for ISSI 2Mx36 QUAD-B4 -- IBM Microelectronics -- Copyright(c) 2006 -- Created on: Aug. 06. 2009 -- Rev.0 (Aug/06/09) : Initial Release. -- v1.0 Preliminary release -- Model : ISSI QUAD Burst 2 -- Parameter : Selection between x36 -- x36 PHYSICAL_PIN_MAP = IS61QDB42M36 -- PHYS_BOUNDARY_SCAN = IS61QDB42M36_BD -- ------------------------------------------------------------------------------- entity ISSI_QUAD is generic (PHYSICAL_PIN_MAP : string := "IS61QDB42M36"); port ( TDO : out bit; TMS : in bit; TDI : in bit; TCK : in bit; ZQ : in bit; VSS : linkage bit_vector(0 to 24); VDDQ : linkage bit_vector(0 to 15); VDD : linkage bit_vector(0 to 9); VREF : linkage bit_vector(0 to 1); BWN : in bit_vector(0 to 3); RN : in bit; WN : in bit; Q : buffer bit_vector(0 to 35); D : in bit_vector(0 to 35); SA : in bit_vector(1 to 19); DOFFN : in bit; CQ : buffer bit; CQN : buffer bit; C : in bit; CN : in bit; K : in bit; KN : in bit; NC : linkage bit_vector (1 to 3)); use STD_1149_1_2001.all ; attribute COMPONENT_CONFORMANCE of ISSI_QUAD: entity is "STD_1149_1_2001"; attribute PIN_MAP of ISSI_QUAD : entity is PHYSICAL_PIN_MAP; constant IS61QDB42M36 : PIN_MAP_STRING := "TDO:R1, " & "TMS:R10, " & "TDI:R11, " & "TCK:R2, " & "ZQ:H11, " & "VSS:(C4, C8, D4, D5, D6, D7, D8, E5, E6, E7, " & " F6, G6, H6, J6, K6, L5, L6, L7, M4, M5, " & " M6, M7, M8, N4, N8), " & "VDDQ:(E4, E8, F4, F8, G4, G8, H3, H4, H8, H9, " & " J4, J8, K4, K8, L4, L8), " & "VDD: (F5, F7, G5, G7, H5, H7, J5, J7, K5, K7), " & "VREF:(H2, H10), " & "BWN: (B7, A7, A5, B5), " & "RN:A8, " & "WN:A4, " & "Q:( P11 , M10 , L11 , K11 , J10 , F11 , E11 , C10 , B11 , " & " P9 , N9 , L10 , K9 , G9 , F10 , E9 , D9 , B10 , " & " B2 , D3 , E3 , F2 , G3 , K3 , L2 , N3 , P3 , " & " B1 , C2 , E1 , F1 , J2 , K1 , L1 , M2 , P1 ) , " & "D:( P10 , N11 , M11 , K10 , J11 , G11 , E10 , D11 , C11 , " & " N10 , M9 , L9 , J9 , G10 , F9 , D10 , C9 , B9 , " & " B3 , C3 , D2 , F3 , G2 , J3 , L3 , M3 , N2 , " & " C1 , D1 , E2 , G1 , J1 , K2 , M1 , N1 , P2 ) , " & "SA:(C7 , B8 , N6 , R9 , R8 , R7 , P7 , P8 , N7 , " & " C5 , B4 , R3 , R4 , P4 , R5 , P5 , N5 , A9 , A3 ), " & "DOFFN:H1, " & "CQ:A11, " & "CQN:A1, " & "C:P6, " & "CN:R6, " & "K:B6, " & "KN:A6, "& "NC : (A2, A10, C6) " ; --Scan Port Identification attribute TAP_SCAN_IN of TDI: signal is true; attribute TAP_SCAN_MODE of TMS: signal is true; attribute TAP_SCAN_OUT of TDO: signal is true; attribute TAP_SCAN_CLOCK of TCK: signal is (20.0e6, BOTH); -- TAP Description attribute INSTRUCTION_LENGTH of ISSI_QUAD: entity is 3; attribute INSTRUCTION_OPCODE of ISSI_QUAD: entity is "EXTEST (000)," & "IDCODE (001)," & "SAMPLEZ (010)," & "PRIVATE1 (011)," & "SAMPLE (100)," & "PRELOAD (100)," & "PRIVATE2 (101)," & "PRIVATE3 (110)," & "BYPASS (111)"; attribute INSTRUCTION_CAPTURE of ISSI_QUAD: entity is "001"; attribute INSTRUCTION_PRIVATE of ISSI_QUAD: entity is "PRIVATE1 , PRIVATE2 , PRIVATE3"; attribute IDCODE_REGISTER of ISSI_QUAD: entity is "000" & -- Revision Number "00" & -- Reserved "011" & -- def = 011 for 72Mb "0" & -- Reserved "11" & -- wx = 11 for x36, 10 for x18 "0" & -- Reserved "X" & -- t = 1 for DLL, 0 for non-DLL, X controlled by DOFFN "0" & -- Reserved "1" & -- q = 1 for QDB2, 0 for DDRII "0" & -- Reserved "1" & -- b = 1 for burst of 4, 0 for burst of 2 "0" & -- Reserved "1" & -- s = 1 for separate I/0, 0 for common I/O "0" & -- Reserved Part Configuration , "00010100100" & -- ISSI JEDEC Code "1"; -- Required by IEEE Std 1149.1-1990 attribute REGISTER_ACCESS of ISSI_QUAD: entity is "BOUNDARY (SAMPLEZ) "; attribute BOUNDARY_LENGTH of ISSI_QUAD: entity is 109; attribute BOUNDARY_REGISTER of ISSI_QUAD: entity is --num cell port function safe [ccell disval rslt] "0 (BC_4, CN, INPUT, X)," & "1 (BC_4, C, INPUT, X)," & "2 (BC_4, SA(3), INPUT, X)," & "3 (BC_4, SA(7), INPUT, X)," & "4 (BC_4, SA(9), INPUT, X)," & "5 (BC_4, SA(6), INPUT, X)," & "6 (BC_4, SA(5), INPUT, X)," & "7 (BC_4, SA(8), INPUT, X)," & "8 (BC_4, SA(4), INPUT, X)," & "9 (BC_9, Q(0), output2, X)," & "10 (BC_4, D(0), INPUT, X)," & "11 (BC_4, D(9), INPUT, X)," & "12 (BC_9, Q(9), output2, X)," & "13 (BC_9, Q(1), output2, X)," & "14 (BC_4, D(1), INPUT, X)," & "15 (BC_4, D(10), INPUT, X)," & "16 (BC_9, Q(10), output2, X)," & "17 (BC_9, Q(2), output2, X)," & "18 (BC_4, D(2), INPUT, X)," & "19 (BC_4, D(11), INPUT, X)," & "20 (BC_9, Q(11), output2, X)," & "21 (BC_9, Q(3), output2, X)," & "22 (BC_4, D(3), INPUT, X)," & "23 (BC_4, D(12), INPUT, X)," & "24 (BC_9, Q(12), output2, X)," & "25 (BC_9, Q(4), output2, X)," & "26 (BC_4, D(4), INPUT, X)," & "27 (BC_4, ZQ, INPUT, X)," & "28 (BC_4, D(13), INPUT, X)," & "29 (BC_9, Q(13), output2, X)," & "30 (BC_9, Q(5), output2, X)," & "31 (BC_4, D(5), INPUT, X)," & "32 (BC_4, D(14), INPUT, X)," & "33 (BC_9, Q(14), output2, X)," & "34 (BC_9, Q(6), output2, X)," & "35 (BC_4, D(6), INPUT, X)," & "36 (BC_4, D(15), INPUT, X)," & "37 (BC_9, Q(15), output2, X)," & "38 (BC_9, Q(7), output2, X)," & "39 (BC_4, D(7), INPUT, X)," & "40 (BC_4, D(16), INPUT, X)," & "41 (BC_9, Q(16), output2, X)," & "42 (BC_9, Q(8), output2, X)," & "43 (BC_4, D(8), INPUT, X)," & "44 (BC_4, D(17), INPUT, X)," & "45 (BC_9, Q(17), output2, X)," & "46 (BC_9, CQ, output2, X)," & "47 (BC_1, *, INTERNAL, X)," & "48 (BC_4, SA(18), INPUT, X)," & "49 (BC_4, SA(2), INPUT, X)," & "50 (BC_4, SA(1), INPUT, X)," & "51 (BC_4, *, INTERNAL, X)," & -- C6 becomes NC for B4, SA(1) for B2 "52 (BC_4, RN, INPUT, X)," & "53 (BC_4, BWN(1), INPUT, X)," & "54 (BC_4, BWN(0), INPUT, X)," & "55 (BC_4, K, INPUT, X)," & "56 (BC_4, KN, INPUT, X)," & "57 (BC_4, BWN(3), INPUT, X)," & "58 (BC_4, BWN(2), INPUT, X)," & "59 (BC_4, WN, INPUT, X)," & "60 (BC_4, SA(10), INPUT, X)," & "61 (BC_4, SA(11), INPUT, X)," & "62 (BC_4, SA(19), INPUT, X)," & -- 72M "63 (BC_1, *, INTERNAL, X)," & "64 (BC_9, CQN, output2, X)," & "65 (BC_9, Q(18), output2, X)," & "66 (BC_4, D(18), INPUT, X)," & "67 (BC_4, D(27), INPUT, X)," & "68 (BC_9, Q(27), output2, X)," & "69 (BC_9, Q(19), output2, X)," & "70 (BC_4, D(19), INPUT, X)," & "71 (BC_4, D(28), INPUT, X)," & "72 (BC_9, Q(28), output2, X)," & "73 (BC_9, Q(20), output2, X)," & "74 (BC_4, D(20), INPUT, X)," & "75 (BC_4, D(29), INPUT, X)," & "76 (BC_9, Q(29), output2, X)," & "77 (BC_9, Q(21), output2, X)," & "78 (BC_4, D(21), INPUT, X)," & "79 (BC_4, D(30), INPUT, X)," & "80 (BC_9, Q(30), output2, X)," & "81 (BC_9, Q(22), output2, X)," & "82 (BC_4, D(22), INPUT, X)," & "83 (BC_4, DOFFN, INPUT, X)," & "84 (BC_4, D(31), INPUT, X)," & "85 (BC_9, Q(31), output2, X)," & "86 (BC_9, Q(23), output2, X)," & "87 (BC_4, D(23), INPUT, X)," & "88 (BC_4, D(32), INPUT, X)," & "89 (BC_9, Q(32), output2, X)," & "90 (BC_9, Q(24), output2, X)," & "91 (BC_4, D(24), INPUT, X)," & "92 (BC_4, D(33), INPUT, X)," & "93 (BC_9, Q(33), output2, X)," & "94 (BC_9, Q(25), output2, X)," & "95 (BC_4, D(25), INPUT, X)," & "96 (BC_4, D(34), INPUT, X)," & "97 (BC_9, Q(34), output2, X)," & "98 (BC_9, Q(26), output2, X)," & "99 (BC_4, D(26), INPUT, X)," & "100 (BC_4, D(35), INPUT, X)," & "101 (BC_9, Q(35), output2, X)," & "102 (BC_4, SA(12), INPUT, X)," & "103 (BC_4, SA(13), INPUT, X)," & "104 (BC_4, SA(14), INPUT, X)," & "105 (BC_4, SA(16), INPUT, X)," & "106 (BC_4, SA(17), INPUT, X)," & "107 (BC_4, SA(15), INPUT, X)," & "108 (BC_1, *, INTERNAL, X)" ; attribute DESIGN_WARNING of ISSI_QUAD: entity is "The SRAM provides a limited set of JTAG functions to test the interconnection " & "between SRAM I/Os and printed circuit board traces or other components. There " & "is no multiplexer in the path from I/O pins to the RAM core."; end ISSI_QUAD ;