--//***************************************************************************** --// --// lm3s101_rc2_qfn_v1p0.bsdl - Boundary Scan Description Language (BSDL) file --// for the Texas Instruments LM3S101 Stellaris microcontroller. --// --// Version 1.0 - 02/15/2010 - Initial Release of BSDL entity --// - LM3S101, Revision C2, 48-pin QFN --// --// --// Copyright (c) 2010 Texas Instruments, Inc. All rights reserved. --// --// Software License Agreement --// --// Texas Instruments, Inc. (TI) is supplying this software for use solely and --// exclusively on TI's Stellaris Family of microcontroller products. --// --// The software is owned by TI and/or its suppliers, and is protected under --// applicable copyright laws. All rights are reserved. Any use in violation --// of the foregoing restrictions may subject the user to criminal sanctions --// under applicable laws, as well as to civil liability for the breach of the --// terms and conditions of this license. --// --// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED --// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF --// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. --// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR --// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. --// --//***************************************************************************** entity LM3S101 is generic (PHYSICAL_PIN_MAP : string := "QFN_48"); port ( GND: linkage bit_vector(0 to 2); LDO: linkage bit; NC: linkage bit_vector(0 to 19); OSC0: linkage bit; OSC1: linkage bit; PA0_U0Rx: inout bit; PA1_U0Tx: inout bit; PA2_SSIClk: inout bit; PA3_SSIFss: inout bit; PA4_SSIRx: inout bit; PA5_SSITx: inout bit; PB0_CCP0: inout bit; PB1_32KHz: inout bit; PB2: inout bit; PB3: inout bit; PB4: inout bit; PB5_C0o: inout bit; PB6: inout bit; RST: in bit; TCK: in bit; TDI: in bit; TDO: out bit; TMS: in bit; TRST: in bit; VDD: linkage bit_vector(0 to 2) ); use STD_1149_1_1994.all; -- Get Std 1149.1-1994 attributes and definitions attribute COMPONENT_CONFORMANCE of LM3S101 : entity is "STD_1149_1_1993"; attribute PIN_MAP of LM3S101 : entity is PHYSICAL_PIN_MAP; constant QFN_48: PIN_MAP_STRING := "RST: 5, " & "LDO: 6, " & "OSC0: 9, " & "OSC1: 10, " & "PA0_U0Rx: 17, " & "PA1_U0Tx: 18, " & "PA2_SSIClk: 19, " & "PA3_SSIFss: 20, " & "PA4_SSIRx: 21, " & "PA5_SSITx: 22, " & "PB0_CCP0: 29, " & "PB1_32KHz: 30, " & "PB2: 33, " & "PB3: 34, " & "TDO: 37, " & "TDI: 38, " & "TMS: 39, " & "TCK: 40, " & "TRST: 41, " & "PB6: 42, " & "PB5_C0o: 43, " & "PB4: 44, " & "GND: ( 8, 24, 31 ), " & "NC: ( 1, 2, 3, 4, 11, 12, 13, 14, 15, 16, 25, 26, 27, 28, 35, 36, 45, 46, 47, 48 ), " & "VDD: ( 7, 23, 32 ) " ; attribute TAP_SCAN_RESET of TRST : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute INSTRUCTION_LENGTH of LM3S101 : entity is 4; attribute INSTRUCTION_OPCODE of LM3S101 : entity is "EXTEST (0000)," & "INTEST (0001)," & "SAMPLE (0010)," & "BYPASS (0011)," & "BYPASS (0100)," & "BYPASS (0101)," & "BYPASS (0110)," & "BYPASS (0111)," & "ABORT (1000)," & "BYPASS (1001)," & "DPACC (1010)," & "APACC (1011)," & "BYPASS (1100)," & "BYPASS (1101)," & "IDCODE (1110)," & "BYPASS (1111)"; attribute INSTRUCTION_CAPTURE of LM3S101 : entity is "0001"; attribute IDCODE_REGISTER of LM3S101 : entity is "0010" & -- Version (Third Revision) "1011101000000000" & -- Part number (ARM Cortex M3) "01000111011" & -- Manufacturer Identity (ARM) "1"; -- Mandatory LSB -- IDCODE = 2BA00477 attribute INSTRUCTION_PRIVATE of LM3S101 : entity is "ABORT, DPACC, APACC"; -- ARM Debug Access Port Instructions attribute BOUNDARY_LENGTH of LM3S101 : entity is 40; attribute BOUNDARY_REGISTER of LM3S101 : entity is -- num cell port function safe [ ccell disval rslt ] -- --- ---- -------------- -------- ---- ------ ------ ------ " 0 (BC_1, *, CONTROL, 1 ), " & " 1 (BC_1, PB3, OUTPUT3, X , 0, 1, Z ), " & " 2 (BC_1, PB3, INPUT, X ), " & " 3 (BC_1, *, CONTROL, 1 ), " & " 4 (BC_1, PB2, OUTPUT3, X , 3, 1, Z ), " & " 5 (BC_1, PB2, INPUT, X ), " & " 6 (BC_1, *, CONTROL, 1 ), " & " 7 (BC_1, PB1_32KHz, OUTPUT3, X , 6, 1, Z ), " & " 8 (BC_1, PB1_32KHz, INPUT, X ), " & " 9 (BC_1, *, CONTROL, 1 ), " & " 10 (BC_1, PB0_CCP0, OUTPUT3, X , 9, 1, Z ), " & " 11 (BC_1, PB0_CCP0, INPUT, X ), " & " 12 (BC_1, *, CONTROL, 1 ), " & " 13 (BC_1, PA5_SSITx, OUTPUT3, X , 12, 1, Z ), " & " 14 (BC_1, PA5_SSITx, INPUT, X ), " & " 15 (BC_1, *, CONTROL, 1 ), " & " 16 (BC_1, PA4_SSIRx, OUTPUT3, X , 15, 1, Z ), " & " 17 (BC_1, PA4_SSIRx, INPUT, X ), " & " 18 (BC_1, *, CONTROL, 1 ), " & " 19 (BC_1, PA3_SSIFss, OUTPUT3, X , 18, 1, Z ), " & " 20 (BC_1, PA3_SSIFss, INPUT, X ), " & " 21 (BC_1, *, CONTROL, 1 ), " & " 22 (BC_1, PA2_SSIClk, OUTPUT3, X , 21, 1, Z ), " & " 23 (BC_1, PA2_SSIClk, INPUT, X ), " & " 24 (BC_1, *, CONTROL, 1 ), " & " 25 (BC_1, PA1_U0Tx, OUTPUT3, X , 24, 1, Z ), " & " 26 (BC_1, PA1_U0Tx, INPUT, X ), " & " 27 (BC_1, *, CONTROL, 1 ), " & " 28 (BC_1, PA0_U0Rx, OUTPUT3, X , 27, 1, Z ), " & " 29 (BC_1, PA0_U0Rx, INPUT, X ), " & " 30 (BC_4, RST, CLOCK, X ), " & " 31 (BC_1, *, CONTROL, 1 ), " & " 32 (BC_1, PB4, OUTPUT3, X , 31, 1, Z ), " & " 33 (BC_1, PB4, INPUT, X ), " & " 34 (BC_1, *, CONTROL, 1 ), " & " 35 (BC_1, PB5_C0o, OUTPUT3, X , 34, 1, Z ), " & " 36 (BC_1, PB5_C0o, INPUT, X ), " & " 37 (BC_1, *, CONTROL, 1 ), " & " 38 (BC_1, PB6, OUTPUT3, X , 37, 1, Z ), " & " 39 (BC_1, PB6, INPUT, X ) " ; end LM3S101;