-- $ XILINX$RCSfile: xc2c32a_vq44.bsd,v $ -- $ XILINX$Revision: 1.7 $ -- -- BSDL file for device xc2c32a_vq44 -- Xilinx, Inc. $State: PRELIMINARY $ $Date: 2006/10/17 16:42:48 $ -- Generated by ABSDG 0.6 on loco -- For technical support, http://support.xilinx.com -> enter text 'bsdl' -- in the text search box at the left of the page. If none of -- these records resolve your problem you should open a web support case -- or contact our technical support at: -- This BSDL file reflects the pre-configuration JTAG behavior. -- ================================================= -- North American Support -- (Mon,Tues,Wed,Fri 6:30am-5pm -- Thr 6:30am - 4:00pm Pacific Standard Time) -- Hotline: 1-800-255-7778 -- or (408) 879-5199 -- Fax: (408) 879-4442 -- Email: hotline\@xilinx.com -- United Kingdom Support -- (Mon-Fri 08:00 to 17:30 GMT) -- Hotline: +44 870 7350 610 -- Fax: +44 870 7350 620 -- Email : eurosupport\@xilinx.com -- -- France Support -- (Mon-Fri 08:00 to 17:30 GMT) -- Hotline: +33 1 3463 0100 -- Fax: +44 870 7350 620 -- Email : eurosupport\@xilinx.com -- -- Germany Support -- (Mon-Fri 08:00 to 17:30 GMT) -- Hotline: +49 180 3 60 60 60 -- Fax: +44 870 7350 620 -- Email : eurosupport\@xilinx.com -- Sweden Support -- (Mon-Fri 08:00 to 17:30 GMT) -- Hotline: +46 8 33 14 00 -- Fax: +44 870 7350 620 -- Email : eurosupport\@xilinx.com -- -- Japan Support -- (Mon,Tues,Thu,Fri 9:00am -5:00pm () -- Wed 9:00am -4:00pm) -- Hotline: (81)3-3297-9163 -- Fax:: (81)3-3297-0067 -- Email: jhotline\@xilinx.com -- ================================================= entity xc2c32a_vq44 is generic (PHYSICAL_PIN_MAP : string := "VQ44"); port ( TCK : in bit; TDI : in bit; TDO : out bit; TMS : in bit; IO_0 : inout bit; IO_1 : inout bit; IO_2 : inout bit; IO_3 : inout bit; IO_4 : inout bit; IO_5 : inout bit; IO_6 : inout bit; IO_7 : inout bit; IO_8 : inout bit; IO_9 : inout bit; IO_10 : inout bit; IO_11 : inout bit; IO_12 : inout bit; IO_13 : inout bit; IO_14 : inout bit; IO_15 : inout bit; IO_16 : inout bit; IO_17 : inout bit; IO_18 : inout bit; IO_19 : inout bit; IO_20 : inout bit; IO_21 : inout bit; IO_22 : inout bit; IO_23 : inout bit; IO_24 : inout bit; IO_25 : inout bit; IO_26 : inout bit; IO_27 : inout bit; IO_28 : inout bit; IO_29 : inout bit; IO_30 : inout bit; IO_31 : inout bit; IN_32 : in bit; GND : linkage bit_vector(0 to 2); VDD : linkage bit_vector (0 to 2)); use std_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of xc2c32a_vq44 : entity is "std_1149_1_1993"; attribute PIN_MAP of xc2c32a_vq44 : entity is PHYSICAL_PIN_MAP; constant VQ44 : PIN_MAP_STRING := "TCK : 11, TDI : 9, TDO : 24, TMS : 10, " & "IO_0 : 38, IO_1 : 37, IO_2 : 36, IO_3 : 34, " & "IO_4 : 33, IO_5 : 32, IO_6 : 31, IO_7 : 30, " & "IO_8 : 29, IO_9 : 28, IO_10 : 27, IO_11 : 23, " & "IO_12 : 22, IO_13 : 21, IO_14 : 20, IO_15 : 19, " & "IO_16 : 39, IO_17 : 40, IO_18 : 41, IO_19 : 42, " & "IO_20 : 43, IO_21 : 44, IO_22 : 1, IO_23 : 2, " & "IO_24 : 3, IO_25 : 5, IO_26 : 6, IO_27 : 8, " & "IO_28 : 12, IO_29 : 13, IO_30 : 14, IO_31 : 16, " & "IN_32 : 18, GND : (4, 17, 25), VDD : (7, 15, 26)"; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (33.0e6, both); attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute INSTRUCTION_LENGTH of xc2c32a_vq44 : entity is 8; attribute INSTRUCTION_OPCODE of xc2c32a_vq44 : entity is "INTEST (00000010)," & "BYPASS (11111111)," & "SAMPLE (00000011)," & "EXTEST (00000000)," & "IDCODE (00000001)," & "USERCODE (11111101)," & "HIGHZ (11111100)," & "ISC_ENABLE_CLAMP (11101001)," & "ISC_ENABLEOTF (11100100)," & "ISC_ENABLE (11101000)," & "ISC_SRAM_READ (11100111)," & "ISC_SRAM_WRITE (11100110)," & "ISC_ERASE (11101101)," & "ISC_PROGRAM (11101010)," & "ISC_READ (11101110)," & "ISC_INIT (11110000)," & "ISC_DISABLE (11000000)," & "TEST_ENABLE (00010001)," & "BULKPROG (00010010)," & "ERASE_ALL (00010100)," & "MVERIFY (00010011)," & "TEST_DISABLE (00010101)," & -- "STCTEST (00010110)," & "ISC_NOOP (11100000)"; attribute INSTRUCTION_CAPTURE of xc2c32a_vq44 : entity is "XXXXXX01" ; attribute IDCODE_REGISTER of xc2c32a_vq44 : entity is "XXXX0110111000011100000010010011"; attribute USERCODE_REGISTER of xc2c32a_vq44 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; attribute REGISTER_ACCESS of xc2c32a_vq44 : entity is "BYPASS (BYPASS)," & "BYPASS (HIGHZ)," & "BOUNDARY (SAMPLE)," & "BOUNDARY (EXTEST)," & "BOUNDARY (INTEST)," & "DATAREG[266] (ISC_ENABLEOTF)," & "DATAREG[266] (ISC_ENABLE)," & "DATAREG[266] (ISC_SRAM_READ)," & "DATAREG[266] (ISC_SRAM_WRITE)," & "DATAREG[266] (ISC_ERASE)," & "DATAREG[266] (ISC_PROGRAM)," & "DATAREG[266] (ISC_READ)," & "DATAREG[266] (ISC_INIT)," & "DATAREG[266] (ISC_DISABLE)," & "DATAREG[266] (TEST_ENABLE)," & "DATAREG[266] (BULKPROG)," & "DATAREG[266] (ERASE_ALL)," & "DATAREG[266] (MVERIFY)," & "DATAREG[266] (TEST_DISABLE)," & -- "STC[] (STCTEST)," & "ISC_DEFAULT[1] (ISC_NOOP)," & "DEVICE_ID (IDCODE, USERCODE)," & "ISC_DEFAULT[1] (ISC_ENABLE_CLAMP)"; attribute BOUNDARY_LENGTH of xc2c32a_vq44 : entity is 97; attribute BOUNDARY_REGISTER of xc2c32a_vq44 : entity is " 96 (BC_1, IO_0, INPUT, X),"& " 95 (BC_1, IO_0, OUTPUT3, X, 94, 0,Z),"& " 94 (BC_1, *, CONTROL, 0),"& " 93 (BC_1, IO_1, INPUT, X),"& " 92 (BC_1, IO_1, OUTPUT3, X, 91, 0,Z),"& " 91 (BC_1, *, CONTROL, 0),"& " 90 (BC_1, IO_2, INPUT, X),"& " 89 (BC_1, IO_2, OUTPUT3, X, 88, 0,Z),"& " 88 (BC_1, *, CONTROL, 0),"& " 87 (BC_1, IO_3, INPUT, X),"& " 86 (BC_1, IO_3, OUTPUT3, X, 85, 0,Z),"& " 85 (BC_1, *, CONTROL, 0),"& " 84 (BC_1, IO_4, INPUT, X),"& " 83 (BC_1, IO_4, OUTPUT3, X, 82, 0,Z),"& " 82 (BC_1, *, CONTROL, 0),"& " 81 (BC_1, IO_5, INPUT, X),"& " 80 (BC_1, IO_5, OUTPUT3, X, 79, 0,Z),"& " 79 (BC_1, *, CONTROL, 0),"& " 78 (BC_1, IO_6, INPUT, X),"& " 77 (BC_1, IO_6, OUTPUT3, X, 76, 0,Z),"& " 76 (BC_1, *, CONTROL, 0),"& " 75 (BC_1, IO_7, INPUT, X),"& " 74 (BC_1, IO_7, OUTPUT3, X, 73, 0,Z),"& " 73 (BC_1, *, CONTROL, 0),"& " 72 (BC_1, IO_8, INPUT, X),"& " 71 (BC_1, IO_8, OUTPUT3, X, 70, 0,Z),"& " 70 (BC_1, *, CONTROL, 0),"& " 69 (BC_1, IO_9, INPUT, X),"& " 68 (BC_1, IO_9, OUTPUT3, X, 67, 0,Z),"& " 67 (BC_1, *, CONTROL, 0),"& " 66 (BC_1, IO_10, INPUT, X),"& " 65 (BC_1, IO_10, OUTPUT3, X, 64, 0,Z),"& " 64 (BC_1, *, CONTROL, 0),"& " 63 (BC_1, IO_11, INPUT, X),"& " 62 (BC_1, IO_11, OUTPUT3, X, 61, 0,Z),"& " 61 (BC_1, *, CONTROL, 0),"& " 60 (BC_1, IO_12, INPUT, X),"& " 59 (BC_1, IO_12, OUTPUT3, X, 58, 0,Z),"& " 58 (BC_1, *, CONTROL, 0),"& " 57 (BC_1, IO_13, INPUT, X),"& " 56 (BC_1, IO_13, OUTPUT3, X, 55, 0,Z),"& " 55 (BC_1, *, CONTROL, 0),"& " 54 (BC_1, IO_14, INPUT, X),"& " 53 (BC_1, IO_14, OUTPUT3, X, 52, 0,Z),"& " 52 (BC_1, *, CONTROL, 0),"& " 51 (BC_1, IO_15, INPUT, X),"& " 50 (BC_1, IO_15, OUTPUT3, X, 49, 0,Z),"& " 49 (BC_1, *, CONTROL, 0),"& " 48 (BC_1, IO_16, INPUT, X),"& " 47 (BC_1, IO_16, OUTPUT3, X, 46, 0,Z),"& " 46 (BC_1, *, CONTROL, 0),"& " 45 (BC_1, IO_17, INPUT, X),"& " 44 (BC_1, IO_17, OUTPUT3, X, 43, 0,Z),"& " 43 (BC_1, *, CONTROL, 0),"& " 42 (BC_1, IO_18, INPUT, X),"& " 41 (BC_1, IO_18, OUTPUT3, X, 40, 0,Z),"& " 40 (BC_1, *, CONTROL, 0),"& " 39 (BC_1, IO_19, INPUT, X),"& " 38 (BC_1, IO_19, OUTPUT3, X, 37, 0,Z),"& " 37 (BC_1, *, CONTROL, 0),"& " 36 (BC_1, IO_20, INPUT, X),"& " 35 (BC_1, IO_20, OUTPUT3, X, 34, 0,Z),"& " 34 (BC_1, *, CONTROL, 0),"& " 33 (BC_1, IO_21, INPUT, X),"& " 32 (BC_1, IO_21, OUTPUT3, X, 31, 0,Z),"& " 31 (BC_1, *, CONTROL, 0),"& " 30 (BC_1, IO_22, INPUT, X),"& " 29 (BC_1, IO_22, OUTPUT3, X, 28, 0,Z),"& " 28 (BC_1, *, CONTROL, 0),"& " 27 (BC_1, IO_23, INPUT, X),"& " 26 (BC_1, IO_23, OUTPUT3, X, 25, 0,Z),"& " 25 (BC_1, *, CONTROL, 0),"& " 24 (BC_1, IO_24, INPUT, X),"& " 23 (BC_1, IO_24, OUTPUT3, X, 22, 0,Z),"& " 22 (BC_1, *, CONTROL, 0),"& " 21 (BC_1, IO_25, INPUT, X),"& " 20 (BC_1, IO_25, OUTPUT3, X, 19, 0,Z),"& " 19 (BC_1, *, CONTROL, 0),"& " 18 (BC_1, IO_26, INPUT, X),"& " 17 (BC_1, IO_26, OUTPUT3, X, 16, 0,Z),"& " 16 (BC_1, *, CONTROL, 0),"& " 15 (BC_1, IO_27, INPUT, X),"& " 14 (BC_1, IO_27, OUTPUT3, X, 13, 0,Z),"& " 13 (BC_1, *, CONTROL, 0),"& " 12 (BC_1, IO_28, INPUT, X),"& " 11 (BC_1, IO_28, OUTPUT3, X, 10, 0,Z),"& " 10 (BC_1, *, CONTROL, 0),"& " 9 (BC_1, IO_29, INPUT, X),"& " 8 (BC_1, IO_29, OUTPUT3, X, 7, 0,Z),"& " 7 (BC_1, *, CONTROL, 0),"& " 6 (BC_1, IO_30, INPUT, X),"& " 5 (BC_1, IO_30, OUTPUT3, X, 4, 0,Z),"& " 4 (BC_1, *, CONTROL, 0),"& " 3 (BC_1, IO_31, INPUT, X),"& " 2 (BC_1, IO_31, OUTPUT3, X, 1, 0,Z),"& " 1 (BC_1, *, CONTROL, 0),"& " 0 (BC_1, IN_32, INPUT, X)" ; end xc2c32a_vq44 ;