------------------------------------------------------------------------------- -- BSDL for ISSI 2MX18 QUAD B2 -- Copyright(c) 2008 ISSI -- Created on: DEC. 01. 2009 -- Rev.0 (DEC/01/09) : Initial Release -- Model : ISSI QDR 2MX18 Burst 2 -- Parameter : Selection between x18 -- x18 PHYSICAL_PIN_MAP = IS61QDRB22M18 -- PHYS_BOUNDARY_SCAN = IS61QDRB22M18_BD -- ------------------------------------------------------------------------------- entity ISSI_QDR is generic (PHYSICAL_PIN_MAP : string := "IS61QDRB22M18"); port ( TDO : out bit; TMS : in bit; TDI : in bit; TCK : in bit; ZQ : in bit; VSS : linkage bit_vector(0 to 24); VDDQ : linkage bit_vector(0 to 15); VDD : linkage bit_vector(0 to 9); VREF : linkage bit_vector(0 to 1); BWN : in bit_vector(0 to 1); RN : in bit; WN : in bit; Q : buffer bit_vector(0 to 17); D : in bit_vector(0 to 17); SA : in bit_vector(1 to 20); DOFFN : in bit; CQ : buffer bit; CQN : buffer bit; C : in bit; CN : in bit; K : in bit; KN : in bit; NC : linkage bit_vector(0 to 39)); use STD_1149_1_2001.all ; attribute COMPONENT_CONFORMANCE of ISSI_QDR: entity is "STD_1149_1_1993"; attribute PIN_MAP of ISSI_QDR : entity is PHYSICAL_PIN_MAP; constant IS61QDRB22M18 : PIN_MAP_STRING := "TDO:R1, " & "TMS:R10, " & "TDI:R11, " & "TCK:R2, " & "ZQ:H11, " & "VSS:(C4, C8, D4, D5, D6, D7, D8, E5, " & " E6, E7, F6, G6, H6, J6, K6, L5, L6, L7, " & " M4, M5, M6, M7, M8, N4, N8), " & "VDDQ: (E4, E8, F4, F8, G4, G8, H3, H4, H8, H9, " & " J4, J8, K4, K8, L4, L8), " & "VDD: (F5, F7, G5, G7, H5, H7, J5, J7, K5, K7), " & "VREF: (H2, H10), " & "BWN: (B7,A5), " & "RN:A8, " & "WN:A4, " & "Q:( P11, M10, L11, K11, J10, F11, E11, C10, B11 ," & " B2, D3 , E3 , F2 , G3 , K3 , L2 , N3 , P3 )," & "D:( P10, N11, M11, K10, J11, G11, E10, D11, C11 ," & " B3 , C3 , D2 , F3 , G2 , J3 , L3 , M3 , N2 )," & "SA:(C6, C7, B8, N6, R9, R8, R7, P7, P8, N7, " & "C5, B4, R3, R4, P4, R5, P5, N5, A9, A3)," & "DOFFN:H1, " & "CQ:A11, " & "CQN:A1, " & "C:P6, " & "CN:R6, " & "K:B6, " & "KN:A6, " & "NC:( A2, A7 , B1 , B5 , B9 , B10, C1 , C2 , C9 , D1 , " & " D9, D10, E1 , E2 , E9 , F1 , F9 , F10, G1 , G9 , " & " G10, J1 , J2 , J9 , K1 , K2 , K9 , L1 , L9 , L10, " & " M1, M2 , M9 , N1 , N9 , N10, P1 , P2 , P9 , A10 ) " ; --Scan Port Identification attribute TAP_SCAN_IN of TDI: signal is true; attribute TAP_SCAN_MODE of TMS: signal is true; attribute TAP_SCAN_OUT of TDO: signal is true; attribute TAP_SCAN_CLOCK of TCK: signal is (20.0e6, BOTH); -- TAP Description attribute INSTRUCTION_LENGTH of ISSI_QDR: entity is 3; attribute INSTRUCTION_OPCODE of ISSI_QDR: entity is "EXTEST (000)," & "IDCODE (001)," & "SAMPLEZ (010)," & "PRIVATE1 (011)," & "SAMPLE (100)," & "PRELOAD (100)," & "PRIVATE2 (101)," & "PRIVATE3 (110)," & "BYPASS (111)"; attribute INSTRUCTION_CAPTURE of ISSI_QDR: entity is "001"; attribute INSTRUCTION_PRIVATE of ISSI_QDR: entity is "PRIVATE1 , PRIVATE2 , PRIVATE3"; attribute IDCODE_REGISTER of ISSI_QDR: entity is "000" & -- Revision Number "00" & -- Reserved "010" & -- def = 010 for 36Mb "0" & -- Reserved "10" & -- wx = 11 for x36, 10 for x18 "0" & -- Reserved "X" & -- t = 1 for DLL, 0 for non-DLL, ¡°X¡±controlled by DOFFN "0" & -- Reserved "1" & -- q = 1 for QDB2, 0 for DDRII "0" & -- Reserved "0" & -- b = 1 for burst of 4, 0 for burst of 2 "0" & -- Reserved "1" & -- s = 1 for separate I/0, 0 for common I/O "0" & -- Reserved Part Configuration , "00010100100" & -- ISSI JEDEC Code "1"; -- Required by IEEE Std 1149.1-1990 attribute REGISTER_ACCESS of ISSI_QDR: entity is "BOUNDARY (SAMPLEZ) "; attribute BOUNDARY_LENGTH of ISSI_QDR: entity is 109; attribute BOUNDARY_REGISTER of ISSI_QDR: entity is --num cell port function safe [ccell disval rslt] "0 (BC_4, CN, INPUT, X)," & -- 6R "1 (BC_4, C, INPUT, X)," & -- 6P "2 (BC_4, SA(4), INPUT, X)," & -- 6N "3 (BC_4, SA(8), INPUT, X)," & -- 7P "4 (BC_4, SA(10), INPUT, X)," & -- 7N "5 (BC_4, SA(7), INPUT, X)," & -- 7R "6 (BC_4, SA(6), INPUT, X)," & -- 8R "7 (BC_4, SA(9), INPUT, X)," & -- 8P "8 (BC_4, SA(5), INPUT, X)," & -- 9R "9 (BC_9, Q(0), output2, X)," & -- 11P "10 (BC_4, D(0), INPUT, X)," & -- 10P "11 (BC_1, *, INTERNAL, X)," & -- 10N "12 (BC_1, *, INTERNAL, X)," & -- 9P "13 (BC_9, Q(1), output2, X)," & -- 10M "14 (BC_4, D(1), INPUT, X)," & -- 11N "15 (BC_1, *, INTERNAL, X)," & -- 9M "16 (BC_1, *, INTERNAL, X)," & -- 9N "17 (BC_9, Q(2), output2, X)," & -- 11L "18 (BC_4, D(2), INPUT, X)," & -- 11M "19 (BC_1, *, INTERNAL, X)," & -- 9L "20 (BC_1, *, INTERNAL, X)," & -- 10L "21 (BC_9, Q(3), output2, X)," & -- 11K "22 (BC_4, D(3), INPUT, X)," & -- 10K "23 (BC_1, *, INTERNAL, X)," & -- 9J "24 (BC_1, *, INTERNAL, X)," & -- 9K "25 (BC_9, Q(4), output2, X)," & -- 10J "26 (BC_4, D(4), INPUT, X)," & -- 11J "27 (BC_4, ZQ, INPUT, X)," & -- 11H "28 (BC_1, *, INTERNAL, X)," & -- 10G "29 (BC_1, *, INTERNAL, X)," & -- 9G "30 (BC_9, Q(5), output2, X)," & -- 11F "31 (BC_4, D(5), INPUT, X)," & -- 11G "32 (BC_1, *, INTERNAL, X)," & -- 9F "33 (BC_1, *, INTERNAL, X)," & -- 10F "34 (BC_9, Q(6), output2, X)," & -- 11E "35 (BC_4, D(6), INPUT, X)," & -- 10E "36 (BC_1, *, INTERNAL, X)," & -- 10D "37 (BC_1, *, INTERNAL, X)," & -- 9E "38 (BC_9, Q(7), output2, X)," & -- 10C "39 (BC_4, D(7), INPUT, X)," & -- 11D "40 (BC_1, *, INTERNAL, X)," & -- 9C "41 (BC_1, *, INTERNAL, X)," & -- 9D "42 (BC_9, Q(8), output2, X)," & -- 11B "43 (BC_4, D(8), INPUT, X)," & -- 11C "44 (BC_1, *, INTERNAL, X)," & -- 9B "45 (BC_1, *, INTERNAL, X)," & -- 10B "46 (BC_9, CQ, output2, X)," & -- 11A "47 (BC_1, *, INTERNAL, X)," & -- 10A -- Address for 72MB "48 (BC_4, SA(19), INPUT, X)," & -- 9A "49 (BC_4, SA(3), INPUT, X)," & -- 8B "50 (BC_4, SA(2), INPUT, X)," & -- 7C --2_20 "51 (BC_4, SA(1), INPUT, X)," & -- 6C "52 (BC_4, RN, INPUT, X)," & -- 8A "53 (BC_1, *, INTERNAL, X)," & -- 7A "54 (BC_4, BWN(0), INPUT, X)," & -- 7B "55 (BC_4, K, INPUT, X)," & -- 6B "56 (BC_4, KN, INPUT, X)," & -- 6A "57 (BC_1, *, INTERNAL, X)," & -- 5B "58 (BC_4, BWN(1), INPUT, X)," & -- 5A "59 (BC_4, WN, INPUT, X)," & -- 4A "60 (BC_4, SA(11), INPUT, X)," & -- 5C "61 (BC_4, SA(12), INPUT, X)," & -- 4B "62 (BC_4, SA(20), INPUT, X)," & -- 3A -- 20_2 "63 (BC_1, *, INTERNAL, X)," & -- 2A "64 (BC_9, CQN, output2, X)," & -- 1A "65 (BC_9, Q(9), output2, X)," & -- 2B "66 (BC_4, D(9), INPUT, X)," & -- 3B "67 (BC_1, *, INTERNAL, X)," & -- 1C "68 (BC_1, *, INTERNAL, X)," & -- 1B "69 (BC_9, Q(10), output2, X)," & -- 3D "70 (BC_4, D(10), INPUT, X)," & -- 3C "71 (BC_1, *, INTERNAL, X)," & -- 1D "72 (BC_1, *, INTERNAL, X)," & -- 2C "73 (BC_9, Q(11), output2, X)," & -- 3E "74 (BC_4, D(11), INPUT, X)," & -- 2D "75 (BC_1, *, INTERNAL, X)," & -- 2E "76 (BC_1, *, INTERNAL, X)," & -- 1E "77 (BC_9, Q(12), output2, X)," & -- 2F "78 (BC_4, D(12), INPUT, X)," & -- 3F "79 (BC_1, *, INTERNAL, X)," & -- 1G "80 (BC_1, *, INTERNAL, X)," & -- 1F "81 (BC_9, Q(13), output2, X)," & -- 3G "82 (BC_4, D(13), INPUT, X)," & -- 2G "83 (BC_4, DOFFN, INPUT, X)," & -- 1H "84 (BC_1, *, INTERNAL, X)," & -- 1J "85 (BC_1, *, INTERNAL, X)," & -- 2J "86 (BC_9, Q(14), output2, X)," & -- 3K "87 (BC_4, D(14), INPUT, X)," & -- 3J "88 (BC_1, *, INTERNAL, X)," & -- 2K "89 (BC_1, *, INTERNAL, X)," & -- 1K "90 (BC_9, Q(15), output2, X)," & -- 2L "91 (BC_4, D(15), INPUT, X)," & -- 3L "92 (BC_1, *, INTERNAL, X)," & -- 1M "93 (BC_1, *, INTERNAL, X)," & -- 1L "94 (BC_9, Q(16), output2, X)," & -- 3N "95 (BC_4, D(16), INPUT, X)," & -- 3M "96 (BC_1, *, INTERNAL, X)," & -- 1N "97 (BC_1, *, INTERNAL, X)," & -- 2M "98 (BC_9, Q(17), output2, X)," & -- 3P "99 (BC_4, D(17), INPUT, X)," & -- 2N "100 (BC_1, *, INTERNAL, X)," & -- 2P "101 (BC_1, *, INTERNAL, X)," & -- 1P "102 (BC_4, SA(13), INPUT, X)," & -- 3R "103 (BC_4, SA(14), INPUT, X)," & -- 4R "104 (BC_4, SA(15), INPUT, X)," & -- 4P "105 (BC_4, SA(17), INPUT, X)," & -- 5P "106 (BC_4, SA(18), INPUT, X)," & -- 5N "107 (BC_4, SA(16), INPUT, X)," & -- 5R "108 (BC_1, *, INTERNAL, X)" ; -- "108 (BC_1, *, CONTROL, 0)"; attribute DESIGN_WARNING of ISSI_QDR: entity is "The SRAM provides a limited set of JTAG functions to test the interconnection " & "between SRAM I/Os and printed circuit board traces or other components. There " & "is no multiplexer in the path from I/O pins to the RAM core."; end ISSI_QDR ;