-- Copyright (C) 1995-2005 Altera Corporation -- File Name : 8160Q_D1.BSD -- Device : EPX8160Q208 (Second JTAG half of the device) -- Package : 208 Pin Plastic Quad Flat Pack (PQFP) -- Created by : Altera Corporation -- BSDL Version : 1.33 -- BSDL Status : Final -- Revision : 1.0, 7/1/95 -- History : 1.31, 8/15/98 -- Updated Info to Altera -- : 1.32, 10/18/99 -- Updated to 1994 spec -- : 1.33, 8/23/02 -- Changed file status to Final -- Verification : Software syntax checked on: -- ASSET Tool Box ver. 2.3d -- Genrad BSDL syntax checker ver. 4.01, a component -- of Scan Pathfinder(tm) and BasicSCAN(tm) -- HP 3070 BSDL Compiler -- JTAG Technologies PLDPROG ver. 2.7 -- Documentation : FLASHlogic Family Datasheet -- Note: This device is obsolete -- AN39 - JTAG Boundary Scan for Altera Devices -- -- -- IMPORTANT NOTICE -- -- Altera and EPX8160 are trademarks of Altera Corporation. -- Altera products, marketed under trademarks are protected -- under numerous US and foreign patents and pending -- applications, maskwork rights, and copyrights. Altera -- warrants performance of its semiconductor products to -- current specifications in accordance with Altera's standard -- warranty, but reserves the right to make changes to any -- products and services at any time without notice. Altera -- assumes no responsibility or liability arising out of the -- application or use of any information, product, or service -- described herein except as expressly agreed to in writing -- by Altera Corporation. Altera customers are advised to -- obtain the latest version of device specifications before -- relying on any published information and before placing -- orders for products or services. entity EPX8160Q208_1 is generic(PHYSICAL_PIN_MAP : string := "PQFP208"); port ( CLK3 : in bit; CLK4 : in bit; INP : in bit_vector(24 to 47); -- inputs -- I/O pins IO80 :inout bit; IO81 :inout bit; IO82 :inout bit; IO83 :inout bit; IO84 :inout bit; IO85 :inout bit; IO86 :inout bit; IO87 :inout bit; IO88 :inout bit; IO89 :inout bit; IO90 :inout bit; IO91 :inout bit; IO92 :inout bit; IO93 :inout bit; IO94 :inout bit; IO95 :inout bit; IO96 :inout bit; IO97 :inout bit; IO98 :inout bit; IO99 :inout bit; IO100:inout bit; IO103:inout bit; IO105:inout bit; IO107:inout bit; IO109:inout bit; IO110:inout bit; IO113:inout bit; IO115:inout bit; IO117:inout bit; IO119:inout bit; IO120:inout bit; IO121:inout bit; IO122:inout bit; IO123:inout bit; IO124:inout bit; IO125:inout bit; IO126:inout bit; IO127:inout bit; IO128:inout bit; IO129:inout bit; IO130:inout bit; IO131:inout bit; IO132:inout bit; IO133:inout bit; IO134:inout bit; IO135:inout bit; IO136:inout bit; IO137:inout bit; IO138:inout bit; IO139:inout bit; IO140:inout bit; IO143:inout bit; IO145:inout bit; IO147:inout bit; IO149:inout bit; IO150:inout bit; IO153:inout bit; IO155:inout bit; IO157:inout bit; IO159:inout bit; TCK, TMS, TDI : in bit; -- Scan Port inputs TDO : out bit; -- Scan Port output VCC : linkage bit_vector(1 to 2); -- VCC VCCO : linkage bit_vector(1 to 4); -- VCC VSS : linkage bit_vector(1 to 10); -- GND pins VPP1 : linkage bit -- VPP pin ); -- end of ports use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of EPX8160Q208_1 : entity is "STD_1149_1_1993"; attribute PIN_MAP of EPX8160Q208_1 : entity is PHYSICAL_PIN_MAP; -- NOTE: lots of the I/O pins in the 208 pin package are buried -- and do not have an external pin. These are represented as being -- above pin 319. constant PQFP208 : PIN_MAP_STRING := -- Define Pin Out of QFP -- I/O pins, listed by CFB "IO80:76,IO81:74,IO82:72,IO83:70,IO84:68, "& "IO85:66,IO86:64,IO87:62,IO88:60,IO89:58, "& "IO90:81,IO91:83,IO92:85,IO93:87,IO94:89, "& "IO95:91,IO96:93,IO97:95,IO98:97,IO99:99, "& "IO100:47,IO103:48,IO105:49,IO107:50,IO109:51, "& "IO110:110,IO113:109,IO115:108,IO117:107,IO119:106, "& "IO120:45,IO121:44,IO122:43,IO123:42,IO124:41, "& "IO125:37,IO126:36,IO127:35,IO128:34,IO129:33, "& "IO130:112,IO131:113,IO132:114,IO133:115,IO134:116, "& "IO135:120,IO136:121,IO137:122,IO138:123,IO139:124, "& "IO140:27,IO143:28,IO145:29,IO147:30,IO149:31, "& "IO150:130,IO153:129,IO155:128,IO157:127,IO159:126, "& -- IO CELLS NOT IN BOUNDARY_REGISTER, AND THEREFORE -- HAVE NO PIN DECLARATIONS -- IO101 , IO102 , IO104 , IO106 , IO108 , -- IO111 , IO112 , IO114 , IO116 , IO118 , -- IO141 , IO142 , IO144 , IO146 , IO148 , -- IO151 , IO152 , IO154 , IO156 , IO158 , -- Dedicated Clocks "CLK3:77, CLK4:80," & -- Power pins "VSS:(21,32,38,46,67,78,90,111,119,125)," & -- GND "VCC:(39, 118), VPP1:79," & "VCCO:(57,100,40,117), " & -- TAP controller pins "TCK:104, TMS:105, TDI:1, TDO:208," & -- Dedicated Inputs "INP:(103,102,101,98,96,94,92,88,86,84,82,75,73,71,69," & "65,63,61,59,56,55,54,53,52)"; attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Clock of TCK : signal is (8.0e6, BOTH); attribute Instruction_Length of EPX8160Q208_1: entity is 5; attribute Instruction_Opcode of EPX8160Q208_1: entity is "BYPASS (11111),"& "EXTEST (00000),"& "SAMPLE (00001),"& "IDCODE (00010),"& "LDVECT (00101),"& "FREAD (00110),"& -- Read FLASH cells "SWRITE (01111),"& -- Write SRAM cells "SREAD (10000),"& -- Read SRAM cells "FPGMALL1(10010),"& -- Program all FLASH cells to '1 "FPGM (10101),"& -- Program FLASH cells "UESCODE (10110),"& "FERASE (10001),"& -- FALSH erase. Do FPGAMALL1 first "RADLOAD (11000),"& -- Row ADdress LOAD "BSCAN (11100),"& -- Buried Macrocell Scan Chain "ISCAN (11110),"& -- Internal Macrocell Register Scan (destructive) "TRIBYP (11101),"& -- Boundary Hi-Z "PRIVATE (00011,00100,00111,01000,01001,01010,01011,01100,01101,"& "01110,10011,10100,10111,11001,11010,11011)"; attribute Instruction_Capture of EPX8160Q208_1: entity is "00001"; -- there is no Instruction_Disable attribute for EPX8160Q208_1 attribute Instruction_Private of EPX8160Q208_1: entity is "private"; attribute Idcode_Register of EPX8160Q208_1: entity is "0000" & --version "0000011000100011" & --part number "00000001001" & --manufacturers identity, 9h for Intel "1"; --required by the standard attribute Register_Access of EPX8160Q208_1: entity is "BYPASS (BYPASS, TRIBYP)," & -- 1149.1 bypass -- High-Z Bypass "BOUNDARY (EXTEST, SAMPLE)," & -- 1149.1 extest & sample "EPROM_VECTOR[43] (LDVECT)," & -- semi-private flash prog. "ROW_VECTOR[622] (FREAD, SWRITE, SREAD)," & -- semi-private flash read -- semi-private sram write -- semi-private sram read "VERIFY[1] (FPGM, FPGMALL1)," & -- semi-private flash verify "ERASE[1] (FERASE)," & -- semi-private flash verify "UES_CODE[622] (UESCODE)," & -- semi-private user code "ADDR[6] (RADLOAD)," & -- semi-private address load "BURIED_SCAN[20] (BSCAN)," & -- semi-private buried mcells "REGISTER_SCAN[80] (ISCAN)"; -- semi-private all mcells --{*******************************************************************} -- ISCAN CHAIN-The ISCAN chain scans out the device macrocell registers -- in the order given below. It goes from Macrocell 9 to 0 in each CFB, -- and from CFB 8 to CFB 15. See the appropriate application notes and -- datasheet restrictions on how to use this instruction. -- TDI -> IO89,IO88,IO87,IO86,IO85,IO84,IO83,IO82,IO81,IO80, -- IO99,IO98,IO97, ... , IO151, IO150 -> TDO --{*******************************************************************} -- BSCAN CHAIN-The BSCAN chain scans out the BURIED macrocell register -- output in the order given below. This chain is the equivalent of -- having INPUT cells on the feedback paths. This chain is provided -- because the feedbacks are not in the normal BOUNDARY chain. -- See the appropriate application notes and datasheet restrictions on -- how to use this instruction. -- TDI -> IO141,IO142,IO144,IO146,IO148, IO101,IO102,IO104,IO106,IO108, -- IO118,IO116,IO114,IO112,IO111...IO154,IO152,IO151 -> TDO --{*******************************************************************} attribute Boundary_Length of EPX8160Q208_1: entity is 206; attribute Boundary_Register of EPX8160Q208_1: entity is --num cell port function safe ccell dsval rslt " 0 (BC_1, *, CONTROLR, 0)," & -- IO150.OE " 1 (BC_1, IO150, output3, X, 0, 0, Z)," & -- IO150.OUT " 2 (BC_1, IO150, input, 0)," & -- IO150.IN " 3 (BC_1, *, CONTROLR, 0)," & -- IO153.OE " 4 (BC_1, IO153, output3, X, 3, 0, Z)," & -- IO153.OUT " 5 (BC_1, IO153, input, 0)," & -- IO153.IN " 6 (BC_1, *, CONTROLR, 0)," & -- IO155.OE " 7 (BC_1, IO155, output3, X, 6, 0, Z)," & -- IO155.OUT " 8 (BC_1, IO155, input, 0)," & -- IO155.IN " 9 (BC_1, *, CONTROLR, 0)," & -- IO157.OE " 10 (BC_1, IO157, output3, X, 9, 0, Z)," & -- IO157.OUT " 11 (BC_1, IO157, input, 0)," & -- IO157.IN " 12 (BC_1, *, CONTROLR, 0)," & -- IO159.OE " 13 (BC_1, IO159, output3, X, 12, 0, Z)," & -- IO159.OUT " 14 (BC_1, IO159, input, 0)," & -- IO159.IN " 15 (BC_1, *, CONTROLR, 0)," & -- IO139 " 16 (BC_1, IO139, output3, X, 15, 0, Z)," & " 17 (BC_1, IO139, input, 0)," & " 18 (BC_1, *, CONTROLR, 0)," & -- IO138 " 19 (BC_1, IO138, output3, X, 18, 0, Z)," & " 20 (BC_1, IO138, input, 0)," & " 21 (BC_1, *, CONTROLR, 0)," & -- IO137 " 22 (BC_1, IO137, output3, X, 21, 0, Z)," & " 23 (BC_1, IO137, input, 0)," & " 24 (BC_1, *, CONTROLR, 0)," & -- IO136 " 25 (BC_1, IO136, output3, X, 24, 0, Z)," & " 26 (BC_1, IO136, input, 0)," & " 27 (BC_1, *, CONTROLR, 0)," & -- IO135 " 28 (BC_1, IO135, output3, X, 27, 0, Z)," & " 29 (BC_1, IO135, input, 0)," & " 30 (BC_1, *, CONTROLR, 0)," & -- IO134 " 31 (BC_1, IO134, output3, X, 30, 0, Z)," & " 32 (BC_1, IO134, input, 0)," & " 33 (BC_1, *, CONTROLR, 0)," & -- IO133 " 34 (BC_1, IO133, output3, X, 33, 0, Z)," & " 35 (BC_1, IO133, input, 0)," & " 36 (BC_1, *, CONTROLR, 0)," & -- IO132 " 37 (BC_1, IO132, output3, X, 36, 0, Z)," & " 38 (BC_1, IO132, input, 0)," & " 39 (BC_1, *, CONTROLR, 0)," & -- IO131 " 40 (BC_1, IO131, output3, X, 39, 0, Z)," & " 41 (BC_1, IO131, input, 0)," & " 42 (BC_1, *, CONTROLR, 0)," & -- IO130 " 43 (BC_1, IO130, output3, X, 42, 0, Z)," & " 44 (BC_1, IO130, input, 0)," & " 45 (BC_1, *, CONTROLR, 0)," & -- IO110 " 46 (BC_1, IO110, output3, X, 45, 0, Z)," & " 47 (BC_1, IO110, input, 0)," & " 48 (BC_1, *, CONTROLR, 0)," & -- IO113 " 49 (BC_1, IO113, output3, X, 48, 0, Z)," & " 50 (BC_1, IO113, input, 0)," & " 51 (BC_1, *, CONTROLR, 0)," & -- IO115 " 52 (BC_1, IO115, output3, X, 51, 0, Z)," & " 53 (BC_1, IO115, input, 0)," & " 54 (BC_1, *, CONTROLR, 0)," & -- IO117 " 55 (BC_1, IO117, output3, X, 54, 0, Z)," & " 56 (BC_1, IO117, input, 0)," & " 57 (BC_1, *, CONTROLR, 0)," & -- IO119 " 58 (BC_1, IO119, output3, X, 57, 0, Z)," & " 59 (BC_1, IO119, input, 0)," & " 60 (BC_4, INP(24), INPUT, X)," & " 61 (BC_4, INP(25), INPUT, X)," & " 62 (BC_4, INP(26), INPUT, X)," & " 63 (BC_1, *, CONTROLR, 0)," & -- IO99 " 64 (BC_1, IO99, output3, X, 63, 0, Z)," & " 65 (BC_1, IO99, input, 0)," & " 66 (BC_4, INP(27), INPUT, X)," & " 67 (BC_1, *, CONTROLR, 0)," & -- IO98 " 68 (BC_1, IO98, output3, X, 67, 0, Z)," & " 69 (BC_1, IO98, input, 0)," & " 70 (BC_4, INP(28), INPUT, X)," & " 71 (BC_1, *, CONTROLR, 0)," & -- IO97 " 72 (BC_1, IO97, output3, X, 71, 0, Z)," & " 73 (BC_1, IO97, input, 0)," & " 74 (BC_4, INP(29), INPUT, X)," & " 75 (BC_1, *, CONTROLR, 0)," & -- IO96 " 76 (BC_1, IO96, output3, X, 75, 0, Z)," & " 77 (BC_1, IO96, input, 0)," & " 78 (BC_4, INP(30), INPUT, X)," & " 79 (BC_1, *, CONTROLR, 0)," & -- IO95 " 80 (BC_1, IO95, output3, X, 79, 0, Z)," & " 81 (BC_1, IO95, input, 0)," & " 82 (BC_1, *, CONTROLR, 0)," & -- IO94 " 83 (BC_1, IO94, output3, X, 82, 0, Z)," & " 84 (BC_1, IO94, input, 0)," & " 85 (BC_4, INP(31), INPUT, X)," & " 86 (BC_1, *, CONTROLR, 0)," & -- IO93 " 87 (BC_1, IO93, output3, X, 86, 0, Z)," & " 88 (BC_1, IO93, input, 0)," & " 89 (BC_4, INP(32), INPUT, X)," & " 90 (BC_1, *, CONTROLR, 0)," & -- IO92 " 91 (BC_1, IO92, output3, X, 90, 0, Z)," & " 92 (BC_1, IO92, input, 0)," & " 93 (BC_4, INP(33), INPUT, X)," & " 94 (BC_1, *, CONTROLR, 0)," & -- IO91 " 95 (BC_1, IO91, output3, X, 94, 0, Z)," & " 96 (BC_1, IO91, input, 0)," & " 97 (BC_4, INP(34), INPUT, X)," & " 98 (BC_1, *, CONTROLR, 0)," & -- IO90 " 99 (BC_1, IO90, output3, X, 98, 0, Z)," & "100 (BC_1, IO90, input, 0)," & "101 (BC_4, CLK4, INPUT, X)," & -- Device CLK1 "102 (BC_4, CLK3, INPUT, X)," & -- Device CLK2 "103 (BC_1, *, CONTROLR, 0)," & -- IO80 "104 (BC_1, IO80, output3, X, 103, 0, Z)," & "105 (BC_1, IO80, input, 0)," & "106 (BC_4, INP(35), INPUT, X)," & "107 (BC_1, *, CONTROLR, 0)," & -- IO81 "108 (BC_1, IO81, output3, X, 107, 0, Z)," & "109 (BC_1, IO81, input, 0)," & "110 (BC_4, INP(36), INPUT, X)," & "111 (BC_1, *, CONTROLR, 0)," & -- IO82 "112 (BC_1, IO82, output3, X, 111, 0, Z)," & "113 (BC_1, IO82, input, 0)," & "114 (BC_4, INP(37), INPUT, X)," & "115 (BC_1, *, CONTROLR, 0)," & -- IO83 "116 (BC_1, IO83, output3, X, 115, 0, Z)," & "117 (BC_1, IO83, input, 0)," & "118 (BC_4, INP(38), INPUT, X)," & "119 (BC_1, *, CONTROLR, 0)," & -- IO84 "120 (BC_1, IO84, output3, X, 119, 0, Z)," & "121 (BC_1, IO84, input, 0)," & "122 (BC_1, *, CONTROLR, 0)," & -- IO85 "123 (BC_1, IO85, output3, X, 122, 0, Z)," & "124 (BC_1, IO85, input, 0)," & "125 (BC_4, INP(39), INPUT, X)," & "126 (BC_1, *, CONTROLR, 0)," & -- IO86 "127 (BC_1, IO86, output3, X, 126, 0, Z)," & "128 (BC_1, IO86, input, 0)," & "129 (BC_4, INP(40), INPUT, X)," & "130 (BC_1, *, CONTROLR, 0)," & -- IO87 "131 (BC_1, IO87, output3, X, 130, 0, Z)," & "132 (BC_1, IO87, input, 0)," & "133 (BC_4, INP(41), INPUT, X)," & "134 (BC_1, *, CONTROLR, 0)," & -- IO88 "135 (BC_1, IO88, output3, X, 134, 0, Z)," & "136 (BC_1, IO88, input, 0)," & "137 (BC_4, INP(42), INPUT, X)," & "138 (BC_1, *, CONTROLR, 0)," & -- IO89 "139 (BC_1, IO89, output3, X, 138, 0, Z)," & "140 (BC_1, IO89, input, 0)," & "141 (BC_4, INP(43), INPUT, X)," & "142 (BC_4, INP(44), INPUT, X)," & "143 (BC_4, INP(45), INPUT, X)," & "144 (BC_4, INP(46), INPUT, X)," & "145 (BC_4, INP(47), INPUT, X)," & "146 (BC_1, *, CONTROLR, 0)," & -- IO109 "147 (BC_1, IO109, output3, X, 146, 0, Z)," & "148 (BC_1, IO109, input, 0)," & "149 (BC_1, *, CONTROLR, 0)," & -- IO107 "150 (BC_1, IO107, output3, X, 149, 0, Z)," & "151 (BC_1, IO107, input, 0)," & "152 (BC_1, *, CONTROLR, 0)," & -- IO105 "153 (BC_1, IO105, output3, X, 152, 0, Z)," & "154 (BC_1, IO105, input, 0)," & "155 (BC_1, *, CONTROLR, 0)," & -- IO103 "156 (BC_1, IO103, output3, X, 155, 0, Z)," & "157 (BC_1, IO103, input, 0)," & "158 (BC_1, *, CONTROLR, 0)," & -- IO100 "159 (BC_1, IO100, output3, X, 158, 0, Z)," & "160 (BC_1, IO100, input, 0)," & "161 (BC_1, *, CONTROLR, 0)," & -- IO120 "162 (BC_1, IO120, output3, X, 161, 0, Z)," & "163 (BC_1, IO120, input, 0)," & "164 (BC_1, *, CONTROLR, 0)," & -- IO121 "165 (BC_1, IO121, output3, X, 164, 0, Z)," & "166 (BC_1, IO121, input, 0)," & "167 (BC_1, *, CONTROLR, 0)," & -- IO122 "168 (BC_1, IO122, output3, X, 167, 0, Z)," & "169 (BC_1, IO122, input, 0)," & "170 (BC_1, *, CONTROLR, 0)," & -- IO123 "171 (BC_1, IO123, output3, X, 170, 0, Z)," & "172 (BC_1, IO123, input, 0)," & "173 (BC_1, *, CONTROLR, 0)," & -- IO124 "174 (BC_1, IO124, output3, X, 173, 0, Z)," & "175 (BC_1, IO124, input, 0)," & "176 (BC_1, *, CONTROLR, 0)," & -- IO125 "177 (BC_1, IO125, output3, X, 176, 0, Z)," & "178 (BC_1, IO125, input, 0)," & "179 (BC_1, *, CONTROLR, 0)," & -- IO126 "180 (BC_1, IO126, output3, X, 179, 0, Z)," & "181 (BC_1, IO126, input, 0)," & "182 (BC_1, *, CONTROLR, 0)," & -- IO127 "183 (BC_1, IO127, output3, X, 182, 0, Z)," & "184 (BC_1, IO127, input, 0)," & "185 (BC_1, *, CONTROLR, 0)," & -- IO128 "186 (BC_1, IO128, output3, X, 185, 0, Z)," & "187 (BC_1, IO128, input, 0)," & "188 (BC_1, *, CONTROLR, 0)," & -- IO129 "189 (BC_1, IO129, output3, X, 188, 0, Z)," & "190 (BC_1, IO129, input, 0)," & "191 (BC_1, *, CONTROLR, 0)," & -- IO149 "192 (BC_1, IO149, output3, X, 191, 0, Z)," & "193 (BC_1, IO149, input, 0)," & "194 (BC_1, *, CONTROLR, 0)," & -- IO147 "195 (BC_1, IO147, output3, X, 194, 0, Z)," & "196 (BC_1, IO147, input, 0)," & "197 (BC_1, *, CONTROLR, 0)," & -- IO145 "198 (BC_1, IO145, output3, X, 197, 0, Z)," & "199 (BC_1, IO145, input, 0)," & "200 (BC_1, *, CONTROLR, 0)," & -- IO143 "201 (BC_1, IO143, output3, X, 200, 0, Z)," & "202 (BC_1, IO143, input, 0)," & "203 (BC_1, *, CONTROLR, 0)," & -- IO140 "204 (BC_1, IO140, output3, X, 203, 0, Z)," & "205 (BC_1, IO140, input, 0)"; end EPX8160Q208_1;