BSDL Files Library for JTAG
The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BS/JTAG tools

Quick Instruments - a new way for board- and system-level test
BSDL File: XCF01S Download View details  


--$ XILINX$RCSfile: xcf01s.bsd,v $
--$ XILINX$Revision: 1.4 $
-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /  Vendor:         Xilinx
-- \   \   \/   Version:        v1.0 (PROM BSDL template version)
--  \   \       Application:    Generate_Prom_Bsdl_Files.pl, 1.00
--  /   /       Filename:       xcf01s.bsd
-- /___/   /\   Generated:      Wed Oct 11 19:34:19 2006
-- \   \  /  \  State:          $State: PRELIMINARY $
--  \___\/\___\                  
--
-- Device:      XCF01S
-- Package(s):  GENERIC (using VO20 package as basis)
-- Purpose:     IEEE 1149.1 BSDL file
-- Reference:   None
-- Revisions:   
--
------------------------------------------------------------------------------
-- Technical Support:
--
-- Find the latest version of this BSDL file, find technical support answers, 
--  or find contact information at:  http://www.support.xilinx.com
--
------------------------------------------------------------------------------
-- Special Instructions:
--
-- This BSDL file reflects the pre-configuration behavior. To reflect
--  the post-configuration JTAG behavior (if any), edit this file as 
--  described below:
--      1. Rename file and entity if necessary to avoid name collisions.
--      2. Modify USERCODE value in USERCODE_REGISTER declaration.
------------------------------------------------------------------------------
-- BSDL Silicon Validation Information
--  None.
------------------------------------------------------------------------------
entity XCF01S is

generic (PHYSICAL_PIN_MAP : string := "VO20");

port (
    CE:         in      bit;
    CEO:        out     bit;
    CF:         out     bit;
    CLK:        in      bit;
    D0:         out     bit;
    OE_RESET:   inout   bit;
    TCK:        in      bit;
    TDI:        in      bit;
    TDO:        out     bit;
    TMS:        in      bit;
    GND:        linkage bit;
    VCCINT:     linkage bit;
    VCCJ:       linkage bit;
    VCCO:       linkage bit;
    DNC:        linkage bit_vector(1 to 6)
); --end port list

use STD_1149_1_2001.all;

attribute COMPONENT_CONFORMANCE of XCF01S : entity is 
    "STD_1149_1_2001";

attribute PIN_MAP of XCF01S : entity is 
    PHYSICAL_PIN_MAP;

constant VO20: PIN_MAP_STRING:=
    "CE:        10," &
    "CEO:       13," &
    "CF:        7," &
    "CLK:       3," &
    "D0:        1," &
    "OE_RESET:  8," &
    "TCK:       6," &
    "TDI:       4," &
    "TDO:       17," &
    "TMS:       5," &
    "GND:       11," &
    "VCCINT:    18," &
    "VCCJ:      20," &
    "VCCO:      19," &
    "DNC:       (2, 9, 12, 14, 15, 16)";

attribute TAP_SCAN_IN    of TDI : signal is true;
attribute TAP_SCAN_MODE  of TMS : signal is true;
attribute TAP_SCAN_OUT   of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (15.00e+06, BOTH);
attribute INSTRUCTION_LENGTH of XCF01S : entity is 
    8;

attribute INSTRUCTION_OPCODE of XCF01S : entity is
    -- IEEE 1149.1 standard instructions
    "BYPASS             (11111111)," &
    "SAMPLE             (00000001)," &
    "PRELOAD            (00000001)," &
    "EXTEST             (00000000)," &
    "IDCODE             (11111110)," &
    "USERCODE           (11111101)," &
    "HIGHZ              (11111100)," &
    "CLAMP              (11111010)," &
    -- Xilinx special function instructions
    "CONFIG             (11101110)," &
    -- Xilinx ISP instructions
    "ISPEN              (11101000)," &
    "ISPENC             (11101001)," &
    "NORMRST            (11110000)," &
    "FPGM               (11101010)," &
    "FERASE             (11101100)," &
    "FADDR              (11101011)," &
    "FDATA0             (11101101)," &
    "FVFY0              (11101111)," &
    "FDATA3             (11110011)," &
    "FVFY1              (11111000)," &
    "FVFY3              (11100010)," &
    "FVFY6              (11100110)," &
    "FBLANK0            (11100101)," &
    "FBLANK3            (11100001)," &
    "FBLANK6            (11100100)," &
    "SERASE             (00001010)," &
    "ISC_READ_INFO      (11110001)," &
    "ISCTESTSTATUS      (11100011)," &
    "priv3              (11100111)," &
    "priv4              (11110110)," &
    "priv5              (11100000)," &
    "priv6              (11110111)," &
    "priv7              (11110010)," &
    "ISCCLRSTATUS       (11110100)," &
    "priv9              (11110101)";
                        
attribute INSTRUCTION_CAPTURE of XCF01S: entity is 
    "XXXXX001";
-- IR[7:6]= Erase/Program Result (10=success; 01=fail; 00/11=N/A)
-- IR[5]  = Erase/Program Status (1=ready; 0=busy)
-- IR[4]  = ISP mode (1=in-system programming mode; 0=normal download mode)
-- IR[3]  = JTAG read-protection (1=secured; 0=unsecured)
-- IR[2]  = 0 value
-- IR[1:0]= 01 as defined by IEEE STD 1149.1

attribute INSTRUCTION_PRIVATE of XCF01S: entity is
    "priv3," &
    "priv4," &
    "priv5," &
    "priv6," &
    "priv7," &
    "priv9";

attribute IDCODE_REGISTER of XCF01S: entity is
    "XXXX" &                -- version
    "0101000001000100" &    -- part number
    "00001001001" &         -- manufacturer's id
    "1";                    -- required by IEEE STD 1149.1

attribute USERCODE_REGISTER of XCF01S: entity is
    "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";


attribute REGISTER_ACCESS of XCF01S : entity is
    -- IEEE 1149.1 standard data registers
    "BOUNDARY           (EXTEST, SAMPLE, PRELOAD),"&
    "DEVICE_ID          (IDCODE, USERCODE),"&
    "BYPASS             (BYPASS, HIGHZ, CLAMP, CONFIG)," &
    -- Xilinx ISP data registers
    "ISC_DEFAULT[1]     (NORMRST, FPGM),"&
    "ISPENABLE[6]       (ISPEN, ISPENC)," &
    "ADDRESS[16]        (FADDR, FERASE, SERASE),"&
    "DATA0[2048]        (FVFY0, FDATA0),"&
    "DATA1[1048576]     (FVFY1, FBLANK0),"&
    "DATA3[6]           (FVFY3, FDATA3, FBLANK3),"&
    "USERCODEV[32]      (FVFY6, FBLANK6),"&
    "ISC_INFO[8]        (ISC_READ_INFO),"&
    "XSC_STATUS[8]      (ISCTESTSTATUS, ISCCLRSTATUS)";

attribute BOUNDARY_LENGTH of XCF01S : entity is 
    25;

attribute BOUNDARY_REGISTER of XCF01S : entity is
-- cellnum (type,     port, function, safe[, ccell, disval, disrslt])
    "    0 (BC_1,      CLK, input,       X                         )," &
    "    1 (BC_1,        *, internal,    0                         )," &
    "    2 (BC_1,        *, internal,    X                         )," &
    "    3 (BC_1,        *, controlr,    0                         )," &
    "    4 (BC_1,       D0, output3,     X,      3,      0,       Z)," &
    "    5 (BC_1,        *, internal,    0                         )," &
    "    6 (BC_1,        *, internal,    X                         )," &
    "    7 (BC_1,        *, internal,    0                         )," &
    "    8 (BC_1,        *, internal,    X                         )," &
    "    9 (BC_1,        *, internal,    0                         )," &
    "   10 (BC_1,        *, internal,    X                         )," &
    "   11 (BC_1,        *, controlr,    0                         )," &
    "   12 (BC_1,      CEO, output3,     X,     11,      0,       Z)," &
    "   13 (BC_1,        *, internal,    0                         )," &
    "   14 (BC_1,        *, internal,    X                         )," &
    "   15 (BC_1,       CE, input,       X                         )," &
    "   16 (BC_1,        *, internal,    0                         )," &
    "   17 (BC_1,        *, internal,    X                         )," &
    "   18 (BC_1,        *, controlr,    0                         )," &
    "   19 (BC_1, OE_RESET, output3,     X,     18,      0,       Z)," &
    "   20 (BC_1, OE_RESET, input,       X                         )," &
    "   21 (BC_1,        *, controlr,    0                         )," &
    "   22 (BC_1,       CF, output3,     X,     21,      0,       Z)," &
    "   23 (BC_1,        *, internal,    0                         )," &
    "   24 (BC_1,        *, internal,    X                         )";

attribute DESIGN_WARNING of XCF01S : entity is
    "The FERASE and FPGM instructions require " &
        "a falling-edge of TCK AFTER the Run-Test/Idle TAP state is entered " &
        "in order to start the operation corresponding to the instruction.  " &
    "The FVFY0, FVFY1, and FBLANK0 instructions activate a non-standard, " &
        "output-only data register that does not pass TDI through to TDO.  Thus, " &
        "data beyond the specififed length of the corresponding data register " &
        "is undefined. " &
        "When the FVFY0, FVFY1, and FBLANK0 instructions are in use, " &
        "all components between TDO of this device and the tester must select " &
        "the BYPASS register to avoid acting on the undefined data values. " &
    "Do not drive CF low when CF is connected to the PROGRAM/PROG_B pin of " &
        "a Virtex, Virtex-E, Virtex-4, Spartan-II, Spartan-IIE FPGA and when " &
        "the FPGA is in the same boundary-scan chain as this XCF01S. " &
        "A Low applied to the PROGRAM/PROG_B pin of these FPGAs resets the TAP " &
        "in these FPGAs.";

end XCF01S;


This library contains 8972 BSDL files (for 7016 distinct entities) from 68 vendors
Last BSDL model (sam4s16b) was added on Dec 7, 2017 14:26
info@bsdl.info