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BSDL File: GS8162Z36BB Download View details  


-- GSI  8162Z36 PBGA J T A G   S O F T W A R E
-- BSDL File Generated: 6th April 2005
--
-- Revision History:
--Rev B 09/29/05   1) Updated Address pin and Byte Write pin order
entity GS8162Z36BB is
     generic (PHYSICAL_PIN_MAP : string := "BGA_PACKAGE");

     port (
         ADDR:   in      bit_vector(0 to 18);
         CK:     in      bit;
         Ba:     in      bit;
         Bb:     in      bit;
         Bc:     in      bit;
         Bd:     in      bit;
         W:      in      bit;
         E1:     in      bit;
         E2:     in      bit;
         E3:     in      bit;
         G:      in      bit; 
         CKE:    in      bit;
         ADV:    in      bit; 
         DQa:    inout   bit_vector(1 to 9);
         DQb:    inout   bit_vector(1 to 9);
         DQc:    inout   bit_vector(1 to 9);
         DQd:    inout   bit_vector(1 to 9);
         ZZ:     in      bit;
--         ZQ:     in      bit;
         FT:     in      bit;
         LBO:    in      bit;
         TMS:    in      bit;
         TDI:    in      bit;
         TDO:    out     bit;
         TCK:    in      bit;
         VDD:    linkage     bit_vector(0 to 4);
         VSS:    linkage     bit_vector(0 to 15);
         VDDQ:   linkage     bit_vector(0 to 9);
         NC:     linkage     bit_vector(0 to 12)
       );

     use STD_1149_1_1990.all;

     attribute PIN_MAP of GS8162Z36BB : entity is PHYSICAL_PIN_MAP;

     constant BGA_PACKAGE : PIN_MAP_STRING := 

     "ADDR:  (P4,N4,C6,B5,A5,A6,R6,T5,A4,G4,T3,R2,A2,T4,C2,A3,B3,C3,C5), " &
     "CK:     K4, " &
     "Bc:     G3, " &
     "Bd:     L3, " &
     "Ba:     L5, " &
     "Bb:     G5, " &
     "W:      H4, " &
     "E1:     E4, " &
     "E2:     B2, " &
     "E3:     B6, " &
     "G:      F4, " &
     "CKE:    M4, " &
     "ADV:    B4, " &
     "DQa:   (P6,P7,N7,N6,M6,L7,L6,K6,K7), " &
     "DQb:   (H6,H7,G7,G6,F6,E6,E7,D7,D6), " &
     "DQc:   (D2,D1,E1,E2,F2,G1,G2,H2,H1), " &
     "DQd:   (K2,K1,L1,L2,M2,N2,N1,P1,P2), " &
     "ZZ:     T7, " &
--     "ZQ:     D4, " &
     "FT:     R5, " &
     "LBO:    R3, " &
     "TMS:    U2, " &
     "TDI:    U3, " &
     "TDO:    U5, " &
     "TCK:    U4, " &
     "VDD:   (C4,J2,J4,J6,R4), " &
     "VSS:   (D3,E3,F3,H3,K3,M3,N3,P3,D5,E5,F5,H5,K5,M5,N5,P5), " &
     "VDDQ:  (A1,F1,J1,M1,U1,A7,F7,J7,M7,U7), " &
     "NC:    (B1,C1,J3,J5,R7,R1,T1,T2,T6,L4,U6,B7,C7)";

     attribute TAP_SCAN_IN    of  TDI : signal is true;
     attribute TAP_SCAN_OUT   of  TDO : signal is true;
     attribute TAP_SCAN_MODE  of  TMS : signal is true;
     attribute TAP_SCAN_CLOCK of  TCK : signal is (10.0e6, BOTH);

     attribute INSTRUCTION_LENGTH of GS8162Z36BB : entity is 3;

     attribute INSTRUCTION_OPCODE of GS8162Z36BB : entity is 
        "EXTEST       (000)," &
        "SAMPLE       (100)," &
        "IDCODE       (001)," &
        "SAMPLZ       (010)," &
        "BYPASS       (111)";


     attribute INSTRUCTION_CAPTURE of GS8162Z36BB : entity is "001";
     attribute IDCODE_REGISTER   of GS8162Z36BB : entity is 
     "00000000000000010000000110110011";
    
     attribute REGISTER_ACCESS of GS8162Z36BB : entity is 
       "BOUNDARY  (EXTEST,SAMPLE,SAMPLZ),"&
       "IDCODE    (IDCODE),"&
       "BYPASS    (BYPASS)";   

     attribute BOUNDARY_CELLS of GS8162Z36BB : entity is 
        "BC_1,BC_4";

     attribute BOUNDARY_LENGTH of GS8162Z36BB : entity is 117;

     attribute BOUNDARY_REGISTER of GS8162Z36BB : entity is 
     -- num    cell     port    func     safe [ccell disval rslt]

 "0      (BC_4, *    ,internal, X)," &
 "1      (BC_4, *    ,internal, X)," &
 "2      (BC_4, *    ,internal, X)," &
 "3      (BC_1, ADDR(18), input, X)," &
 "4      (BC_1, ADDR(17), input, X)," &
 "5      (BC_1, ADDR(16), input, X)," &
 "6      (BC_1, ADDR(15), input, X)," &
 "7      (BC_1, ADDR(14), input, X)," &
 "8      (BC_1, ADDR(13), input, X)," &
 "9      (BC_1, ADDR(12), input, X)," &
 "10     (BC_1, DQc(1), output3, X, 116, 0, Z)," &
 "11     (BC_1, DQc(1), input, X)," &
 "12     (BC_1, DQc(2), output3, X, 116, 0, Z)," &
 "13     (BC_1, DQc(2), input, X)," &
 "14     (BC_1, DQc(3), output3, X, 116, 0, Z)," &
 "15     (BC_1, DQc(3), input, X)," &
 "16     (BC_1, DQc(4), output3, X, 116, 0, Z)," &
 "17     (BC_1, DQc(4), input, X)," &
 "18     (BC_1, DQc(5), output3, X, 116, 0, Z)," &
 "19     (BC_1, DQc(5), input, X)," &
 "20     (BC_1, DQc(6), output3, X, 116, 0, Z)," &
 "21     (BC_1, DQc(6), input, X)," &
 "22     (BC_1, DQc(7), output3, X, 116, 0, Z)," &
 "23     (BC_1, DQc(7), input, X)," &
 "24     (BC_1, DQc(8), output3, X, 116, 0, Z)," &
 "25     (BC_1, DQc(8), input, X)," &
 "26     (BC_1, DQc(9), output3, X, 116, 0, Z)," &
 "27     (BC_1, DQc(9), input, X)," &
 "28     (BC_1, ZZ       , input, X)," &
 "29     (BC_4, *        ,internal, X)," &
 "30     (BC_1, DQd(1), output3, X, 116, 0, Z)," &
 "31     (BC_1, DQd(1), input, X)," &
 "32     (BC_1, DQd(2), output3, X, 116, 0, Z)," &
 "33     (BC_1, DQd(2), input, X)," &
 "34     (BC_1, DQd(3), output3, X, 116, 0, Z)," &
 "35     (BC_1, DQd(3), input, X)," &
 "36     (BC_1, DQd(4), output3, X, 116, 0, Z)," &
 "37     (BC_1, DQd(4), input, X)," &
 "38     (BC_1, DQd(5), output3, X, 116, 0, Z)," &
 "39     (BC_1, DQd(5), input, X)," &
 "40     (BC_1, DQd(6), output3, X, 116, 0, Z)," &
 "41     (BC_1, DQd(6), input, X)," &
 "42     (BC_1, DQd(7), output3, X, 116, 0, Z)," &
 "43     (BC_1, DQd(7), input, X)," &
 "44     (BC_1, DQd(8), output3, X, 116, 0, Z)," &
 "45     (BC_1, DQd(8), input, X)," &
 "46     (BC_1, DQd(9), output3, X, 116, 0, Z)," &
 "47     (BC_1, DQd(9), input, X)," &
 "48     (BC_4, *    ,internal, X)," &
 "49     (BC_1, ADDR(11), input, X)," &
 "50     (BC_1, ADDR(10), input, X)," &
 "51     (BC_1, ADDR(9), input, X)," &
 "52     (BC_1, ADDR(8), input, X)," &
 "53     (BC_1, ADV, input, X)," &
 "54     (BC_1, G, input, X)," &
 "55     (BC_1, CKE, input, X)," &
 "56     (BC_1, W, input, X)," &
 "57     (BC_1, CK, input, X)," &
 "58     (BC_4, *    ,internal, X)," &
 "59     (BC_4, *    ,internal, X)," &
 "60     (BC_4, *    ,internal, X)," &
 "61     (BC_4, *    ,internal, X)," &
 "62    (BC_1, E3, input, X)," &
 "63    (BC_1, Bc, input, X)," &
 "64    (BC_1, Bd, input, X)," &
 "65    (BC_1, Ba, input, X)," &
 "66    (BC_1, Bb, input, X)," &
 "67    (BC_1, E2, input, X)," &
 "68    (BC_1, E1, input, X)," &
 "69    (BC_1, ADDR(7), input, X)," &
 "70    (BC_1, ADDR(6), input, X)," &
 "71    (BC_1, DQa(1), output3, X, 116, 0, Z)," &
 "72    (BC_1, DQa(1), input, X)," &
 "73    (BC_1, DQa(2), output3, X, 116, 0, Z)," &
 "74    (BC_1, DQa(2), input, X)," &
 "75    (BC_1, DQa(3), output3, X, 116, 0, Z)," &
 "76    (BC_1, DQa(3), input, X)," &
 "77    (BC_1, DQa(4), output3, X, 116, 0, Z)," &
 "78    (BC_1, DQa(4), input, X)," &
 "79    (BC_1, DQa(5), output3, X, 116, 0, Z)," &
 "80    (BC_1, DQa(5), input, X)," &
 "81    (BC_1, DQa(6), output3, X, 116, 0, Z)," &
 "82    (BC_1, DQa(6), input, X)," &
 "83    (BC_1, DQa(7), output3, X, 116, 0, Z)," &
 "84    (BC_1, DQa(7), input, X)," &
 "85    (BC_1, DQa(8), output3, X, 116, 0, Z)," &
 "86    (BC_1, DQa(8), input, X)," &
 "87    (BC_1, DQa(9), output3, X, 116, 0, Z)," &
 "88    (BC_1, DQa(9), input, X)," &
 "89    (BC_1, FT, input, X)," &
 "90    (BC_4, *    ,internal, X)," &
 "91    (BC_1, DQb(1), output3, X, 116, 0, Z)," &
 "92    (BC_1, DQb(1), input, X)," &
 "93    (BC_1, DQb(2), output3, X, 116, 0, Z)," &
 "94    (BC_1, DQb(2), input, X)," &
 "95    (BC_1, DQb(3), output3, X, 116, 0, Z)," &
 "96    (BC_1, DQb(3), input, X)," &
 "97    (BC_1, DQb(4), output3, X, 116, 0, Z)," &
 "98    (BC_1, DQb(4), input, X)," &
 "99    (BC_1, DQb(5), output3, X, 116, 0, Z)," &
 "100   (BC_1, DQb(5), input, X)," &
 "101   (BC_1, DQb(6), output3, X, 116, 0, Z)," &
 "102   (BC_1, DQb(6), input, X)," &
 "103   (BC_1, DQb(7), output3, X, 116, 0, Z)," &
 "104   (BC_1, DQb(7), input, X)," &
 "105   (BC_1, DQb(8), output3, X, 116, 0, Z)," &
 "106   (BC_1, DQb(8), input, X)," &
 "107   (BC_1, DQb(9), output3, X, 116, 0, Z)," &
 "108   (BC_1, DQb(9), input, X)," &
 "109   (BC_1, LBO, input, X)," &
 "110   (BC_1, ADDR(5), input, X)," &
 "111   (BC_1, ADDR(4), input, X)," &
 "112   (BC_1, ADDR(3), input, X)," &
 "113   (BC_1, ADDR(2), input, X)," &
 "114   (BC_1, ADDR(1), input, X)," &
 "115   (BC_1, ADDR(0), input, X)," &
 "116   (BC_1, *, control, 0)" ;

end GS8162Z36BB;

This library contains 7714 BSDL files (for 6086 distinct entities) from 64 vendors
Last BSDL model (CY7C1512KV18) was added on Sep 15, 2017 14:30
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