BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: Tsi572

-- ***************************************************************
--      Company:  Integrated Device Technology, Inc.
--
--      Tundra Document number: 35B805C_BS001_03
--
--      Title: BSDL file of Tsi572
--      Generated by :DFT
--
--      Release status: formal issue
--      Security level: client use
--      BSDL Version 2001
--      Group ownership: DFT         Revision Date: 
--      Released by  :       
--      Revision History:
--              Feb 14, 2008:   initial release
--     		Aug 11, 2009:	Updated with IDT formatting
--     		Oct 23, 2009:	rename TCK2_P/N as VSS
--              
--      BSDL Syntax Checker ->  passed Oct 27, 2009 
--           
--           
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2b-Build20051027.004 on 04/03/07 16:33:00
-- BSDL Version 2001
-- The default acjt_lvl[4:0] which is controled by IRbits[29:25] is set to 2'h03, 
-- tx_lvl which is controlled by IRbits[38:34] is set to 4'h1F
-- To program acjt_lvl and tx_lvl IRbits[33] has to be set to 0
-- VHDL for LVS_BSCAN_CELLS is appended at the end of this file. This VHDL file need to be uploaded
-- when compiling this BSDL.

entity Tsi572 is 
    generic (PHYSICAL_PIN_MAP : string := "HSBGA_399_21");

    port (
        -- Port List
        SP0_TD_P             : out      bit;
        SP0_TD_N             : out      bit;
        SP0_RD_P             : in       bit;
        SP0_RD_N             : in       bit;
        SP0_TC_P             : out      bit;
        SP0_TC_N             : out      bit;
        SP0_RC_P             : in       bit;
        SP0_RC_N             : in       bit;
        SP0_TB_P             : out      bit;
        SP0_TB_N             : out      bit;
        SP0_RB_P             : in       bit;
        SP0_RB_N             : in       bit;
        SP0_TA_P             : out      bit;
        SP0_TA_N             : out      bit;
        SP0_RA_P             : in       bit;
        SP0_RA_N             : in       bit;
        SP0_REXT             : linkage  bit;
        SP2_TB_P             : out      bit;
        SP2_TB_N             : out      bit;
        SP2_RB_P             : in       bit;
        SP2_RB_N             : in       bit;
        SP2_TA_P             : out      bit;
        SP2_TA_N             : out      bit;
        SP2_RA_P             : in       bit;
        SP2_RA_N             : in       bit;
        SP2_REXT             : linkage  bit;
        SP4_TB_P             : out      bit;
        SP4_TB_N             : out      bit;
        SP4_RB_P             : in       bit;
        SP4_RB_N             : in       bit;
        SP4_TA_P             : out      bit;
        SP4_TA_N             : out      bit;
        SP4_RA_P             : in       bit;
        SP4_RA_N             : in       bit;
        SP4_REXT             : linkage  bit;
        SP6_TD_P             : out      bit;
        SP6_TD_N             : out      bit;
        SP6_RD_P             : in       bit;
        SP6_RD_N             : in       bit;
        SP6_TC_P             : out      bit;
        SP6_TC_N             : out      bit;
        SP6_RC_P             : in       bit;
        SP6_RC_N             : in       bit;
        SP6_TB_P             : out      bit;
        SP6_TB_N             : out      bit;
        SP6_RB_P             : in       bit;
        SP6_RB_N             : in       bit;
        SP6_TA_P             : out      bit;
        SP6_TA_N             : out      bit;
        SP6_RA_P             : in       bit;
        SP6_RA_N             : in       bit;
        SP6_REXT             : linkage  bit;
        P_CLK                : in       bit;
        S_CLK_P              : linkage  bit;
        S_CLK_N              : linkage  bit;
        I2C_SCLK             : inout    bit;
        I2C_SD               : inout    bit;
        I2C_DISABLE          : inout    bit;
        I2C_MA               : inout    bit;
        I2C_SA               : inout    bit_vector( 1 downto 0 );
        I2C_SEL              : inout    bit;
        HARD_RST_B           : linkage  bit;
        INT_B                : inout    bit;
        SW_RST_B             : inout    bit;
        TCK                  : in       bit;
        TMS                  : in       bit;
        TDI                  : in       bit;
        TDO                  : out      bit;
        TRST_B               : in       bit;
        BCE                  : in       bit;
        DO                   : out      bit;
        SP_RX_SWAP           : inout    bit;
        SP_TX_SWAP           : inout    bit;
        SP_IO_SPEED          : inout    bit_vector( 1 downto 0 );
        SP1_PWRDN            : inout    bit;
        SP2_PWRDN            : inout    bit;
        SP3_PWRDN            : inout    bit;
        SP4_PWRDN            : inout    bit;
        SP5_PWRDN            : inout    bit;
        SP6_PWRDN            : inout    bit;
        SP7_PWRDN            : inout    bit;
        SP0_MODESEL          : inout    bit;
        SP2_MODESEL          : inout    bit;
        SP4_MODESEL          : inout    bit;
        SP6_MODESEL          : inout    bit;
        TEST10_MODESEL         : inout    bit;
        MCES                 : inout    bit;
        VDD_IO               : linkage  bit_vector( 11 downto 0 );
        VSS_IO               : linkage  bit_vector( 12 downto 0 );
        VSS                  : linkage  bit_vector( 184 downto 0 );
        VDD                  : linkage  bit_vector( 31 downto 0 );
        SP_VDD               : linkage  bit_vector( 30 downto 0 );
        REF_AVDD             : linkage  bit_vector( 1 downto 0 );
        SP_AVDD              : linkage  bit_vector( 13 downto 0 ));

    use STD_1149_1_2001.all;
    use STD_1149_6_2003.all;
    use LVS_BSCAN_CELLS.all;

    attribute COMPONENT_CONFORMANCE of Tsi572: entity is "STD_1149_1_2001";

    --Pin mappings

    attribute PIN_MAP of Tsi572: entity is PHYSICAL_PIN_MAP;

    constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := 
    "SP0_TD_P             : L1   , " &
    "SP0_TD_N             : L2   , " &
    "SP0_RD_P             : L5   , " &
    "SP0_RD_N             : L4   , " &
    "SP0_TC_P             : J2   , " &
    "SP0_TC_N             : J1   , " &
    "SP0_RC_P             : J4   , " &
    "SP0_RC_N             : J5   , " &
    "SP0_TB_P             : G1   , " &
    "SP0_TB_N             : G2   , " &
    "SP0_RB_P             : G5   , " &
    "SP0_RB_N             : G4   , " &
    "SP0_TA_P             : E2   , " &
    "SP0_TA_N             : E1   , " &
    "SP0_RA_P             : E4   , " &
    "SP0_RA_N             : E5   , " &
    "SP0_REXT             : H4   , " &
    "SP2_TB_P             : Y9  , " &
    "SP2_TB_N             : W9  , " &
    "SP2_RB_P             : T9  , " &
    "SP2_RB_N             : U9  , " &
    "SP2_TA_P             : W7   , " &
    "SP2_TA_N             : Y7   , " &
    "SP2_RA_P             : U7   , " &
    "SP2_RA_N             : T7   , " &
    "SP2_REXT             : U10  , " &
    "SP4_TB_P             : L20  , " &
    "SP4_TB_N             : L19  , " &
    "SP4_RB_P             : L16  , " &
    "SP4_RB_N             : L17  , " &
    "SP4_TA_P             : N19  , " &
    "SP4_TA_N             : N20  , " &
    "SP4_RA_P             : N17  , " &
    "SP4_RA_N             : N16  , " &
    "SP4_REXT             : K17  , " &
    "SP6_TD_P             : A8   , " &
    "SP6_TD_N             : B8   , " &
    "SP6_RD_P             : E8   , " &
    "SP6_RD_N             : D8   , " &
    "SP6_TC_P             : B10  , " &
    "SP6_TC_N             : A10  , " &
    "SP6_RC_P             : D10  , " &
    "SP6_RC_N             : E10  , " &
    "SP6_TB_P             : A12  , " &
    "SP6_TB_N             : B12  , " &
    "SP6_RB_P             : E12  , " &
    "SP6_RB_N             : D12  , " &
    "SP6_TA_P             : B14  , " &
    "SP6_TA_N             : A14  , " &
    "SP6_RA_P             : D14  , " &
    "SP6_RA_N             : E14  , " &
    "SP6_REXT             : D11  , " &
    "P_CLK                : Y1   , " &
    "S_CLK_P              : B18  , " &
    "S_CLK_N              : B19  , " &
    "I2C_SCLK             : Y19  , " &
    "I2C_SD               : W18  , " &
    "I2C_DISABLE          : U18  , " &
    "I2C_MA               : W16  , " &
    "I2C_SA               :(R17  , " &  -- I2C_SA[1]
                           "R16 ), " &  -- I2C_SA[0]
    "I2C_SEL              : T17  , " &
    "HARD_RST_B           : Y3   , " &
    "INT_B                : U2   , " &
    "SW_RST_B             : V3   , " &
    "TCK                  : Y20  , " &
    "TMS                  : U20  , " &
    "TDI                  : V20  , " &
    "TDO                  : V19  , " &
    "TRST_B               : W20  , " &
    "BCE                  : R20  , " &
    "DO                   : W2   , " &
    "SP_RX_SWAP           : T19  , " &
    "SP_TX_SWAP           : T20  , " &
    "SP_IO_SPEED          :(U16  , " &  -- SP_IO_SPEED[1]
                           "T16 ), " &  -- SP_IO_SPEED[0]
    "SP1_PWRDN            : Y16  , " &
    "SP2_PWRDN            : W17  , " &
    "SP3_PWRDN            : Y17  , " &
    "SP4_PWRDN            : N2  , " &
    "SP5_PWRDN            : N3  , " &
    "SP6_PWRDN            : P1  , " &
    "SP7_PWRDN            : P3  , " &
    "SP0_MODESEL          : V16  , " &
    "SP2_MODESEL          : Y13  , " &
    "SP4_MODESEL          : V1  , " &
    "SP6_MODESEL          : U5  , " &
    "TEST10_MODESEL         : V4 , " &
    "MCES                 : R19  , " &
    "VDD_IO               :(Y2  , " &  -- VDD_IO[11]
                           "W19  , " &  -- VDD_IO[10]
                           "W4  , " &  -- VDD_IO[9]
                           "V2  , " &  -- VDD_IO[8]
                           "U19  , " &  -- VDD_IO[7]
                           "U17  , " &  -- VDD_IO[6]
                           "U4  , " &  -- VDD_IO[5]
                           "T3  , " &  -- VDD_IO[4]
                           "T2  , " &  -- VDD_IO[3]
                           "R4  , " &  -- VDD_IO[2]
                           "P2  , " &  -- VDD_IO[1]
                           "N4 ), " &  -- VDD_IO[0]
    "VSS_IO               :(Y18  , " &  -- VSS_IO[12]
                           "Y4  , " &  -- VSS_IO[11]
                           "W1  , " &  -- VSS_IO[10]
                           "V18  , " &  -- VSS_IO[9]
                           "V17  , " &  -- VSS_IO[8]
                           "U3 , " &  -- VSS_IO[7]
                           "U1  , " &  -- VSS_IO[6]
                           "T18  , " &  -- VSS_IO[5]
                           "T4  , " &  -- VSS_IO[4]
                           "T1  , " &  -- VSS_IO[3]
                           "R1  , " &  -- VSS_IO[2]
                           "P4  , " &  -- VSS_IO[1]
                           "N1 ), " &  -- VSS_IO[0]
    "VSS               :(Y15  , " &  -- VSS[184]
                           "W3  , " &  -- VSS[183] -- DI
                           "D19  , " &  -- VSS[182] -- TCK2_N
                           "D18  , " &  -- VSS[181] -- TCK2_P
                           "Y14  , " &  -- VSS[180]
                           "Y12  , " &  -- VSS[179]
                           "Y10  , " &  -- VSS[178]
                           "Y8  , " &  -- VSS[177]
                           "Y6  , " &  -- VSS[176]
                           "Y5  , " &  -- VSS[175]
                           "W15  , " &  -- VSS[174]
                           "W12  , " &  -- VSS[173]
                           "W8  , " &  -- VSS[172]
                           "W6  , " &  -- VSS[171]
                           "V15  , " &  -- VSS[170]
                           "V14  , " &  -- VSS[169]
                           "V12  , " &  -- VSS[168]
                           "V10  , " &  -- VSS[167]
                           "V8  , " &  -- VSS[166]
                           "V6  , " &  -- VSS[165]
                           "U15  , " &  -- VSS[164]
                           "U12  , " &  -- VSS[163]
                           "U8  , " &  -- VSS[162]
                           "U6  , " &  -- VSS[161]
                           "T15  , " &  -- VSS[160]
                           "T6  , " &  -- VSS[159]
                           "T5  , " &  -- VSS[158]
                           "R18  , " &  -- VSS[157]
                           "R15  , " &  -- VSS[156]
                           "R14  , " &  -- VSS[155]
                           "R12  , " &  -- VSS[154]
                           "R10  , " &  -- VSS[153]
                           "R9  , " &  -- VSS[152]
                           "R8  , " &  -- VSS[151]
                           "R7  , " &  -- VSS[150]
                           "R6  , " &  -- VSS[149]
                           "R5  , " &  -- VSS[148]
                           "P20  , " &  -- VSS[147]
                           "P18  , " &  -- VSS[146]
                           "P17  , " &  -- VSS[145]
                           "P16  , " &  -- VSS[144]
                           "P15  , " &  -- VSS[143]
                           "P14  , " &  -- VSS[142]
                           "P12  , " &  -- VSS[141]
                           "P10  , " &  -- VSS[140]
                           "P8  , " &  -- VSS[139]
                           "P6  , " &  -- VSS[138]
                           "P5  , " &  -- VSS[137]
                           "N15  , " &  -- VSS[136]
                           "N13  , " &  -- VSS[135]
                           "N11  , " &  -- VSS[134]
                           "N9  , " &  -- VSS[133]
                           "N7  , " &  -- VSS[132]
                           "N6  , " &  -- VSS[131]
                           "N5  , " &  -- VSS[130]
                           "M20  , " &  -- VSS[129]
                           "M19  , " &  -- VSS[128]
                           "M18  , " &  -- VSS[127]
                           "M17  , " &  -- VSS[126]
                           "M15  , " &  -- VSS[125]
                           "M14  , " &  -- VSS[124]
                           "M12  , " &  -- VSS[123]
                           "M10  , " &  -- VSS[122]
                           "M8  , " &  -- VSS[121]
                           "M6  , " &  -- VSS[120]
                           "M5  , " &  -- VSS[119]
                           "M4  , " &  -- VSS[118]
                           "M3  , " &  -- VSS[117]
                           "M1  , " &  -- VSS[116]
                           "L13  , " &  -- VSS[115]
                           "L11  , " &  -- VSS[114]
                           "L9  , " &  -- VSS[113]
                           "L7  , " &  -- VSS[112]
                           "K20  , " &  -- VSS[111]
                           "K18  , " &  -- VSS[110]
                           "K15  , " &  -- VSS[109]
                           "K14  , " &  -- VSS[108]
                           "K12  , " &  -- VSS[107]
                           "K10  , " &  -- VSS[106]
                           "K8  , " &  -- VSS[105]
                           "K6  , " &  -- VSS[104]
                           "K4  , " &  -- VSS[103]
                           "K3  , " &  -- VSS[102]
                           "K2  , " &  -- VSS[101]
                           "K1  , " &  -- VSS[100]
                           "J15  , " &  -- VSS[99]
                           "J13  , " &  -- VSS[98]
                           "J11  , " &  -- VSS[97]
                           "J9  , " &  -- VSS[96]
                           "J7  , " &  -- VSS[95]
                           "J6  , " &  -- VSS[94]
                           "H20  , " &  -- VSS[93]
                           "H19  , " &  -- VSS[92]
                           "H18  , " &  -- VSS[91]
                           "H17  , " &  -- VSS[90]
                           "H14  , " &  -- VSS[89]
                           "H12  , " &  -- VSS[88]
                           "H10  , " &  -- VSS[87]
                           "H8  , " &  -- VSS[86]
                           "H6  , " &  -- VSS[85]
                           "H3  , " &  -- VSS[84]
                           "H1  , " &  -- VSS[83]
                           "G15  , " &  -- VSS[82]
                           "G13  , " &  -- VSS[81]
                           "G11  , " &  -- VSS[80]
                           "G9  , " &  -- VSS[79]
                           "G7  , " &  -- VSS[78]
                           "G6  , " &  -- VSS[77]
                           "F20  , " &  -- VSS[76]
                           "F19  , " &  -- VSS[75]
                           "F18  , " &  -- VSS[74]
                           "F15  , " &  -- VSS[73]
                           "F14  , " &  -- VSS[72]
                           "F13  , " &  -- VSS[71]
                           "F12  , " &  -- VSS[70]
                           "F10  , " &  -- VSS[69]
                           "F9  , " &  -- VSS[68]
                           "F8  , " &  -- VSS[67]
                           "F7  , " &  -- VSS[66]
                           "F6  , " &  -- VSS[65]
                           "F4  , " &  -- VSS[64]
                           "F3  , " &  -- VSS[63]
                           "F2  , " &  -- VSS[62]
                           "F1  , " &  -- VSS[61]
                           "E20  , " &  -- VSS[60]
                           "E19  , " &  -- VSS[59]
                           "E18  , " &  -- VSS[58]
                           "E17  , " &  -- VSS[57]
                           "E16  , " &  -- VSS[56]
                           "E15  , " &  -- VSS[55]
                           "E7  , " &  -- VSS[54]
                           "E6  , " &  -- VSS[53]
                           "D20  , " &  -- VSS[52]
                           "D17 , " &  -- VSS[51]
                           "D16 , " &  -- VSS[50]
                           "D15 , " &  -- VSS[49]
                           "D13 , " &  -- VSS[48]
                           "D9 , " &  -- VSS[47]
                           "D7 , " &  -- VSS[46]
                           "D6 , " &  -- VSS[45]
                           "D5 , " &  -- VSS[44]
                           "D4 , " &  -- VSS[43]
                           "D3 , " &  -- VSS[42]
                           "D1 , " &  -- VSS[41]
                           "C19 , " &  -- VSS[40]
                           "C17 , " &  -- VSS[39]
                           "C16 , " &  -- VSS[38]
                           "C15 , " &  -- VSS[37]
                           "C13 , " &  -- VSS[36]
                           "C11 , " &  -- VSS[35]
                           "C9 , " &  -- VSS[34]
                           "C7 , " &  -- VSS[33]
                           "C6 , " &  -- VSS[32]
                           "C5 , " &  -- VSS[31]
                           "C4 , " &  -- VSS[30]
                           "C3 , " &  -- VSS[29]
                           "C2 , " &  -- VSS[28]
                           "C1 , " &  -- VSS[27]
                           "B20 , " &  -- VSS[26]
                           "B17 , " &  -- VSS[25]
                           "B16 , " &  -- VSS[24]
                           "B13 , " &  -- VSS[23]
                           "B9 , " &  -- VSS[22]
                           "B7 , " &  -- VSS[21]
                           "B6 , " &  -- VSS[20]
                           "B5 , " &  -- VSS[19]
                           "B4 , " &  -- VSS[18]
                           "B3 , " &  -- VSS[17]
                           "B2 , " &  -- VSS[16]
                           "B1 , " &  -- VSS[15]
                           "A20 , " &  -- VSS[14]
                           "A19 , " &  -- VSS[13]
                           "A18 , " &  -- VSS[12]
                           "A17 , " &  -- VSS[11]
                           "A16 , " &  -- VSS[10]
                           "A15 , " &  -- VSS[9]
                           "A13 , " &  -- VSS[8]
                           "A11 , " &  -- VSS[7]
                           "A9 , " &  -- VSS[6]
                           "A7 , " &  -- VSS[5]
                           "A6 , " &  -- VSS[4]
                           "A5 , " &  -- VSS[3]
                           "A4 , " &  -- VSS[2]
                           "A3 , " &  -- VSS[1]
                           "A2 ), " &  -- VSS[0]
    "VDD                :(P13  , " &  -- VDD[31]
                           "P11  , " &  -- VDD[30]
                           "P9  , " &  -- VDD[29]
                           "P7  , " &  -- VDD[28]
                           "N14  , " &  -- VDD[27]
                           "N12  , " &  -- VDD[26]
                           "N10  , " &  -- VDD[25]
                           "N8  , " &  -- VDD[24]
                           "M13  , " &  -- VDD[23]
                           "M11  , " &  -- VDD[22]
                           "M9  , " &  -- VDD[21]
                           "M7  , " &  -- VDD[20]
                           "L14  , " &  -- VDD[19]
                           "L12  , " &  -- VDD[18]
                           "L10  , " &  -- VDD[17]
                           "L8  , " &  -- VDD[16]
                           "K13  , " &  -- VDD[15]
                           "K11  , " &  -- VDD[14]
                           "K9  , " &  -- VDD[13]
                           "K7  , " &  -- VDD[12]
                           "J14  , " &  -- VDD[11]
                           "J12  , " &  -- VDD[10]
                           "J10  , " &  -- VDD[9]
                           "J8  , " &  -- VDD[8]
                           "H13  , " &  -- VDD[7]
                           "H11  , " &  -- VDD[6]
                           "H9  , " &  -- VDD[5]
                           "H7  , " &  -- VDD[4]
                           "G14  , " &  -- VDD[3]
                           "G12  , " &  -- VDD[2]
                           "G10  , " &  -- VDD[1]
                           "G8 ), " &  -- VDD[0]

    "SP_VDD                :(W14  , " &  -- SP_VDD[30]
                           "W10  , " &  -- SP_VDD[29]
                           "V13  , " &  -- SP_VDD[28]
                           "V11  , " &  -- SP_VDD[27]
                           "V9  , " &  -- SP_VDD[26]
                           "V7  , " &  -- SP_VDD[25]
                           "T12  , " &  -- SP_VDD[24]
                           "T8  , " &  -- SP_VDD[23]
                           "P19  , " &  -- SP_VDD[22]
                           "N18  , " &  -- SP_VDD[21]
                           "M16  , " &  -- SP_VDD[20]
                           "M2  , " &  -- SP_VDD[19]
                           "L18  , " &  -- SP_VDD[18]
                           "L3  , " &  -- SP_VDD[17]
                           "K19  , " &  -- SP_VDD[16]
                           "J18  , " &  -- SP_VDD[15]
                           "J3  , " &  -- SP_VDD[14]
                           "H16  , " &  -- SP_VDD[13]
                           "H2  , " &  -- SP_VDD[12]
                           "G18  , " &  -- SP_VDD[11]
                           "G3  , " &  -- SP_VDD[10]
                           "F5  , " &  -- SP_VDD[9]
                           "E13  , " &  -- SP_VDD[8]
                           "E3  , " &  -- SP_VDD[7]
                           "D2  , " &  -- SP_VDD[6]
                           "C14  , " &  -- SP_VDD[5]
                           "C12  , " &  -- SP_VDD[4]
                           "C10  , " &  -- SP_VDD[3]
                           "C8  , " &  -- SP_VDD[2]
                           "B15  , " &  -- SP_VDD[1]
                           "B11 ), " &  -- SP_VDD[0]

    "SP_AVDD              :(T14  , " &  -- SP_AVDD[13]
                           "T10  , " &  -- SP_AVDD[12]
                           "R13  , " &  -- SP_AVDD[11]
                           "R11  , " &  -- SP_AVDD[10]
                           "L15  , " &  -- SP_AVDD[9]
                           "L6  , " &  -- SP_AVDD[8]
                           "K16  , " &  -- SP_AVDD[7]
                           "K5  , " &  -- SP_AVDD[6]
                           "H15  , " &  -- SP_AVDD[5]
                           "H5  , " &  -- SP_AVDD[4]
                           "F16  , " &  -- SP_AVDD[3]
                           "F11  , " &  -- SP_AVDD[2]
                           "E11  , " &  -- SP_AVDD[1]
                           "E9 ), " &  -- SP_AVDD[0]

    "REF_AVDD             :(C20  , " &  -- REF_AVDD[1]
                           "C18 ) " ;  -- REF_AVDD[0]


    attribute PORT_GROUPING of Tsi572 : entity is 
        "Differential_Current ( (SP0_TB_P, SP0_TB_N), " &
                                "(SP0_RB_P, SP0_RB_N), " &
                                "(SP0_TA_P, SP0_TA_N), " &
                                "(SP0_RA_P, SP0_RA_N), " &
                                "(SP0_TC_P, SP0_TC_N), " &
                                "(SP0_RC_P, SP0_RC_N), " &
                                "(SP0_TD_P, SP0_TD_N), " &
                                "(SP0_RD_P, SP0_RD_N), " &
                                "(SP2_TB_P, SP2_TB_N), " &
                                "(SP2_RB_P, SP2_RB_N), " &
                                "(SP2_TA_P, SP2_TA_N), " &
                                "(SP2_RA_P, SP2_RA_N), " &
                                "(SP4_TB_P, SP4_TB_N), " &
                                "(SP4_RB_P, SP4_RB_N), " &
                                "(SP4_TA_P, SP4_TA_N), " &
                                "(SP4_RA_P, SP4_RA_N), " &
                                "(SP6_TB_P, SP6_TB_N), " &
                                "(SP6_RB_P, SP6_RB_N), " &
                                "(SP6_TA_P, SP6_TA_N), " &
                                "(SP6_RA_P, SP6_RA_N), " &
                                "(SP6_TC_P, SP6_TC_N), " &
                                "(SP6_RC_P, SP6_RC_N), " &
                                "(SP6_TD_P, SP6_TD_N), " &
                                "(SP6_RD_P, SP6_RD_N)) " ;
 
 
 
   attribute TAP_SCAN_RESET of TRST_B                       : signal is true;
   attribute TAP_SCAN_IN    of TDI                          : signal is true;
   attribute TAP_SCAN_MODE  of TMS                          : signal is true;
   attribute TAP_SCAN_OUT   of TDO                          : signal is true;
   attribute TAP_SCAN_CLOCK of TCK                          : signal is (1.0000000000000000000e+07, BOTH);


    attribute COMPLIANCE_PATTERNS of Tsi572 : entity is 
        "(BCE) (1)";
 
 
 
   attribute INSTRUCTION_LENGTH of Tsi572: entity is 61;
 
   attribute INSTRUCTION_OPCODE of Tsi572: entity is
      "IDCODE       (1111111111111111111111111111111111111111111111111111111111110)," &
      "BYPASS       (0000000000000000000000000000000000000000000000000000000000000, 1111111111111111111111111111111111111111111111111111111111111)," &
      "EXTEST       (1111111111111111111111000000111111001111111111111111111101000)," &
      "EXTEST_PULSE (1111111111111111111111000000111111001111111101111111111101000)," &
      "EXTEST_TRAIN (1111111111111111111111000000111111001111111011111111111101000)," &
      "SAMPLE       (1111111111111111111111000000111111001111111111111111111111000)," &
      "PRELOAD      (1111111111111111111111000000111111001111111111111111111111000)," &
      "CLAMP        (1111111111111111111111000000111111001111111111111111111101111) " ;
 
   attribute INSTRUCTION_CAPTURE of Tsi572: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
 
   attribute IDCODE_REGISTER of Tsi572: entity is
      "1000"             & -- version
      "0000010101110101" & -- part number
      "00010110011"      & -- manufacturer's identity
      "1";                   -- required by 1149.1
 
   attribute REGISTER_ACCESS of Tsi572: entity is
      "BOUNDARY     ( EXTEST_PULSE, EXTEST_TRAIN )," &
      "BOUNDARY     ( SAMPLE, PRELOAD )," &
      "BYPASS       ( CLAMP, BYPASS ) " ;


    --Boundary scan definition
    attribute BOUNDARY_LENGTH of Tsi572: entity is 116;

    attribute BOUNDARY_REGISTER of Tsi572: entity is 
    -- num  cell         port               function       safe     [ccell disval  rslt]
    "  115  (BC_1       , *                , control      , 0   )                          ,"&
    "  114  (AC_1       , SP0_TB_P         , output3      , X    ,   115    , 0     , Z   ),"&
    "  113  (BC_4       , SP0_RB_P         , observe_only , X   )                          ,"&
    "  112  (BC_4       , SP0_RB_N         , observe_only , X   )                          ,"&
    "  111  (BC_1       , *                , control      , 0   )                          ,"&
    "  110  (AC_1       , SP0_TA_P         , output3      , X    ,   111    , 0     , Z   ),"&
    "  109  (BC_4       , SP0_RA_P         , observe_only , X   )                          ,"&
    "  108  (BC_4       , SP0_RA_N         , observe_only , X   )                          ,"&
    "  107  (BC_1       , *                , control      , 0   )                          ,"&
    "  106  (AC_1       , SP0_TC_P         , output3      , X    ,   107    , 0     , Z   ),"&
    "  105  (BC_4       , SP0_RC_P         , observe_only , X   )                          ,"&
    "  104  (BC_4       , SP0_RC_N         , observe_only , X   )                          ,"&
    "  103  (BC_1       , *                , control      , 0   )                          ,"&
    "  102  (AC_1       , SP0_TD_P         , output3      , X    ,   103    , 0     , Z   ),"&
    "  101  (BC_4       , SP0_RD_P         , observe_only , X   )                          ,"&
    "  100  (BC_4       , SP0_RD_N         , observe_only , X   )                          ,"&
    "  99   (BC_1       , *                , control      , 0   )                          ,"&
    "  98   (AC_1       , SP2_TB_P         , output3      , X    ,   99     , 0     , Z   ),"&
    "  97   (BC_4       , SP2_RB_P         , observe_only , X   )                          ,"&
    "  96   (BC_4       , SP2_RB_N         , observe_only , X   )                          ,"&
    "  95   (BC_1       , *                , control      , 0   )                          ,"&
    "  94   (AC_1       , SP2_TA_P         , output3      , X    ,   95     , 0     , Z   ),"&
    "  93   (BC_4       , SP2_RA_P         , observe_only , X   )                          ,"&
    "  92   (BC_4       , SP2_RA_N         , observe_only , X   )                          ,"&
    "  91   (BC_0       , *                , internal , 0   )                              ,"&
    "  90   (BC_0       , *         , internal , X   ),"&
    "  89   (BC_0       , *         , internal , X   ),"&
    "  88   (BC_0       , *         , internal , X   ),"&
    "  87   (BC_0       , *                , internal      , 0   )                          ,"&
    "  86   (BC_0       , *         , internal , X   ),"&
    "  85   (BC_0       , *         , internal , X   ),"&
    "  84   (BC_0       , *         , internal , X   ),"&
    "  83   (BC_1       , *                , control      , 0   )                          ,"&
    "  82   (AC_1       , SP4_TB_P         , output3      , X    ,   83     , 0     , Z   ),"&
    "  81   (BC_4       , SP4_RB_P         , observe_only , X   )                          ,"&
    "  80   (BC_4       , SP4_RB_N         , observe_only , X   )                          ,"&
    "  79   (BC_1       , *                , control      , 0   )                          ,"&
    "  78   (AC_1       , SP4_TA_P         , output3      , X    ,   79     , 0     , Z   ),"&
    "  77   (BC_4       , SP4_RA_P         , observe_only , X   )                          ,"&
    "  76   (BC_4       , SP4_RA_N         , observe_only , X   )                          ,"&
    "  75   (BC_0       , *                , internal      , 0   )                          ,"&
    "  74   (BC_0       , *         , internal , X   ),"&
    "  73   (BC_0       , *         , internal , X   )                          ,"&
    "  72   (BC_0       , *         , internal , X   )                          ,"&
    "  71   (BC_0       , *                , internal      , 0   )                          ,"&
    "  70   (BC_0       , *         , internal , X   ),"&
    "  69   (BC_0       , *         , internal , X   )                          ,"&
    "  68   (BC_0       , *         , internal , X   )                          ,"&
    "  67   (BC_1       , *                , control      , 0   )                          ,"&
    "  66   (AC_1       , SP6_TB_P         , output3      , X    ,   67     , 0     , Z   ),"&
    "  65   (BC_4       , SP6_RB_P         , observe_only , X   )                          ,"&
    "  64   (BC_4       , SP6_RB_N         , observe_only , X   )                          ,"&
    "  63   (BC_1       , *                , control      , 0   )                          ,"&
    "  62   (AC_1       , SP6_TA_P         , output3      , X    ,   63     , 0     , Z   ),"&
    "  61   (BC_4       , SP6_RA_P         , observe_only , X   )                          ,"&
    "  60   (BC_4       , SP6_RA_N         , observe_only , X   )                          ,"&
    "  59   (BC_1       , *                , control      , 0   )                          ,"&
    "  58   (AC_1       , SP6_TC_P         , output3      , X    ,   59     , 0     , Z   ),"&
    "  57   (BC_4       , SP6_RC_P         , observe_only , X   )                          ,"&
    "  56   (BC_4       , SP6_RC_N         , observe_only , X   )                          ,"&
    "  55   (BC_1       , *                , control      , 0   )                          ,"&
    "  54   (AC_1       , SP6_TD_P         , output3      , X    ,   55     , 0     , Z   ),"&
    "  53   (BC_4       , SP6_RD_P         , observe_only , X   )                          ,"&
    "  52   (BC_4       , SP6_RD_N         , observe_only , X   )                          ,"&
    "  51   (BC_4       , P_CLK            , clock        , X   )                          ,"&
    "  50   (BC_2       , *                , control      , 0   )                          ,"&
    "  49   (LV_BC_7    , I2C_SCLK         , bidir        , X    ,   50     , 0     , Z   ),"&
    "  48   (BC_2       , *                , control      , 0   )                          ,"&
    "  47   (LV_BC_7    , I2C_SD           , bidir        , X    ,   48     , 0     , Z   ),"&
    "  46   (BC_2       , *                , control      , 0   )                          ,"&
    "  45   (LV_BC_7    , I2C_DISABLE      , bidir        , X    ,   46     , 0     , Z   ),"&
    "  44   (BC_2       , *                , control      , 0   )                          ,"&
    "  43   (LV_BC_7    , I2C_MA           , bidir        , X    ,   44     , 0     , Z   ),"&
    "  42   (LV_BC_7    , I2C_SA(1)        , bidir        , X    ,   44     , 0     , Z   ),"&
    "  41   (LV_BC_7    , I2C_SA(0)        , bidir        , X    ,   44     , 0     , Z   ),"&
    "  40   (LV_BC_7    , I2C_SEL          , bidir        , X    ,   44     , 0     , Z   ),"&
    "  39   (BC_2       , *                , control      , 0   )                          ,"&
    "  38   (LV_BC_7    , INT_B            , bidir        , X    ,   39     , 0     , Z   ),"&
    "  37   (BC_2       , *                , control      , 0   )                          ,"&
    "  36   (LV_BC_7    , SW_RST_B         , bidir        , X    ,   37     , 0     , Z   ),"&
    "  35   (BC_2       , *                , control      , 0   )                          ,"&
    "  34   (BC_2       , DO               , output3      , X    ,   35     , 0     , Z   ),"&
    "  33   (BC_2       , *                , control      , 0   )                          ,"&
    "  32   (LV_BC_7    , SP_RX_SWAP       , bidir        , X    ,   33     , 0     , Z   ),"&
    "  31   (LV_BC_7    , SP_TX_SWAP       , bidir        , X    ,   33     , 0     , Z   ),"&
    "  30   (LV_BC_7    , SP_IO_SPEED(1)   , bidir        , X    ,   33     , 0     , Z   ),"&
    "  29   (LV_BC_7    , SP_IO_SPEED(0)   , bidir        , X    ,   33     , 0     , Z   ),"&
    "  28   (BC_2       , *                , control      , 0   )                          ,"&
    "  27   (LV_BC_7    , SP1_PWRDN        , bidir        , X    ,   28     , 0     , Z   ),"&
    "  26   (LV_BC_7    , SP2_PWRDN        , bidir        , X    ,   28     , 0     , Z   ),"&
    "  25   (LV_BC_7    , SP3_PWRDN        , bidir        , X    ,   28     , 0     , Z   ),"&
    "  24   (BC_2       , *                , control      , 0   )                          ,"&
    "  23   (LV_BC_7    , SP4_PWRDN        , bidir        , X    ,   24     , 0     , Z   ),"&
    "  22   (LV_BC_7    , SP5_PWRDN        , bidir        , X    ,   24     , 0     , Z   ),"&
    "  21   (LV_BC_7    , SP6_PWRDN        , bidir        , X    ,   24     , 0     , Z   ),"&
    "  20   (LV_BC_7    , SP7_PWRDN        , bidir        , X    ,   24     , 0     , Z   ),"&
    "  19   (BC_0       , *                , internal      , 0   )                          ,"&
    "  18   (BC_0    , *        , internal        , X ),"&
    "  17   (BC_0    , *        , internal        , X ),"&
    "  16   (BC_0    , *       , internal        , X ),"&
    "  15   (BC_0    , *       , internal        , X ),"&
    "  14   (BC_2       , *                , internal      , 0   )                          ,"&
    "  13   (BC_0    , *       , internal        , X ),"&
    "  12   (BC_0    , *       , internal        , X ),"&
    "  11   (BC_0    , *       , internal        , X ),"&
    "  10   (BC_0    , *       , internal        , X ),"&
    "  9    (LV_BC_7    , SP0_MODESEL      , bidir        , X    ,   28     , 0     , Z   ),"&
    "  8    (BC_2       , *                , control      , 0   )                          ,"&
    "  7    (LV_BC_7    , SP2_MODESEL      , bidir        , X    ,   8      , 0     , Z   ),"&
    "  6    (BC_2       , *                , control      , 0   )                          ,"&
    "  5    (LV_BC_7    , SP4_MODESEL      , bidir        , X    ,   6      , 0     , Z   ),"&
    "  4    (LV_BC_7    , SP6_MODESEL      , bidir        , X    ,   6      , 0     , Z   ),"&
    "  3    (BC_0    , *      , internal        , X ),"&
    "  2    (LV_BC_7    , TEST10_MODESEL     , bidir        , X    ,   6      , 0     , Z   ),"&
    "  1    (BC_2       , *                , control      , 0   )                          ,"&
    "  0    (LV_BC_7    , MCES             , bidir        , X    ,   1      , 0     , Z   ) ";

    attribute AIO_COMPONENT_CONFORMANCE of Tsi572: entity is "STD_1149_6_2003";


    attribute AIO_Pin_Behavior of Tsi572: entity is 
        "SP0_TD_P;"&
        "SP0_TC_P;"&
        "SP0_TB_P;"&
        "SP0_TA_P;"&
        "SP2_TB_P;"&
        "SP2_TA_P;"&
        "SP4_TB_P;"&
        "SP4_TA_P;"&
        "SP6_TD_P;"&
        "SP6_TC_P;"&
        "SP6_TB_P;"&
        "SP6_TA_P;"&
        "SP0_RB_P[113]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP0_RA_P[109]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP0_RC_P[105]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP0_RD_P[101]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP2_RB_P[97]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP2_RA_P[93]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP4_RB_P[81]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP4_RA_P[77]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RB_P[65]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RA_P[61]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RC_P[57]             : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RD_P[53]             : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi572;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO := 
--           ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
--           (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
--           (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
--
--end LVS_BSCAN_CELLS;
--