-------------------------------------------------------------------------------
-- TI 66AK2G02 Fixed & Floating Point DSP with Boundary Scan --
-------------------------------------------------------------------------------
-- Supported Devices: 66AK2G02 Revision 1.0 --
-------------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : 66AK2G02 Users Guide --
-- --
-- BSDL Revision : 1.4 match signal names to data manual (03/20/2016) --
-- BSDL Revision : 1.3 updated Warning section (01/16/2015) --
-- BSDL Revision : 1.2 updated to latest BGA package (10/30/2014) --
-- BSDL Revision : 1.1 updated to latest bscan chain (07/28/2014) --
-- BSDL Revision : 1.0 originally created (04/04/2014) --
-- --
-- BSDL Status : Preliminary --
-- Date Created : 04/04/2014 --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- --
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-- ------------------------------------------------------------------------- --
entity TI66AK2G02 is
generic(PHYSICAL_PIN_MAP : string := "ZBB");
port(
audosc_in : linkage bit;
audosc_out : linkage bit;
baw_resonator_m : linkage bit;
baw_resonator_p : linkage bit;
rsv7 : linkage bit;
rsv6 : linkage bit;
bootcomplete : inout bit;
cpts_refclk_n : in bit;
cpts_refclk_p : in bit;
dcan0_rx : inout bit;
dcan0_tx : inout bit;
ddr3_a00 : inout bit;
ddr3_a01 : inout bit;
ddr3_a02 : inout bit;
ddr3_a03 : inout bit;
ddr3_a04 : inout bit;
ddr3_a05 : inout bit;
ddr3_a06 : inout bit;
ddr3_a07 : inout bit;
ddr3_a08 : inout bit;
ddr3_a09 : inout bit;
ddr3_a10 : inout bit;
ddr3_a11 : inout bit;
ddr3_a12 : inout bit;
ddr3_a13 : inout bit;
ddr3_a14 : inout bit;
ddr3_a15 : inout bit;
rsv12 : linkage bit;
ddr3_ba0 : inout bit;
ddr3_ba1 : inout bit;
ddr3_ba2 : inout bit;
ddr3_rzq0 : linkage bit;
ddr3_rzq1 : linkage bit;
ddr3_casn : inout bit;
ddr3_cb00 : inout bit;
ddr3_cb01 : inout bit;
ddr3_cb02 : inout bit;
ddr3_cb03 : inout bit;
ddr3_cbdqm : inout bit;
ddr3_cbdqs_n : inout bit;
ddr3_cbdqs_p : inout bit;
ddr3_cen0 : inout bit;
ddr3_cen1 : inout bit;
ddr3_cke0 : inout bit;
ddr3_cke1 : inout bit;
ddr3_clkout_n0 : inout bit;
ddr3_clkout_n1 : inout bit;
ddr3_clkout_p0 : inout bit;
ddr3_clkout_p1 : inout bit;
ddr3_d00 : inout bit;
ddr3_d01 : inout bit;
ddr3_d02 : inout bit;
ddr3_d03 : inout bit;
ddr3_d04 : inout bit;
ddr3_d05 : inout bit;
ddr3_d06 : inout bit;
ddr3_d07 : inout bit;
ddr3_d08 : inout bit;
ddr3_d09 : inout bit;
ddr3_d10 : inout bit;
ddr3_d11 : inout bit;
ddr3_d12 : inout bit;
ddr3_d13 : inout bit;
ddr3_d14 : inout bit;
ddr3_d15 : inout bit;
ddr3_d16 : inout bit;
ddr3_d17 : inout bit;
ddr3_d18 : inout bit;
ddr3_d19 : inout bit;
ddr3_d20 : inout bit;
ddr3_d21 : inout bit;
ddr3_d22 : inout bit;
ddr3_d23 : inout bit;
ddr3_d24 : inout bit;
ddr3_d25 : inout bit;
ddr3_d26 : inout bit;
ddr3_d27 : inout bit;
ddr3_d28 : inout bit;
ddr3_d29 : inout bit;
ddr3_d30 : inout bit;
ddr3_d31 : inout bit;
ddr3_dqm0 : inout bit;
ddr3_dqm1 : inout bit;
ddr3_dqm2 : inout bit;
ddr3_dqm3 : inout bit;
ddr3_dqs0_n : inout bit;
ddr3_dqs0_p : inout bit;
ddr3_dqs1_n : inout bit;
ddr3_dqs1_p : inout bit;
ddr3_dqs2_n : inout bit;
ddr3_dqs2_p : inout bit;
ddr3_dqs3_n : inout bit;
ddr3_dqs3_p : inout bit;
rsv10 : inout bit;
rsv11 : inout bit;
ddr3_odt0 : inout bit;
ddr3_odt1 : inout bit;
ddr3_rasn : inout bit;
ddr3_resetn : inout bit;
ddr3_wen : inout bit;
ddr_clk_n : in bit;
ddr_clk_p : in bit;
dss_data0 : inout bit;
dss_data1 : inout bit;
dss_data10 : inout bit;
dss_data11 : inout bit;
dss_data12 : inout bit;
dss_data13 : inout bit;
dss_data14 : inout bit;
dss_data15 : inout bit;
dss_data16 : inout bit;
dss_data17 : inout bit;
dss_data18 : inout bit;
dss_data19 : inout bit;
dss_data2 : inout bit;
dss_data20 : inout bit;
dss_data21 : inout bit;
dss_data22 : inout bit;
dss_data23 : inout bit;
dss_data3 : inout bit;
dss_data4 : inout bit;
dss_data5 : inout bit;
dss_data6 : inout bit;
dss_data7 : inout bit;
dss_data8 : inout bit;
dss_data9 : inout bit;
dss_de : inout bit;
dss_fid : inout bit;
dss_hsync : inout bit;
dss_pclk : inout bit;
dss_vsync : inout bit;
emu00 : inout bit;
emu01 : inout bit;
spi3_scsn0 : inout bit;
mii_col : inout bit;
mii_crs : inout bit;
mii_rxclk : inout bit;
mii_rxd0 : inout bit;
mii_rxd1 : inout bit;
mii_rxd2 : inout bit;
mii_rxd3 : inout bit;
ehrpwm3_synco : inout bit;
ehrpwm3_synci : inout bit;
ehrpwm3_b : inout bit;
ehrpwm3_a : inout bit;
mii_rxdv : inout bit;
mii_rxer : inout bit;
mii_txclk : inout bit;
mii_txd0 : inout bit;
mii_txd1 : inout bit;
mii_txd2 : inout bit;
mii_txd3 : inout bit;
spi3_simo : inout bit;
spi3_somi : inout bit;
spi3_clk : inout bit;
spi3_scsn1 : inout bit;
mii_txen : inout bit;
mii_txer : inout bit;
gpmc_ad0 : inout bit;
gpmc_ad1 : inout bit;
gpmc_ad10 : inout bit;
gpmc_ad11 : inout bit;
gpmc_ad12 : inout bit;
gpmc_ad13 : inout bit;
gpmc_ad14 : inout bit;
gpmc_ad15 : inout bit;
gpmc_ad2 : inout bit;
gpmc_ad3 : inout bit;
gpmc_ad4 : inout bit;
gpmc_ad5 : inout bit;
gpmc_ad6 : inout bit;
gpmc_ad7 : inout bit;
gpmc_ad8 : inout bit;
gpmc_ad9 : inout bit;
gpmc_advn_ale : inout bit;
gpmc_ben0_cle : inout bit;
gpmc_ben1 : inout bit;
gpmc_clk : inout bit;
gpmc_csn0 : inout bit;
gpmc_csn1 : inout bit;
gpmc_csn2 : inout bit;
gpmc_csn3 : inout bit;
gpmc_dir : inout bit;
gpmc_oen_ren : inout bit;
gpmc_wait0 : inout bit;
gpmc_wait1 : inout bit;
gpmc_wen : inout bit;
gpmc_wpn : inout bit;
rsv1 : linkage bit;
lresetnmienn : inout bit;
lresetn : inout bit;
mdio_clk : inout bit;
mdio_data : inout bit;
mlbp_clk_n : in bit;
mlbp_clk_p : in bit;
mlbp_dat_n : inout bit;
mlbp_dat_p : inout bit;
mlbp_sig_n : inout bit;
mlbp_sig_p : inout bit;
mmc1_clk : inout bit;
mmc1_cmd : inout bit;
mmc1_dat0 : inout bit;
mmc1_dat1 : inout bit;
mmc1_dat2 : inout bit;
mmc1_dat3 : inout bit;
mmc1_dat4 : inout bit;
mmc1_dat5 : inout bit;
mmc1_dat6 : inout bit;
mmc1_dat7 : inout bit;
mmc1_pow : inout bit;
mmc1_sdcd : inout bit;
mmc1_sdwp : inout bit;
nmin : inout bit;
obsclk_n : buffer bit;
obsclk_p : buffer bit;
obspll_lock : inout bit;
pcie_clk_n : linkage bit;
pcie_clk_p : linkage bit;
rsv5 : linkage bit;
pcie_refres : linkage bit;
pcie_rxn0 : in bit;
pcie_rxp0 : in bit;
pcie_txn0 : buffer bit;
pcie_txp0 : buffer bit;
porn : in bit;
pr0_mdio_data : inout bit;
pr0_mdio_mdclk : inout bit;
pr0_pru0_gpo0 : inout bit;
pr0_pru0_gpo1 : inout bit;
pr0_pru0_gpo10 : inout bit;
pr0_pru0_gpo11 : inout bit;
pr0_pru0_gpo12 : inout bit;
pr0_pru0_gpo13 : inout bit;
pr0_pru0_gpo14 : inout bit;
pr0_pru0_gpo15 : inout bit;
pr0_pru0_gpo16 : inout bit;
pr0_pru0_gpo17 : inout bit;
pr0_pru0_gpo18 : inout bit;
pr0_pru0_gpo19 : inout bit;
pr0_pru0_gpo2 : inout bit;
pr0_pru0_gpo3 : inout bit;
pr0_pru0_gpo4 : inout bit;
pr0_pru0_gpo5 : inout bit;
pr0_pru0_gpo6 : inout bit;
pr0_pru0_gpo7 : inout bit;
pr0_pru0_gpo8 : inout bit;
pr0_pru0_gpo9 : inout bit;
pr0_pru1_gpo0 : inout bit;
pr0_pru1_gpo1 : inout bit;
pr0_pru1_gpo10 : inout bit;
pr0_pru1_gpo11 : inout bit;
pr0_pru1_gpo12 : inout bit;
pr0_pru1_gpo13 : inout bit;
pr0_pru1_gpo14 : inout bit;
pr0_pru1_gpo15 : inout bit;
pr0_pru1_gpo16 : inout bit;
pr0_pru1_gpo17 : inout bit;
pr0_pru1_gpo18 : inout bit;
pr0_pru1_gpo19 : inout bit;
pr0_pru1_gpo2 : inout bit;
pr0_pru1_gpo3 : inout bit;
pr0_pru1_gpo4 : inout bit;
pr0_pru1_gpo5 : inout bit;
pr0_pru1_gpo6 : inout bit;
pr0_pru1_gpo7 : inout bit;
pr0_pru1_gpo8 : inout bit;
pr0_pru1_gpo9 : inout bit;
pr1_mdio_data : inout bit;
pr1_mdio_mdclk : inout bit;
pr1_pru0_gpo0 : inout bit;
pr1_pru0_gpo1 : inout bit;
pr1_pru0_gpo10 : inout bit;
pr1_pru0_gpo11 : inout bit;
pr1_pru0_gpo12 : inout bit;
pr1_pru0_gpo13 : inout bit;
pr1_pru0_gpo14 : inout bit;
pr1_pru0_gpo15 : inout bit;
pr1_pru0_gpo16 : inout bit;
pr1_pru0_gpo17 : inout bit;
pr1_pru0_gpo18 : inout bit;
pr1_pru0_gpo19 : inout bit;
pr1_pru0_gpo2 : inout bit;
pr1_pru0_gpo3 : inout bit;
pr1_pru0_gpo4 : inout bit;
pr1_pru0_gpo5 : inout bit;
pr1_pru0_gpo6 : inout bit;
pr1_pru0_gpo7 : inout bit;
pr1_pru0_gpo8 : inout bit;
pr1_pru0_gpo9 : inout bit;
pr1_pru1_gpo0 : inout bit;
pr1_pru1_gpo1 : inout bit;
pr1_pru1_gpo10 : inout bit;
pr1_pru1_gpo11 : inout bit;
pr1_pru1_gpo12 : inout bit;
pr1_pru1_gpo13 : inout bit;
pr1_pru1_gpo14 : inout bit;
pr1_pru1_gpo15 : inout bit;
pr1_pru1_gpo16 : inout bit;
pr1_pru1_gpo17 : inout bit;
pr1_pru1_gpo18 : inout bit;
pr1_pru1_gpo19 : inout bit;
pr1_pru1_gpo2 : inout bit;
pr1_pru1_gpo3 : inout bit;
pr1_pru1_gpo4 : inout bit;
pr1_pru1_gpo5 : inout bit;
pr1_pru1_gpo6 : inout bit;
pr1_pru1_gpo7 : inout bit;
pr1_pru1_gpo8 : inout bit;
pr1_pru1_gpo9 : inout bit;
qspi_clk : inout bit;
qspi_csn0 : inout bit;
qspi_csn1 : inout bit;
qspi_csn2 : inout bit;
qspi_csn3 : inout bit;
qspi_d0 : inout bit;
qspi_d1 : inout bit;
qspi_d2 : inout bit;
qspi_d3 : inout bit;
qspi_rclk : inout bit;
resetfulln : in bit;
resetstatn : inout bit;
resetn : in bit;
rmii_refclk : inout bit;
i2c0_scl : inout bit;
i2c1_scl : inout bit;
i2c2_scl : inout bit;
i2c0_sda : inout bit;
i2c1_sda : inout bit;
i2c2_sda : inout bit;
spi0_clk : inout bit;
spi0_somi : inout bit;
spi0_simo : inout bit;
spi0_scsn0 : inout bit;
spi0_scsn1 : inout bit;
spi1_clk : inout bit;
spi1_somi : inout bit;
spi1_simo : inout bit;
spi1_scsn0 : inout bit;
spi1_scsn1 : inout bit;
spi2_clk : inout bit;
spi2_somi : inout bit;
spi2_simo : inout bit;
spi2_scsn0 : inout bit;
spi2_scsn1 : inout bit;
sysclk_n : in bit;
sysclkout : inout bit;
sysclk_p : in bit;
sysclksel : linkage bit;
sysosc_in : linkage bit;
sysosc_out : linkage bit;
tck : in bit;
tdi : in bit;
tdo : out bit;
rsv4 : linkage bit;
rsv3 : linkage bit;
tms : in bit;
trstn : in bit;
uart0_ctsn : inout bit;
uart0_rtsn : inout bit;
uart0_rxd : inout bit;
uart0_txd : inout bit;
uart1_ctsn : inout bit;
uart1_rtsn : inout bit;
uart1_rxd : inout bit;
uart1_txd : inout bit;
uart2_ctsn : inout bit;
uart2_rtsn : inout bit;
uart2_rxd : inout bit;
uart2_txd : inout bit;
usb0_dm : linkage bit;
usb0_dp : linkage bit;
usb0_drvvbus : inout bit;
usb0_id : linkage bit;
usb0_txrtune_rkelvin : linkage bit;
usb0_vbus : linkage bit;
usb0_xo : linkage bit;
usb1_dm : linkage bit;
usb1_dp : linkage bit;
usb1_drvvbus : inout bit;
usb1_id : linkage bit;
usb1_txrtune_rkelvin : linkage bit;
usb1_vbus : linkage bit;
usb1_xo : linkage bit;
rsv13 : inout bit;
rsv14 : inout bit;
rsv15 : inout bit;
rsv16 : inout bit;
rsv17 : inout bit;
rsv18 : inout bit;
rsv8 : linkage bit;
rsv9 : linkage bit;
rsv2 : linkage bit;
vpp : linkage bit;
vpp2 : linkage bit;
ddr3_vrefsstl : linkage bit;
vddahv : linkage bit;
dvdd33_usb : linkage bit_vector(1 to 2);
ldo_pcie_cap : linkage bit_vector(1 to 2);
ldo_usb_cap : linkage bit_vector(1 to 2);
dvdd_ddrdll : linkage bit_vector(1 to 3);
cvdd1 : linkage bit_vector(1 to 5);
dvdd18 : linkage bit_vector(1 to 13);
avdda_uartpll : linkage bit;
avdda_nsspll : linkage bit;
avdda_icsspll : linkage bit;
avdda_mainpll : linkage bit;
avdda_dsspll : linkage bit;
avdda_armpll : linkage bit;
avdda_ddrpll : linkage bit;
dvdd33 : linkage bit_vector(1 to 23);
dvdd_ddr : linkage bit_vector(1 to 16);
cvdd : linkage bit_vector(1 to 38);
vss_osc_sys : linkage bit;
vss_osc_audio : linkage bit;
vss : linkage bit_vector(1 to 118));
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
attribute COMPONENT_CONFORMANCE of TI66AK2G02 : entity is "STD_1149_1_2001";
attribute PIN_MAP of TI66AK2G02 : entity is PHYSICAL_PIN_MAP;
constant ZBB : PIN_MAP_STRING :=
"audosc_in : C17," &
"audosc_out : A17," &
"rsv7 : G3," &
"rsv6 : L2," &
"bootcomplete : Y3," &
"cpts_refclk_n : L21," &
"cpts_refclk_p : K21," &
"dcan0_rx : R5," &
"dcan0_tx : P5," &
"ddr3_a00 : AC15," &
"ddr3_a01 : Y15," &
"ddr3_a02 : AC16," &
"ddr3_a03 : AA15," &
"ddr3_a04 : AB16," &
"ddr3_a05 : AE17," &
"ddr3_a06 : AC14," &
"ddr3_a07 : AB15," &
"ddr3_a08 : AC17," &
"ddr3_a09 : AB17," &
"ddr3_a10 : AB14," &
"ddr3_a11 : AA16," &
"ddr3_a12 : AA17," &
"ddr3_a13 : AA12," &
"ddr3_a14 : Y17," &
"ddr3_a15 : Y16," &
"rsv12 : Y14," &
"ddr3_ba0 : AA14," &
"ddr3_ba1 : AB13," &
"ddr3_ba2 : AD17," &
"ddr3_casn : AC13," &
"ddr3_cb00 : AA11," &
"ddr3_cb01 : AB11," &
"ddr3_cb02 : AC11," &
"ddr3_cb03 : AC12," &
"ddr3_cbdqm : Y11," &
"ddr3_cbdqs_n : AD12," &
"ddr3_cbdqs_p : AE12," &
"ddr3_cen0 : AD13," &
"ddr3_cen1 : AB12," &
"ddr3_cke0 : AB18," &
"ddr3_cke1 : AC18," &
"ddr3_clkout_n0 : AD15," &
"ddr3_clkout_n1 : AD16," &
"ddr3_clkout_p0 : AE15," &
"ddr3_clkout_p1 : AE16," &
"ddr3_d00 : AD2," &
"ddr3_d01 : Y4," &
"ddr3_d02 : AC3," &
"ddr3_d03 : AC2," &
"ddr3_d04 : AE3," &
"ddr3_d05 : AA4," &
"ddr3_d06 : AD3," &
"ddr3_d07 : AB3," &
"ddr3_d08 : AA6," &
"ddr3_d09 : Y7," &
"ddr3_d10 : Y6," &
"ddr3_d11 : AC5," &
"ddr3_d12 : AB6," &
"ddr3_d13 : Y5," &
"ddr3_d14 : AC4," &
"ddr3_d15 : AB5," &
"ddr3_d16 : AB7," &
"ddr3_d17 : AB8," &
"ddr3_d18 : AC7," &
"ddr3_d19 : AA7," &
"ddr3_d20 : AA8," &
"ddr3_d21 : AC6," &
"ddr3_d22 : AE7," &
"ddr3_d23 : AD7," &
"ddr3_d24 : AA10," &
"ddr3_d25 : AE10," &
"ddr3_d26 : AD10," &
"ddr3_d27 : AC10," &
"ddr3_d28 : AC9," &
"ddr3_d29 : AB10," &
"ddr3_d30 : AB9," &
"ddr3_d31 : Y8," &
"ddr3_dqm0 : AB4," &
"ddr3_dqm1 : AA5," &
"ddr3_dqm2 : AC8," &
"ddr3_dqm3 : AA9," &
"ddr3_dqs0_n : AE2," &
"ddr3_dqs0_p : AD1," &
"ddr3_dqs1_n : AE4," &
"ddr3_dqs1_p : AD4," &
"ddr3_dqs2_n : AD6," &
"ddr3_dqs2_p : AE6," &
"ddr3_dqs3_n : AD9," &
"ddr3_dqs3_p : AE9," &
"rsv10 : AA18," &
"rsv11 : Y19," &
"ddr3_odt0 : AA13," &
"ddr3_odt1 : Y12," &
"ddr3_rasn : AE13," &
"ddr3_resetn : Y18," &
"ddr3_rzq0 : W12," &
"ddr3_rzq1 : V9," &
"ddr3_wen : Y13," &
"ddr_clk_n : AD24," &
"ddr_clk_p : AE24," &
"dss_data0 : V22," &
"dss_data1 : U21," &
"dss_data10 : U24," &
"dss_data11 : V25," &
"dss_data12 : T24," &
"dss_data13 : P21," &
"dss_data14 : U25," &
"dss_data15 : R22," &
"dss_data16 : P23," &
"dss_data17 : R24," &
"dss_data18 : N22," &
"dss_data19 : T25," &
"dss_data2 : W22," &
"dss_data20 : N24," &
"dss_data21 : P24," &
"dss_data22 : P25," &
"dss_data23 : N23," &
"dss_data3 : V23," &
"dss_data4 : U23," &
"dss_data5 : V24," &
"dss_data6 : T21," &
"dss_data7 : U22," &
"dss_data8 : T22," &
"dss_data9 : R21," &
"dss_de : M25," &
"dss_fid : L25," &
"dss_hsync : P22," &
"dss_pclk : N25," &
"dss_vsync : R25," &
"emu00 : M22," &
"emu01 : L22," &
"spi3_scsn0 : C24," &
"mii_col : B25," &
"mii_crs : G22," &
"mii_rxclk : A22," &
"mii_rxd0 : B24," &
"mii_rxd1 : C23," &
"mii_rxd2 : B23," &
"mii_rxd3 : F22," &
"ehrpwm3_synco : D23," &
"ehrpwm3_synci : C22," &
"ehrpwm3_b : B22," &
"ehrpwm3_a : A23," &
"mii_rxdv : A24," &
"mii_rxer : F23," &
"mii_txclk : C25," &
"mii_txd0 : G23," &
"mii_txd1 : G24," &
"mii_txd2 : G25," &
"mii_txd3 : D25," &
"spi3_simo : F24," &
"spi3_somi : F25," &
"spi3_clk : E24," &
"spi3_scsn1 : E25," &
"mii_txen : H25," &
"mii_txer : H24," &
"gpmc_ad0 : AC21," &
"gpmc_ad1 : AE20," &
"gpmc_ad10 : AA20," &
"gpmc_ad11 : AD23," &
"gpmc_ad12 : AA21," &
"gpmc_ad13 : AB21," &
"gpmc_ad14 : AB22," &
"gpmc_ad15 : AA22," &
"gpmc_ad2 : AD22," &
"gpmc_ad3 : AD20," &
"gpmc_ad4 : AE21," &
"gpmc_ad5 : AE22," &
"gpmc_ad6 : AC20," &
"gpmc_ad7 : AD21," &
"gpmc_ad8 : AE23," &
"gpmc_ad9 : AB20," &
"gpmc_advn_ale : AC23," &
"gpmc_ben0_cle : AC24," &
"gpmc_ben1 : AB24," &
"gpmc_clk : AB23," &
"gpmc_csn0 : AB25," &
"gpmc_csn1 : W24," &
"gpmc_csn2 : W23," &
"gpmc_csn3 : Y25," &
"gpmc_dir : AA25," &
"gpmc_oen_ren : AC22," &
"gpmc_wait0 : Y24," &
"gpmc_wait1 : AA24," &
"gpmc_wen : Y22," &
"gpmc_wpn : W25," &
"rsv1 : AA19," &
"lresetnmienn : V1," &
"lresetn : V2," &
"mdio_clk : U3," &
"mdio_data : V3," &
"mlbp_clk_n : L23," &
"mlbp_clk_p : M23," &
"mlbp_dat_n : K22," &
"mlbp_dat_p : K23," &
"mlbp_sig_n : M24," &
"mlbp_sig_p : L24," &
"mmc1_clk : J4," &
"mmc1_cmd : J2," &
"mmc1_dat0 : H3," &
"mmc1_dat1 : F5," &
"mmc1_dat2 : J5," &
"mmc1_dat3 : H4," &
"mmc1_dat4 : E3," &
"mmc1_dat5 : G4," &
"mmc1_dat6 : F4," &
"mmc1_dat7 : G5," &
"mmc1_pow : K2," &
"mmc1_sdcd : J3," &
"mmc1_sdwp : K3," &
"nmin : W1," &
"obsclk_n : L1," &
"obsclk_p : K1," &
"obspll_lock : N5," &
"rsv5 : D2," &
"pcie_clk_n : F2," &
"pcie_clk_p : G2," &
"rsv9 : H2," &
"pcie_refres : H7," &
"pcie_rxn0 : D1," &
"pcie_rxp0 : E1," &
"pcie_txn0 : H1," &
"pcie_txp0 : G1," &
"porn : AA3," &
"pr0_mdio_data : A10," &
"pr0_mdio_mdclk : C10," &
"pr0_pru0_gpo0 : D3," &
"pr0_pru0_gpo1 : A2," &
"pr0_pru0_gpo10 : C3," &
"pr0_pru0_gpo11 : D5," &
"pr0_pru0_gpo12 : B3," &
"pr0_pru0_gpo13 : B4," &
"pr0_pru0_gpo14 : A4," &
"pr0_pru0_gpo15 : E7," &
"pr0_pru0_gpo16 : D6," &
"pr0_pru0_gpo17 : C4," &
"pr0_pru0_gpo18 : C5," &
"pr0_pru0_gpo19 : A5," &
"pr0_pru0_gpo2 : E4," &
"pr0_pru0_gpo3 : B1," &
"pr0_pru0_gpo4 : A3," &
"pr0_pru0_gpo5 : E5," &
"pr0_pru0_gpo6 : B2," &
"pr0_pru0_gpo7 : D4," &
"pr0_pru0_gpo8 : E6," &
"pr0_pru0_gpo9 : C2," &
"pr0_pru1_gpo0 : B5," &
"pr0_pru1_gpo1 : B6," &
"pr0_pru1_gpo10 : C7," &
"pr0_pru1_gpo11 : E9," &
"pr0_pru1_gpo12 : A8," &
"pr0_pru1_gpo13 : B8," &
"pr0_pru1_gpo14 : D9," &
"pr0_pru1_gpo15 : C8," &
"pr0_pru1_gpo16 : C9," &
"pr0_pru1_gpo17 : B9," &
"pr0_pru1_gpo18 : A9," &
"pr0_pru1_gpo19 : B10," &
"pr0_pru1_gpo2 : D7," &
"pr0_pru1_gpo3 : A6," &
"pr0_pru1_gpo4 : C6," &
"pr0_pru1_gpo5 : E8," &
"pr0_pru1_gpo6 : A7," &
"pr0_pru1_gpo7 : D8," &
"pr0_pru1_gpo8 : F9," &
"pr0_pru1_gpo9 : B7," &
"pr1_mdio_data : E18," &
"pr1_mdio_mdclk : D18," &
"pr1_pru0_gpo0 : E10," &
"pr1_pru0_gpo1 : D10," &
"pr1_pru0_gpo10 : B12," &
"pr1_pru0_gpo11 : A12," &
"pr1_pru0_gpo12 : A11," &
"pr1_pru0_gpo13 : A13," &
"pr1_pru0_gpo14 : B13," &
"pr1_pru0_gpo15 : F13," &
"pr1_pru0_gpo16 : C13," &
"pr1_pru0_gpo17 : E13," &
"pr1_pru0_gpo18 : D12," &
"pr1_pru0_gpo19 : D13," &
"pr1_pru0_gpo2 : F10," &
"pr1_pru0_gpo3 : C11," &
"pr1_pru0_gpo4 : D11," &
"pr1_pru0_gpo5 : E11," &
"pr1_pru0_gpo6 : F12," &
"pr1_pru0_gpo7 : E12," &
"pr1_pru0_gpo8 : C12," &
"pr1_pru0_gpo9 : B11," &
"pr1_pru1_gpo0 : A14," &
"pr1_pru1_gpo1 : B14," &
"pr1_pru1_gpo10 : A16," &
"pr1_pru1_gpo11 : E15," &
"pr1_pru1_gpo12 : B16," &
"pr1_pru1_gpo13 : C16," &
"pr1_pru1_gpo14 : D17," &
"pr1_pru1_gpo15 : C18," &
"pr1_pru1_gpo16 : D16," &
"pr1_pru1_gpo17 : F16," &
"pr1_pru1_gpo18 : E17," &
"pr1_pru1_gpo19 : E16," &
"pr1_pru1_gpo2 : C14," &
"pr1_pru1_gpo3 : E14," &
"pr1_pru1_gpo4 : D14," &
"pr1_pru1_gpo5 : A15," &
"pr1_pru1_gpo6 : F14," &
"pr1_pru1_gpo7 : B15," &
"pr1_pru1_gpo8 : C15," &
"pr1_pru1_gpo9 : D15," &
"qspi_clk : K25," &
"qspi_csn0 : J25," &
"qspi_csn1 : H23," &
"qspi_csn2 : H22," &
"qspi_csn3 : H21," &
"qspi_d0 : J23," &
"qspi_d1 : J22," &
"qspi_d2 : J21," &
"qspi_d3 : J24," &
"qspi_rclk : K24," &
"resetfulln : W2," &
"resetstatn : Y2," &
"resetn : W3," &
"rmii_refclk : D24," &
"i2c0_scl : U5," &
"i2c1_scl : V6," &
"i2c2_scl : V5," &
"i2c0_sda : W5," &
"i2c1_sda : W4," &
"i2c2_sda : V4," &
"spi0_clk : M2," &
"spi0_somi : M1," &
"spi0_simo : N4," &
"spi0_scsn0 : M3," &
"spi0_scsn1 : M4," &
"spi1_clk : N2," &
"spi1_somi : N1," &
"spi1_simo : P2," &
"spi1_scsn0 : P1," &
"spi1_scsn1 : N3," &
"spi2_clk : R2," &
"spi2_somi : R4," &
"spi2_simo : R3," &
"spi2_scsn0 : P3," &
"spi2_scsn1 : P4," &
"sysclk_n : AC25," &
"sysclkout : M21," &
"sysclk_p : AD25," &
"sysclksel : R1," &
"sysosc_in : AC19," &
"sysosc_out : AE19," &
"tck : L3," &
"tdi : L5," &
"tdo : K5," &
"rsv4 : W19," &
"rsv3 : Y20," &
"tms : K4," &
"trstn : L4," &
"uart0_ctsn : T2," &
"uart0_rtsn : U1," &
"uart0_rxd : T4," &
"uart0_txd : T1," &
"uart1_ctsn : U2," &
"uart1_rtsn : U4," &
"uart1_rxd : T3," &
"uart1_txd : T5," &
"uart2_ctsn : D22," &
"uart2_rtsn : C21," &
"uart2_rxd : E21," &
"uart2_txd : D21," &
"usb0_dm : B18," &
"usb0_dp : A18," &
"usb0_drvvbus : E19," &
"usb0_id : A19," &
"usb0_txrtune_rkelvin : C19," &
"usb0_vbus : B19," &
"usb0_xo : D19," &
"usb1_dm : A20," &
"usb1_dp : B20," &
"usb1_drvvbus : B21," &
"usb1_id : E20," &
"usb1_txrtune_rkelvin : D20," &
"usb1_vbus : A21," &
"usb1_xo : C20," &
"rsv8 : F18," &
"rsv13 : Y1," &
"rsv14 : AA1," &
"rsv15 : AB1," &
"rsv16 : AA2," &
"rsv17 : AB2," &
"rsv18 : AC1," &
"rsv2 : AB19," &
"vpp : Y21," &
"vpp2 : W21," &
"ddr3_vrefsstl : Y9," &
"vddahv : K7," &
"dvdd33_usb : (H17, G18)," &
"ldo_pcie_cap : (J8, L8)," &
"ldo_usb_cap : (H19, J18)," &
"dvdd_ddrdll : (W8, W10, W14)," &
"cvdd1 : (T13, N8, N18, J12, M5)," &
"dvdd18 : (U18, V19, U6, W6, J6, L6, M7, K19, L20, F17, G6, F19, H5)," &
"avdda_uartpll : G10," &
"avdda_nsspll : G14," &
"avdda_icsspll : G8," &
"avdda_mainpll : M19," &
"avdda_dsspll : N20," &
"avdda_armpll : N6," &
"avdda_ddrpll : W20," &
"dvdd33 : (E23, F21, G20, J20, AA23, P19, R20, T19, T23, U20, V21, F7, H9, F11, F15, G12, G16, H11," &
"H13, H15, P7, R6, T7)," &
"dvdd_ddr : (U8, V7, AD11, AD18, AD5, AE14, AE8, U10, U12, U14, V11, V13, V15, V17, W16, W18)," &
"cvdd : (K9, M9, P9, R8, T9, J10, J14, J16, K11, K13, K15, K17, L10, L12, L14, L16, L18, M11, M13, M15," &
"M17, N10, N12, N14, N16, P11, P13, P15, P17, R10, R12, R14, R16, R18, T11, T15, T17, U16)," &
"vss_osc_sys : AD19," &
"vss_osc_audio : B17," &
"vss : (A1, C1, E2, F1, F3, F6, F8, G7, G9, H6, H8, J1, J7, J9, K6, K8, L7, L9, M6, M8, N7, N9," &
"P6, P8, R7, R9, T6, T8, U7, U9, V8, W7, W9, A25, AD14, AD8, AE1, AE11, AE18, AE25, AE5," &
"E22, F20, G11, G13, G15, G17, G19, G21, H10, H12, H14, H16, H18, H20, J11, J13, J15, J17," &
"J19, K10, K12, K14, K16, K18, K20, L11, L13, L15, L17, L19, M10, M12, M14, M16, M18, M20," &
"N11, N13, N15, N17, N19, N21, P10, P12, P14, P16, P18, P20, R11, R13, R15, R17, R19, R23," &
"T10, T12, T14, T16, T18, T20, U11, U13, U15, U17, U19, V10, V12, V14, V16, V18, V20, W11," &
"W13, W15, W17, Y10, Y23)";
attribute PORT_GROUPING of TI66AK2G02 : entity is
"Differential_Voltage ( "&
"(ddr_clk_p, ddr_clk_n), "&
"(obsclk_p, obsclk_n), "&
"(pcie_txp0, pcie_txn0), "&
"(sysclk_p, sysclk_n), "&
"(mlbp_clk_p, mlbp_clk_n), "&
"(mlbp_dat_p, mlbp_dat_n), "&
"(mlbp_sig_p, mlbp_sig_n), "&
"(cpts_refclk_p, cpts_refclk_n)) ";
attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute TAP_SCAN_CLOCK of tck : signal is (20.0e6,BOTH);
attribute TAP_SCAN_RESET of trstn : signal is true;
attribute COMPLIANCE_PATTERNS of TI66AK2G02 : entity is "(porn, resetfulln, resetn)(111)";
attribute INSTRUCTION_LENGTH of TI66AK2G02 : entity is 6;
attribute INSTRUCTION_OPCODE of TI66AK2G02 : entity is
"private_0 (000010), "&
"IDCODE (000100), "&
"private_1 (000101), "&
"private_2 (000111), "&
"private_3 (001000), "&
"private_4 (010111), "&
"EXTEST (011000), "&
"private_5 (011001), "&
"private_6 (011010), "&
"SAMPLE (011011), "&
"PRELOAD (011100), "&
"private_7 (011101), "&
"private_8 (011110), "&
"private_9 (011111), "&
"EXTEST_PULSE (100100), "&
"EXTEST_TRAIN (100101), "&
"private_a (110001), "&
"BYPASS (000000,111111)";
attribute INSTRUCTION_CAPTURE of TI66AK2G02 : entity is "000001";
attribute INSTRUCTION_PRIVATE of TI66AK2G02 : entity is
"private_0, " &
"private_1, " &
"private_2, " &
"private_3, " &
"private_4, " &
"private_5, " &
"private_6, " &
"private_7, " &
"private_8, " &
"private_9, " &
"EXTEST_PULSE, " &
"EXTEST_TRAIN, " &
"private_a";
attribute IDCODE_REGISTER of TI66AK2G02 : entity is
"0000" &
"1011101100000110" &
"00000010111" &
"1";
attribute REGISTER_ACCESS of TI66AK2G02 : entity is
"BOUNDARY (EXTEST), "&
"BOUNDARY (SAMPLE), "&
"BOUNDARY (PRELOAD), "&
"DEVICE_ID (IDCODE), "&
"GEN_REG1[1] (private_0), "&
"GEN_REG32[32] (private_1), "&
"GEN_REG8[8] (private_2), "&
"GEN_REG32[32] (private_3), "&
"GEN_REG1[1] (private_4), "&
"GEN_REG1[1] (private_5), "&
"GEN_REG1[1] (private_6), "&
"GEN_REG1[1] (private_7), "&
"GEN_REG1[1] (private_8), "&
"GEN_REG1[1] (private_9), "&
"BOUNDARY (EXTEST_PULSE), "&
"BOUNDARY (EXTEST_TRAIN), "&
"GEN_REG1[1] (private_a), "&
"BYPASS (BYPASS) ";
attribute BOUNDARY_LENGTH of TI66AK2G02 : entity is 689;
attribute BOUNDARY_REGISTER of TI66AK2G02 : entity is
" 688 (AC_SELU, * , internal , 0 ),"&
" 687 (AC_1, pcie_txp0 , output2 , X ),"&
" 686 (BC_4, pcie_rxn0 , observe_only , X ),"&
" 685 (BC_4, pcie_rxp0 , observe_only , X ),"&
" 684 (BC_7, obspll_lock , bidir , X, 683, 1, PULL0 ),"&
" 683 (BC_2, * , control , 1 ),"&
" 682 (BC_1, obsclk_p , output2 , X ),"&
" 681 (BC_7, mmc1_pow , bidir , X, 680, 1, PULL1 ),"&
" 680 (BC_2, * , control , 1 ),"&
" 679 (BC_7, mmc1_sdwp , bidir , X, 678, 1, PULL1 ),"&
" 678 (BC_2, * , control , 1 ),"&
" 677 (BC_7, mmc1_sdcd , bidir , X, 676, 1, PULL1 ),"&
" 676 (BC_2, * , control , 1 ),"&
" 675 (BC_7, mmc1_cmd , bidir , X, 674, 1, PULL1 ),"&
" 674 (BC_2, * , control , 1 ),"&
" 673 (BC_7, mmc1_clk , bidir , X, 672, 1, PULL1 ),"&
" 672 (BC_2, * , control , 1 ),"&
" 671 (BC_7, mmc1_dat0 , bidir , X, 670, 1, PULL1 ),"&
" 670 (BC_2, * , control , 1 ),"&
" 669 (BC_7, mmc1_dat1 , bidir , X, 668, 1, PULL1 ),"&
" 668 (BC_2, * , control , 1 ),"&
" 667 (BC_7, mmc1_dat2 , bidir , X, 666, 1, PULL1 ),"&
" 666 (BC_2, * , control , 1 ),"&
" 665 (BC_7, mmc1_dat3 , bidir , X, 664, 1, PULL1 ),"&
" 664 (BC_2, * , control , 1 ),"&
" 663 (BC_7, mmc1_dat4 , bidir , X, 662, 1, PULL1 ),"&
" 662 (BC_2, * , control , 1 ),"&
" 661 (BC_7, mmc1_dat5 , bidir , X, 660, 1, PULL1 ),"&
" 660 (BC_2, * , control , 1 ),"&
" 659 (BC_7, mmc1_dat6 , bidir , X, 658, 1, PULL1 ),"&
" 658 (BC_2, * , control , 1 ),"&
" 657 (BC_7, mmc1_dat7 , bidir , X, 656, 1, PULL1 ),"&
" 656 (BC_2, * , control , 1 ),"&
" 655 (BC_7, pr0_pru0_gpo0 , bidir , X, 654, 1, PULL0 ),"&
" 654 (BC_2, * , control , 1 ),"&
" 653 (BC_7, pr0_pru0_gpo1 , bidir , X, 652, 1, PULL0 ),"&
" 652 (BC_2, * , control , 1 ),"&
" 651 (BC_7, pr0_pru0_gpo2 , bidir , X, 650, 1, PULL0 ),"&
" 650 (BC_2, * , control , 1 ),"&
" 649 (BC_7, pr0_pru0_gpo3 , bidir , X, 648, 1, PULL0 ),"&
" 648 (BC_2, * , control , 1 ),"&
" 647 (BC_7, pr0_pru0_gpo4 , bidir , X, 646, 1, PULL0 ),"&
" 646 (BC_2, * , control , 1 ),"&
" 645 (BC_7, pr0_pru0_gpo5 , bidir , X, 644, 1, PULL0 ),"&
" 644 (BC_2, * , control , 1 ),"&
" 643 (BC_7, pr0_pru0_gpo6 , bidir , X, 642, 1, PULL0 ),"&
" 642 (BC_2, * , control , 1 ),"&
" 641 (BC_7, pr0_pru0_gpo7 , bidir , X, 640, 1, PULL0 ),"&
" 640 (BC_2, * , control , 1 ),"&
" 639 (BC_7, pr0_pru0_gpo8 , bidir , X, 638, 1, PULL0 ),"&
" 638 (BC_2, * , control , 1 ),"&
" 637 (BC_7, pr0_pru0_gpo9 , bidir , X, 636, 1, PULL0 ),"&
" 636 (BC_2, * , control , 1 ),"&
" 635 (BC_7, pr0_pru0_gpo10 , bidir , X, 634, 1, PULL0 ),"&
" 634 (BC_2, * , control , 1 ),"&
" 633 (BC_7, pr0_pru0_gpo11 , bidir , X, 632, 1, PULL0 ),"&
" 632 (BC_2, * , control , 1 ),"&
" 631 (BC_7, pr0_pru0_gpo12 , bidir , X, 630, 1, PULL0 ),"&
" 630 (BC_2, * , control , 1 ),"&
" 629 (BC_7, pr0_pru0_gpo13 , bidir , X, 628, 1, PULL0 ),"&
" 628 (BC_2, * , control , 1 ),"&
" 627 (BC_7, pr0_pru0_gpo14 , bidir , X, 626, 1, PULL0 ),"&
" 626 (BC_2, * , control , 1 ),"&
" 625 (BC_7, pr0_pru0_gpo15 , bidir , X, 624, 1, PULL0 ),"&
" 624 (BC_2, * , control , 1 ),"&
" 623 (BC_7, pr0_pru0_gpo16 , bidir , X, 622, 1, PULL0 ),"&
" 622 (BC_2, * , control , 1 ),"&
" 621 (BC_7, pr0_pru0_gpo17 , bidir , X, 620, 1, PULL0 ),"&
" 620 (BC_2, * , control , 1 ),"&
" 619 (BC_7, pr0_pru0_gpo18 , bidir , X, 618, 1, PULL0 ),"&
" 618 (BC_2, * , control , 1 ),"&
" 617 (BC_7, pr0_pru0_gpo19 , bidir , X, 616, 1, PULL0 ),"&
" 616 (BC_2, * , control , 1 ),"&
" 615 (BC_7, pr0_pru1_gpo0 , bidir , X, 614, 1, PULL0 ),"&
" 614 (BC_2, * , control , 1 ),"&
" 613 (BC_7, pr0_pru1_gpo1 , bidir , X, 612, 1, PULL0 ),"&
" 612 (BC_2, * , control , 1 ),"&
" 611 (BC_7, pr0_pru1_gpo2 , bidir , X, 610, 1, PULL0 ),"&
" 610 (BC_2, * , control , 1 ),"&
" 609 (BC_7, pr0_pru1_gpo3 , bidir , X, 608, 1, PULL0 ),"&
" 608 (BC_2, * , control , 1 ),"&
" 607 (BC_7, pr0_pru1_gpo4 , bidir , X, 606, 1, PULL0 ),"&
" 606 (BC_2, * , control , 1 ),"&
" 605 (BC_7, pr0_pru1_gpo5 , bidir , X, 604, 1, PULL0 ),"&
" 604 (BC_2, * , control , 1 ),"&
" 603 (BC_7, pr0_pru1_gpo6 , bidir , X, 602, 1, PULL0 ),"&
" 602 (BC_2, * , control , 1 ),"&
" 601 (BC_7, pr0_pru1_gpo7 , bidir , X, 600, 1, PULL0 ),"&
" 600 (BC_2, * , control , 1 ),"&
" 599 (BC_7, pr0_pru1_gpo8 , bidir , X, 598, 1, PULL0 ),"&
" 598 (BC_2, * , control , 1 ),"&
" 597 (BC_7, pr0_pru1_gpo9 , bidir , X, 596, 1, PULL0 ),"&
" 596 (BC_2, * , control , 1 ),"&
" 595 (BC_7, pr0_pru1_gpo10 , bidir , X, 594, 1, PULL0 ),"&
" 594 (BC_2, * , control , 1 ),"&
" 593 (BC_7, pr0_pru1_gpo11 , bidir , X, 592, 1, PULL0 ),"&
" 592 (BC_2, * , control , 1 ),"&
" 591 (BC_7, pr0_pru1_gpo12 , bidir , X, 590, 1, PULL0 ),"&
" 590 (BC_2, * , control , 1 ),"&
" 589 (BC_7, pr0_pru1_gpo13 , bidir , X, 588, 1, PULL0 ),"&
" 588 (BC_2, * , control , 1 ),"&
" 587 (BC_7, pr0_pru1_gpo14 , bidir , X, 586, 1, PULL0 ),"&
" 586 (BC_2, * , control , 1 ),"&
" 585 (BC_7, pr0_pru1_gpo15 , bidir , X, 584, 1, PULL0 ),"&
" 584 (BC_2, * , control , 1 ),"&
" 583 (BC_7, pr0_pru1_gpo16 , bidir , X, 582, 1, PULL0 ),"&
" 582 (BC_2, * , control , 1 ),"&
" 581 (BC_7, pr0_pru1_gpo17 , bidir , X, 580, 1, PULL0 ),"&
" 580 (BC_2, * , control , 1 ),"&
" 579 (BC_7, pr0_pru1_gpo18 , bidir , X, 578, 1, PULL0 ),"&
" 578 (BC_2, * , control , 1 ),"&
" 577 (BC_7, pr0_pru1_gpo19 , bidir , X, 576, 1, PULL0 ),"&
" 576 (BC_2, * , control , 1 ),"&
" 575 (BC_7, pr0_mdio_mdclk , bidir , X, 574, 1, PULL0 ),"&
" 574 (BC_2, * , control , 1 ),"&
" 573 (BC_7, pr0_mdio_data , bidir , X, 572, 1, PULL0 ),"&
" 572 (BC_2, * , control , 1 ),"&
" 571 (BC_7, pr1_pru0_gpo0 , bidir , X, 570, 1, PULL0 ),"&
" 570 (BC_2, * , control , 1 ),"&
" 569 (BC_7, pr1_pru0_gpo1 , bidir , X, 568, 1, PULL0 ),"&
" 568 (BC_2, * , control , 1 ),"&
" 567 (BC_7, pr1_pru0_gpo2 , bidir , X, 566, 1, PULL0 ),"&
" 566 (BC_2, * , control , 1 ),"&
" 565 (BC_7, pr1_pru0_gpo3 , bidir , X, 564, 1, PULL0 ),"&
" 564 (BC_2, * , control , 1 ),"&
" 563 (BC_7, pr1_pru0_gpo4 , bidir , X, 562, 1, PULL0 ),"&
" 562 (BC_2, * , control , 1 ),"&
" 561 (BC_7, pr1_pru0_gpo5 , bidir , X, 560, 1, PULL0 ),"&
" 560 (BC_2, * , control , 1 ),"&
" 559 (BC_7, pr1_pru0_gpo6 , bidir , X, 558, 1, PULL0 ),"&
" 558 (BC_2, * , control , 1 ),"&
" 557 (BC_7, pr1_pru0_gpo7 , bidir , X, 556, 1, PULL0 ),"&
" 556 (BC_2, * , control , 1 ),"&
" 555 (BC_7, pr1_pru0_gpo8 , bidir , X, 554, 1, PULL0 ),"&
" 554 (BC_2, * , control , 1 ),"&
" 553 (BC_7, pr1_pru0_gpo9 , bidir , X, 552, 1, PULL0 ),"&
" 552 (BC_2, * , control , 1 ),"&
" 551 (BC_7, pr1_pru0_gpo10 , bidir , X, 550, 1, PULL0 ),"&
" 550 (BC_2, * , control , 1 ),"&
" 549 (BC_7, pr1_pru0_gpo11 , bidir , X, 548, 1, PULL0 ),"&
" 548 (BC_2, * , control , 1 ),"&
" 547 (BC_7, pr1_pru0_gpo12 , bidir , X, 546, 1, PULL0 ),"&
" 546 (BC_2, * , control , 1 ),"&
" 545 (BC_7, pr1_pru0_gpo13 , bidir , X, 544, 1, PULL0 ),"&
" 544 (BC_2, * , control , 1 ),"&
" 543 (BC_7, pr1_pru0_gpo14 , bidir , X, 542, 1, PULL0 ),"&
" 542 (BC_2, * , control , 1 ),"&
" 541 (BC_7, pr1_pru0_gpo15 , bidir , X, 540, 1, PULL0 ),"&
" 540 (BC_2, * , control , 1 ),"&
" 539 (BC_7, pr1_pru0_gpo16 , bidir , X, 538, 1, PULL0 ),"&
" 538 (BC_2, * , control , 1 ),"&
" 537 (BC_7, pr1_pru0_gpo17 , bidir , X, 536, 1, PULL0 ),"&
" 536 (BC_2, * , control , 1 ),"&
" 535 (BC_7, pr1_pru0_gpo18 , bidir , X, 534, 1, PULL0 ),"&
" 534 (BC_2, * , control , 1 ),"&
" 533 (BC_7, pr1_pru0_gpo19 , bidir , X, 532, 1, PULL0 ),"&
" 532 (BC_2, * , control , 1 ),"&
" 531 (BC_7, pr1_pru1_gpo0 , bidir , X, 530, 1, PULL0 ),"&
" 530 (BC_2, * , control , 1 ),"&
" 529 (BC_7, pr1_pru1_gpo1 , bidir , X, 528, 1, PULL0 ),"&
" 528 (BC_2, * , control , 1 ),"&
" 527 (BC_7, pr1_pru1_gpo2 , bidir , X, 526, 1, PULL0 ),"&
" 526 (BC_2, * , control , 1 ),"&
" 525 (BC_7, pr1_pru1_gpo3 , bidir , X, 524, 1, PULL0 ),"&
" 524 (BC_2, * , control , 1 ),"&
" 523 (BC_7, pr1_pru1_gpo4 , bidir , X, 522, 1, PULL0 ),"&
" 522 (BC_2, * , control , 1 ),"&
" 521 (BC_7, pr1_pru1_gpo5 , bidir , X, 520, 1, PULL0 ),"&
" 520 (BC_2, * , control , 1 ),"&
" 519 (BC_7, pr1_pru1_gpo6 , bidir , X, 518, 1, PULL0 ),"&
" 518 (BC_2, * , control , 1 ),"&
" 517 (BC_7, pr1_pru1_gpo7 , bidir , X, 516, 1, PULL0 ),"&
" 516 (BC_2, * , control , 1 ),"&
" 515 (BC_7, pr1_pru1_gpo8 , bidir , X, 514, 1, PULL0 ),"&
" 514 (BC_2, * , control , 1 ),"&
" 513 (BC_7, pr1_pru1_gpo9 , bidir , X, 512, 1, PULL0 ),"&
" 512 (BC_2, * , control , 1 ),"&
" 511 (BC_7, pr1_pru1_gpo10 , bidir , X, 510, 1, PULL0 ),"&
" 510 (BC_2, * , control , 1 ),"&
" 509 (BC_7, pr1_pru1_gpo11 , bidir , X, 508, 1, PULL0 ),"&
" 508 (BC_2, * , control , 1 ),"&
" 507 (BC_7, pr1_pru1_gpo12 , bidir , X, 506, 1, PULL0 ),"&
" 506 (BC_2, * , control , 1 ),"&
" 505 (BC_7, pr1_pru1_gpo13 , bidir , X, 504, 1, PULL0 ),"&
" 504 (BC_2, * , control , 1 ),"&
" 503 (BC_7, pr1_pru1_gpo14 , bidir , X, 502, 1, PULL0 ),"&
" 502 (BC_2, * , control , 1 ),"&
" 501 (BC_7, pr1_pru1_gpo15 , bidir , X, 500, 1, PULL0 ),"&
" 500 (BC_2, * , control , 1 ),"&
" 499 (BC_7, pr1_pru1_gpo16 , bidir , X, 498, 1, PULL0 ),"&
" 498 (BC_2, * , control , 1 ),"&
" 497 (BC_7, pr1_pru1_gpo17 , bidir , X, 496, 1, PULL0 ),"&
" 496 (BC_2, * , control , 1 ),"&
" 495 (BC_7, pr1_pru1_gpo18 , bidir , X, 494, 1, PULL0 ),"&
" 494 (BC_2, * , control , 1 ),"&
" 493 (BC_7, pr1_pru1_gpo19 , bidir , X, 492, 1, PULL0 ),"&
" 492 (BC_2, * , control , 1 ),"&
" 491 (BC_7, pr1_mdio_mdclk , bidir , X, 490, 1, PULL0 ),"&
" 490 (BC_2, * , control , 1 ),"&
" 489 (BC_7, pr1_mdio_data , bidir , X, 488, 1, PULL0 ),"&
" 488 (BC_2, * , control , 1 ),"&
" 487 (BC_7, usb1_drvvbus , bidir , X, 486, 1, PULL0 ),"&
" 486 (BC_2, * , control , 1 ),"&
" 485 (BC_7, usb0_drvvbus , bidir , X, 484, 1, PULL0 ),"&
" 484 (BC_2, * , control , 1 ),"&
" 483 (BC_7, uart2_rtsn , bidir , X, 482, 1, PULL1 ),"&
" 482 (BC_2, * , control , 1 ),"&
" 481 (BC_7, uart2_ctsn , bidir , X, 480, 1, PULL1 ),"&
" 480 (BC_2, * , control , 1 ),"&
" 479 (BC_7, uart2_txd , bidir , X, 478, 1, PULL1 ),"&
" 478 (BC_2, * , control , 1 ),"&
" 477 (BC_7, uart2_rxd , bidir , X, 476, 1, PULL1 ),"&
" 476 (BC_2, * , control , 1 ),"&
" 475 (BC_7, mii_rxclk , bidir , X, 474, 1, PULL0 ),"&
" 474 (BC_2, * , control , 1 ),"&
" 473 (BC_7, ehrpwm3_a , bidir , X, 472, 1, PULL0 ),"&
" 472 (BC_2, * , control , 1 ),"&
" 471 (BC_7, ehrpwm3_b , bidir , X, 470, 1, PULL0 ),"&
" 470 (BC_2, * , control , 1 ),"&
" 469 (BC_7, ehrpwm3_synci , bidir , X, 468, 1, PULL0 ),"&
" 468 (BC_2, * , control , 1 ),"&
" 467 (BC_7, ehrpwm3_synco , bidir , X, 466, 1, PULL0 ),"&
" 466 (BC_2, * , control , 1 ),"&
" 465 (BC_7, mii_rxd3 , bidir , X, 464, 1, PULL0 ),"&
" 464 (BC_2, * , control , 1 ),"&
" 463 (BC_7, mii_rxd2 , bidir , X, 462, 1, PULL0 ),"&
" 462 (BC_2, * , control , 1 ),"&
" 461 (BC_7, mii_rxd1 , bidir , X, 460, 1, PULL0 ),"&
" 460 (BC_2, * , control , 1 ),"&
" 459 (BC_7, mii_rxd0 , bidir , X, 458, 1, PULL0 ),"&
" 458 (BC_2, * , control , 1 ),"&
" 457 (BC_7, mii_rxdv , bidir , X, 456, 1, PULL0 ),"&
" 456 (BC_2, * , control , 1 ),"&
" 455 (BC_7, mii_rxer , bidir , X, 454, 1, PULL0 ),"&
" 454 (BC_2, * , control , 1 ),"&
" 453 (BC_7, mii_col , bidir , X, 452, 1, PULL0 ),"&
" 452 (BC_2, * , control , 1 ),"&
" 451 (BC_7, mii_crs , bidir , X, 450, 1, PULL0 ),"&
" 450 (BC_2, * , control , 1 ),"&
" 449 (BC_7, mii_txclk , bidir , X, 448, 1, PULL0 ),"&
" 448 (BC_2, * , control , 1 ),"&
" 447 (BC_7, spi3_scsn0 , bidir , X, 446, 1, PULL0 ),"&
" 446 (BC_2, * , control , 1 ),"&
" 445 (BC_7, spi3_scsn1 , bidir , X, 444, 1, PULL0 ),"&
" 444 (BC_2, * , control , 1 ),"&
" 443 (BC_7, spi3_clk , bidir , X, 442, 1, PULL0 ),"&
" 442 (BC_2, * , control , 1 ),"&
" 441 (BC_7, spi3_somi , bidir , X, 440, 1, PULL0 ),"&
" 440 (BC_2, * , control , 1 ),"&
" 439 (BC_7, spi3_simo , bidir , X, 438, 1, PULL0 ),"&
" 438 (BC_2, * , control , 1 ),"&
" 437 (BC_7, mii_txd3 , bidir , X, 436, 1, PULL0 ),"&
" 436 (BC_2, * , control , 1 ),"&
" 435 (BC_7, mii_txd2 , bidir , X, 434, 1, PULL0 ),"&
" 434 (BC_2, * , control , 1 ),"&
" 433 (BC_7, mii_txd1 , bidir , X, 432, 1, PULL0 ),"&
" 432 (BC_2, * , control , 1 ),"&
" 431 (BC_7, mii_txd0 , bidir , X, 430, 1, PULL0 ),"&
" 430 (BC_2, * , control , 1 ),"&
" 429 (BC_7, mii_txen , bidir , X, 428, 1, PULL0 ),"&
" 428 (BC_2, * , control , 1 ),"&
" 427 (BC_7, mii_txer , bidir , X, 426, 1, PULL0 ),"&
" 426 (BC_2, * , control , 1 ),"&
" 425 (BC_7, rmii_refclk , bidir , X, 424, 1, PULL0 ),"&
" 424 (BC_2, * , control , 1 ),"&
" 423 (BC_7, qspi_csn3 , bidir , X, 422, 1, PULL1 ),"&
" 422 (BC_2, * , control , 1 ),"&
" 421 (BC_7, qspi_csn2 , bidir , X, 420, 1, PULL1 ),"&
" 420 (BC_2, * , control , 1 ),"&
" 419 (BC_7, qspi_csn1 , bidir , X, 418, 1, PULL1 ),"&
" 418 (BC_2, * , control , 1 ),"&
" 417 (BC_7, qspi_csn0 , bidir , X, 416, 1, PULL1 ),"&
" 416 (BC_2, * , control , 1 ),"&
" 415 (BC_7, qspi_d3 , bidir , X, 414, 1, PULL1 ),"&
" 414 (BC_2, * , control , 1 ),"&
" 413 (BC_7, qspi_d2 , bidir , X, 412, 1, PULL1 ),"&
" 412 (BC_2, * , control , 1 ),"&
" 411 (BC_7, qspi_d1 , bidir , X, 410, 1, PULL1 ),"&
" 410 (BC_2, * , control , 1 ),"&
" 409 (BC_7, qspi_d0 , bidir , X, 408, 1, PULL1 ),"&
" 408 (BC_2, * , control , 1 ),"&
" 407 (BC_7, qspi_rclk , bidir , X, 406, 1, PULL1 ),"&
" 406 (BC_2, * , control , 1 ),"&
" 405 (BC_7, qspi_clk , bidir , X, 404, 1, PULL1 ),"&
" 404 (BC_2, * , control , 1 ),"&
" 403 (BC_7, emu01 , bidir , X, 402, 1, PULL1 ),"&
" 402 (BC_2, * , control , 1 ),"&
" 401 (BC_7, mlbp_dat_p , bidir , X, 400, 1, Z ),"&
" 400 (BC_2, * , control , 1 ),"&
" 399 (BC_1, mlbp_clk_p , input , X ),"&
" 398 (BC_7, mlbp_sig_p , bidir , X, 397, 1, Z ),"&
" 397 (BC_2, * , control , 1 ),"&
" 396 (BC_1, cpts_refclk_p , input , X ),"&
" 395 (BC_7, sysclkout , bidir , X, 394, 1, PULL0 ),"&
" 394 (BC_2, * , control , 1 ),"&
" 393 (BC_7, emu00 , bidir , X, 392, 1, PULL1 ),"&
" 392 (BC_2, * , control , 1 ),"&
" 391 (BC_7, dss_pclk , bidir , X, 390, 1, PULL0 ),"&
" 390 (BC_2, * , control , 1 ),"&
" 389 (BC_7, dss_fid , bidir , X, 388, 1, PULL0 ),"&
" 388 (BC_2, * , control , 1 ),"&
" 387 (BC_7, dss_de , bidir , X, 386, 1, PULL0 ),"&
" 386 (BC_2, * , control , 1 ),"&
" 385 (BC_7, dss_hsync , bidir , X, 384, 1, PULL0 ),"&
" 384 (BC_2, * , control , 1 ),"&
" 383 (BC_7, dss_vsync , bidir , X, 382, 1, PULL0 ),"&
" 382 (BC_2, * , control , 1 ),"&
" 381 (BC_7, dss_data23 , bidir , X, 380, 1, PULL0 ),"&
" 380 (BC_2, * , control , 1 ),"&
" 379 (BC_7, dss_data22 , bidir , X, 378, 1, PULL0 ),"&
" 378 (BC_2, * , control , 1 ),"&
" 377 (BC_7, dss_data21 , bidir , X, 376, 1, PULL0 ),"&
" 376 (BC_2, * , control , 1 ),"&
" 375 (BC_7, dss_data20 , bidir , X, 374, 1, PULL0 ),"&
" 374 (BC_2, * , control , 1 ),"&
" 373 (BC_7, dss_data19 , bidir , X, 372, 1, PULL0 ),"&
" 372 (BC_2, * , control , 1 ),"&
" 371 (BC_7, dss_data18 , bidir , X, 370, 1, PULL0 ),"&
" 370 (BC_2, * , control , 1 ),"&
" 369 (BC_7, dss_data17 , bidir , X, 368, 1, PULL0 ),"&
" 368 (BC_2, * , control , 1 ),"&
" 367 (BC_7, dss_data16 , bidir , X, 366, 1, PULL0 ),"&
" 366 (BC_2, * , control , 1 ),"&
" 365 (BC_7, dss_data15 , bidir , X, 364, 1, PULL0 ),"&
" 364 (BC_2, * , control , 1 ),"&
" 363 (BC_7, dss_data14 , bidir , X, 362, 1, PULL0 ),"&
" 362 (BC_2, * , control , 1 ),"&
" 361 (BC_7, dss_data13 , bidir , X, 360, 1, PULL0 ),"&
" 360 (BC_2, * , control , 1 ),"&
" 359 (BC_7, dss_data12 , bidir , X, 358, 1, PULL0 ),"&
" 358 (BC_2, * , control , 1 ),"&
" 357 (BC_7, dss_data11 , bidir , X, 356, 1, PULL0 ),"&
" 356 (BC_2, * , control , 1 ),"&
" 355 (BC_7, dss_data10 , bidir , X, 354, 1, PULL0 ),"&
" 354 (BC_2, * , control , 1 ),"&
" 353 (BC_7, dss_data9 , bidir , X, 352, 1, PULL0 ),"&
" 352 (BC_2, * , control , 1 ),"&
" 351 (BC_7, dss_data8 , bidir , X, 350, 1, PULL0 ),"&
" 350 (BC_2, * , control , 1 ),"&
" 349 (BC_7, dss_data7 , bidir , X, 348, 1, PULL0 ),"&
" 348 (BC_2, * , control , 1 ),"&
" 347 (BC_7, dss_data6 , bidir , X, 346, 1, PULL0 ),"&
" 346 (BC_2, * , control , 1 ),"&
" 345 (BC_7, dss_data5 , bidir , X, 344, 1, PULL1 ),"&
" 344 (BC_2, * , control , 1 ),"&
" 343 (BC_7, dss_data4 , bidir , X, 342, 1, PULL0 ),"&
" 342 (BC_2, * , control , 1 ),"&
" 341 (BC_7, dss_data3 , bidir , X, 340, 1, PULL0 ),"&
" 340 (BC_2, * , control , 1 ),"&
" 339 (BC_7, dss_data2 , bidir , X, 338, 1, PULL0 ),"&
" 338 (BC_2, * , control , 1 ),"&
" 337 (BC_7, dss_data1 , bidir , X, 336, 1, PULL0 ),"&
" 336 (BC_2, * , control , 1 ),"&
" 335 (BC_7, dss_data0 , bidir , X, 334, 1, PULL0 ),"&
" 334 (BC_2, * , control , 1 ),"&
" 333 (BC_7, gpmc_wpn , bidir , X, 332, 1, PULL1 ),"&
" 332 (BC_2, * , control , 1 ),"&
" 331 (BC_7, gpmc_csn3 , bidir , X, 330, 1, PULL1 ),"&
" 330 (BC_2, * , control , 1 ),"&
" 329 (BC_7, gpmc_csn2 , bidir , X, 328, 1, PULL1 ),"&
" 328 (BC_2, * , control , 1 ),"&
" 327 (BC_7, gpmc_csn1 , bidir , X, 326, 1, PULL1 ),"&
" 326 (BC_2, * , control , 1 ),"&
" 325 (BC_7, gpmc_csn0 , bidir , X, 324, 1, PULL1 ),"&
" 324 (BC_2, * , control , 1 ),"&
" 323 (BC_7, gpmc_dir , bidir , X, 322, 1, PULL1 ),"&
" 322 (BC_2, * , control , 1 ),"&
" 321 (BC_7, gpmc_wait0 , bidir , X, 320, 1, PULL1 ),"&
" 320 (BC_2, * , control , 1 ),"&
" 319 (BC_7, gpmc_wait1 , bidir , X, 318, 1, PULL1 ),"&
" 318 (BC_2, * , control , 1 ),"&
" 317 (BC_7, gpmc_wen , bidir , X, 316, 1, PULL1 ),"&
" 316 (BC_2, * , control , 1 ),"&
" 315 (BC_7, gpmc_ben1 , bidir , X, 314, 1, PULL1 ),"&
" 314 (BC_2, * , control , 1 ),"&
" 313 (BC_7, gpmc_ben0_cle , bidir , X, 312, 1, PULL1 ),"&
" 312 (BC_2, * , control , 1 ),"&
" 311 (BC_7, gpmc_clk , bidir , X, 310, 1, PULL0 ),"&
" 310 (BC_2, * , control , 1 ),"&
" 309 (BC_7, gpmc_oen_ren , bidir , X, 308, 1, PULL1 ),"&
" 308 (BC_2, * , control , 1 ),"&
" 307 (BC_7, gpmc_advn_ale , bidir , X, 306, 1, PULL1 ),"&
" 306 (BC_2, * , control , 1 ),"&
" 305 (BC_7, gpmc_ad15 , bidir , X, 304, 1, PULL0 ),"&
" 304 (BC_2, * , control , 1 ),"&
" 303 (BC_7, gpmc_ad14 , bidir , X, 302, 1, PULL0 ),"&
" 302 (BC_2, * , control , 1 ),"&
" 301 (BC_7, gpmc_ad13 , bidir , X, 300, 1, PULL0 ),"&
" 300 (BC_2, * , control , 1 ),"&
" 299 (BC_7, gpmc_ad12 , bidir , X, 298, 1, PULL0 ),"&
" 298 (BC_2, * , control , 1 ),"&
" 297 (BC_1, sysclk_p , input , X ),"&
" 296 (BC_1, ddr_clk_p , input , X ),"&
" 295 (BC_7, gpmc_ad11 , bidir , X, 294, 1, PULL0 ),"&
" 294 (BC_2, * , control , 1 ),"&
" 293 (BC_7, gpmc_ad10 , bidir , X, 292, 1, PULL0 ),"&
" 292 (BC_2, * , control , 1 ),"&
" 291 (BC_7, gpmc_ad9 , bidir , X, 290, 1, PULL0 ),"&
" 290 (BC_2, * , control , 1 ),"&
" 289 (BC_7, gpmc_ad8 , bidir , X, 288, 1, PULL0 ),"&
" 288 (BC_2, * , control , 1 ),"&
" 287 (BC_7, gpmc_ad7 , bidir , X, 286, 1, PULL0 ),"&
" 286 (BC_2, * , control , 1 ),"&
" 285 (BC_7, gpmc_ad6 , bidir , X, 284, 1, PULL0 ),"&
" 284 (BC_2, * , control , 1 ),"&
" 283 (BC_7, gpmc_ad5 , bidir , X, 282, 1, PULL0 ),"&
" 282 (BC_2, * , control , 1 ),"&
" 281 (BC_7, gpmc_ad4 , bidir , X, 280, 1, PULL0 ),"&
" 280 (BC_2, * , control , 1 ),"&
" 279 (BC_7, gpmc_ad3 , bidir , X, 278, 1, PULL0 ),"&
" 278 (BC_2, * , control , 1 ),"&
" 277 (BC_7, gpmc_ad2 , bidir , X, 276, 1, PULL0 ),"&
" 276 (BC_2, * , control , 1 ),"&
" 275 (BC_7, gpmc_ad1 , bidir , X, 274, 1, PULL0 ),"&
" 274 (BC_2, * , control , 1 ),"&
" 273 (BC_7, gpmc_ad0 , bidir , X, 272, 1, PULL0 ),"&
" 272 (BC_2, * , control , 1 ),"&
" 271 (BC_1, rsv18 , output2 , 1, 271, 1, WEAK1 ),"&
" 270 (BC_1, * , internal , 0 ),"&
" 269 (BC_4, rsv18 , observe_only , X ),"&
" 268 (BC_1, rsv17 , output2 , 1, 268, 1, WEAK1 ),"&
" 267 (BC_1, * , internal , 0 ),"&
" 266 (BC_4, rsv17 , observe_only , X ),"&
" 265 (BC_1, rsv16 , output2 , 1, 265, 1, WEAK1 ),"&
" 264 (BC_1, * , internal , 0 ),"&
" 263 (BC_4, rsv16 , observe_only , X ),"&
" 262 (BC_1, rsv15 , output2 , 1, 262, 1, WEAK1 ),"&
" 261 (BC_1, * , internal , 0 ),"&
" 260 (BC_4, rsv15 , observe_only , X ),"&
" 259 (BC_1, rsv14 , output2 , 1, 259, 1, WEAK1 ),"&
" 258 (BC_1, * , internal , 0 ),"&
" 257 (BC_4, rsv14 , observe_only , X ),"&
" 256 (BC_1, rsv13 , output2 , 1, 256, 1, WEAK1 ),"&
" 255 (BC_1, * , internal , 0 ),"&
" 254 (BC_4, rsv13 , observe_only , X ),"&
" 253 (BC_7, resetstatn , bidir , X, 252, 1, PULL1 ),"&
" 252 (BC_2, * , control , 1 ),"&
" 251 (BC_7, bootcomplete , bidir , X, 250, 1, PULL0 ),"&
" 250 (BC_2, * , control , 1 ),"&
" 249 (BC_7, lresetnmienn , bidir , X, 248, 1, PULL1 ),"&
" 248 (BC_2, * , control , 1 ),"&
" 247 (BC_7, lresetn , bidir , X, 246, 1, PULL1 ),"&
" 246 (BC_2, * , control , 1 ),"&
" 245 (BC_7, nmin , bidir , X, 244, 1, PULL1 ),"&
" 244 (BC_2, * , control , 1 ),"&
" 243 (BC_1, i2c2_sda , output2 , 1, 243, 1, WEAK1 ),"&
" 242 (BC_1, * , internal , 0 ),"&
" 241 (BC_3, i2c2_sda , input , X ),"&
" 240 (BC_1, i2c2_scl , output2 , 1, 240, 1, WEAK1 ),"&
" 239 (BC_1, * , internal , 0 ),"&
" 238 (BC_3, i2c2_scl , input , X ),"&
" 237 (BC_1, i2c1_sda , output2 , 1, 237, 1, WEAK1 ),"&
" 236 (BC_1, * , internal , 0 ),"&
" 235 (BC_3, i2c1_sda , input , X ),"&
" 234 (BC_1, i2c1_scl , output2 , 1, 234, 1, WEAK1 ),"&
" 233 (BC_1, * , internal , 0 ),"&
" 232 (BC_3, i2c1_scl , input , X ),"&
" 231 (BC_1, i2c0_sda , output2 , 1, 231, 1, WEAK1 ),"&
" 230 (BC_1, * , internal , 0 ),"&
" 229 (BC_3, i2c0_sda , input , X ),"&
" 228 (BC_1, i2c0_scl , output2 , 1, 228, 1, WEAK1 ),"&
" 227 (BC_1, * , internal , 0 ),"&
" 226 (BC_3, i2c0_scl , input , X ),"&
" 225 (BC_7, mdio_clk , bidir , X, 224, 1, PULL1 ),"&
" 224 (BC_2, * , control , 1 ),"&
" 223 (BC_7, mdio_data , bidir , X, 222, 1, PULL1 ),"&
" 222 (BC_2, * , control , 1 ),"&
" 221 (BC_7, uart1_rtsn , bidir , X, 220, 1, PULL1 ),"&
" 220 (BC_2, * , control , 1 ),"&
" 219 (BC_7, uart1_ctsn , bidir , X, 218, 1, PULL1 ),"&
" 218 (BC_2, * , control , 1 ),"&
" 217 (BC_7, uart1_txd , bidir , X, 216, 1, PULL1 ),"&
" 216 (BC_2, * , control , 1 ),"&
" 215 (BC_7, uart1_rxd , bidir , X, 214, 1, PULL1 ),"&
" 214 (BC_2, * , control , 1 ),"&
" 213 (BC_7, uart0_rtsn , bidir , X, 212, 1, PULL1 ),"&
" 212 (BC_2, * , control , 1 ),"&
" 211 (BC_7, uart0_ctsn , bidir , X, 210, 1, PULL1 ),"&
" 210 (BC_2, * , control , 1 ),"&
" 209 (BC_7, uart0_txd , bidir , X, 208, 1, PULL0 ),"&
" 208 (BC_2, * , control , 1 ),"&
" 207 (BC_7, uart0_rxd , bidir , X, 206, 1, PULL0 ),"&
" 206 (BC_2, * , control , 1 ),"&
" 205 (BC_7, dcan0_rx , bidir , X, 204, 1, PULL1 ),"&
" 204 (BC_2, * , control , 1 ),"&
" 203 (BC_7, dcan0_tx , bidir , X, 202, 1, PULL1 ),"&
" 202 (BC_2, * , control , 1 ),"&
" 201 (BC_7, spi2_simo , bidir , X, 200, 1, PULL0 ),"&
" 200 (BC_2, * , control , 1 ),"&
" 199 (BC_7, spi2_somi , bidir , X, 198, 1, PULL0 ),"&
" 198 (BC_2, * , control , 1 ),"&
" 197 (BC_7, spi2_clk , bidir , X, 196, 1, PULL0 ),"&
" 196 (BC_2, * , control , 1 ),"&
" 195 (BC_7, spi2_scsn1 , bidir , X, 194, 1, PULL1 ),"&
" 194 (BC_2, * , control , 1 ),"&
" 193 (BC_7, spi2_scsn0 , bidir , X, 192, 1, PULL1 ),"&
" 192 (BC_2, * , control , 1 ),"&
" 191 (BC_7, spi1_simo , bidir , X, 190, 1, PULL0 ),"&
" 190 (BC_2, * , control , 1 ),"&
" 189 (BC_7, spi1_somi , bidir , X, 188, 1, PULL0 ),"&
" 188 (BC_2, * , control , 1 ),"&
" 187 (BC_7, spi1_clk , bidir , X, 186, 1, PULL0 ),"&
" 186 (BC_2, * , control , 1 ),"&
" 185 (BC_7, spi1_scsn1 , bidir , X, 184, 1, PULL1 ),"&
" 184 (BC_2, * , control , 1 ),"&
" 183 (BC_7, spi1_scsn0 , bidir , X, 182, 1, PULL1 ),"&
" 182 (BC_2, * , control , 1 ),"&
" 181 (BC_7, spi0_simo , bidir , X, 180, 1, PULL0 ),"&
" 180 (BC_2, * , control , 1 ),"&
" 179 (BC_7, spi0_somi , bidir , X, 178, 1, PULL0 ),"&
" 178 (BC_2, * , control , 1 ),"&
" 177 (BC_7, spi0_clk , bidir , X, 176, 1, PULL0 ),"&
" 176 (BC_2, * , control , 1 ),"&
" 175 (BC_7, spi0_scsn1 , bidir , X, 174, 1, PULL1 ),"&
" 174 (BC_2, * , control , 1 ),"&
" 173 (BC_7, spi0_scsn0 , bidir , X, 172, 1, PULL1 ),"&
" 172 (BC_2, * , control , 1 ),"&
" 171 (BC_7, ddr3_resetn , bidir , X, 170, 1, Z ),"&
" 170 (BC_2, * , control , 1 ),"&
" 169 (BC_7, ddr3_clkout_p0 , bidir , X, 168, 1, Z ),"&
" 168 (BC_2, * , control , 1 ),"&
" 167 (BC_7, ddr3_clkout_p1 , bidir , X, 166, 1, Z ),"&
" 166 (BC_2, * , control , 1 ),"&
" 165 (BC_7, ddr3_clkout_n0 , bidir , X, 164, 1, Z ),"&
" 164 (BC_2, * , control , 1 ),"&
" 163 (BC_7, ddr3_clkout_n1 , bidir , X, 162, 1, Z ),"&
" 162 (BC_2, * , control , 1 ),"&
" 161 (BC_7, ddr3_cke0 , bidir , X, 160, 1, Z ),"&
" 160 (BC_2, * , control , 1 ),"&
" 159 (BC_7, ddr3_cke1 , bidir , X, 158, 1, Z ),"&
" 158 (BC_2, * , control , 1 ),"&
" 157 (BC_7, ddr3_odt0 , bidir , X, 156, 1, Z ),"&
" 156 (BC_2, * , control , 1 ),"&
" 155 (BC_7, ddr3_odt1 , bidir , X, 154, 1, Z ),"&
" 154 (BC_2, * , control , 1 ),"&
" 153 (BC_7, ddr3_cen0 , bidir , X, 152, 1, Z ),"&
" 152 (BC_2, * , control , 1 ),"&
" 151 (BC_7, ddr3_cen1 , bidir , X, 150, 1, Z ),"&
" 150 (BC_2, * , control , 1 ),"&
" 149 (BC_7, ddr3_rasn , bidir , X, 148, 1, Z ),"&
" 148 (BC_2, * , control , 1 ),"&
" 147 (BC_7, ddr3_casn , bidir , X, 146, 1, Z ),"&
" 146 (BC_2, * , control , 1 ),"&
" 145 (BC_7, ddr3_wen , bidir , X, 144, 1, Z ),"&
" 144 (BC_2, * , control , 1 ),"&
" 143 (BC_7, ddr3_ba0 , bidir , X, 142, 1, Z ),"&
" 142 (BC_2, * , control , 1 ),"&
" 141 (BC_7, ddr3_ba1 , bidir , X, 140, 1, Z ),"&
" 140 (BC_2, * , control , 1 ),"&
" 139 (BC_7, ddr3_ba2 , bidir , X, 138, 1, Z ),"&
" 138 (BC_2, * , control , 1 ),"&
" 137 (BC_7, ddr3_a00 , bidir , X, 136, 1, Z ),"&
" 136 (BC_2, * , control , 1 ),"&
" 135 (BC_7, ddr3_a01 , bidir , X, 134, 1, Z ),"&
" 134 (BC_2, * , control , 1 ),"&
" 133 (BC_7, ddr3_a02 , bidir , X, 132, 1, Z ),"&
" 132 (BC_2, * , control , 1 ),"&
" 131 (BC_7, ddr3_a03 , bidir , X, 130, 1, Z ),"&
" 130 (BC_2, * , control , 1 ),"&
" 129 (BC_7, ddr3_a04 , bidir , X, 128, 1, Z ),"&
" 128 (BC_2, * , control , 1 ),"&
" 127 (BC_7, ddr3_a05 , bidir , X, 126, 1, Z ),"&
" 126 (BC_2, * , control , 1 ),"&
" 125 (BC_7, ddr3_a06 , bidir , X, 124, 1, Z ),"&
" 124 (BC_2, * , control , 1 ),"&
" 123 (BC_7, ddr3_a07 , bidir , X, 122, 1, Z ),"&
" 122 (BC_2, * , control , 1 ),"&
" 121 (BC_7, ddr3_a08 , bidir , X, 120, 1, Z ),"&
" 120 (BC_2, * , control , 1 ),"&
" 119 (BC_7, ddr3_a09 , bidir , X, 118, 1, Z ),"&
" 118 (BC_2, * , control , 1 ),"&
" 117 (BC_7, ddr3_a10 , bidir , X, 116, 1, Z ),"&
" 116 (BC_2, * , control , 1 ),"&
" 115 (BC_7, ddr3_a11 , bidir , X, 114, 1, Z ),"&
" 114 (BC_2, * , control , 1 ),"&
" 113 (BC_7, ddr3_a12 , bidir , X, 112, 1, Z ),"&
" 112 (BC_2, * , control , 1 ),"&
" 111 (BC_7, ddr3_a13 , bidir , X, 110, 1, Z ),"&
" 110 (BC_2, * , control , 1 ),"&
" 109 (BC_7, ddr3_a14 , bidir , X, 108, 1, Z ),"&
" 108 (BC_2, * , control , 1 ),"&
" 107 (BC_7, ddr3_a15 , bidir , X, 106, 1, Z ),"&
" 106 (BC_2, * , control , 1 ),"&
" 105 (BC_7, ddr3_dqs0_p , bidir , X, 104, 1, PULL0 ),"&
" 104 (BC_2, * , control , 1 ),"&
" 103 (BC_7, ddr3_dqs1_p , bidir , X, 102, 1, PULL0 ),"&
" 102 (BC_2, * , control , 1 ),"&
" 101 (BC_7, ddr3_dqs2_p , bidir , X, 100, 1, PULL0 ),"&
" 100 (BC_2, * , control , 1 ),"&
" 99 (BC_7, ddr3_dqs3_p , bidir , X, 98, 1, PULL0 ),"&
" 98 (BC_2, * , control , 1 ),"&
" 97 (BC_7, ddr3_cbdqs_p , bidir , X, 96, 1, PULL0 ),"&
" 96 (BC_2, * , control , 1 ),"&
" 95 (BC_7, ddr3_dqs0_n , bidir , X, 94, 1, PULL1 ),"&
" 94 (BC_2, * , control , 1 ),"&
" 93 (BC_7, ddr3_dqs1_n , bidir , X, 92, 1, PULL1 ),"&
" 92 (BC_2, * , control , 1 ),"&
" 91 (BC_7, ddr3_dqs2_n , bidir , X, 90, 1, PULL1 ),"&
" 90 (BC_2, * , control , 1 ),"&
" 89 (BC_7, ddr3_dqs3_n , bidir , X, 88, 1, PULL1 ),"&
" 88 (BC_2, * , control , 1 ),"&
" 87 (BC_7, ddr3_cbdqs_n , bidir , X, 86, 1, PULL1 ),"&
" 86 (BC_2, * , control , 1 ),"&
" 85 (BC_7, ddr3_dqm0 , bidir , X, 84, 1, Z ),"&
" 84 (BC_2, * , control , 1 ),"&
" 83 (BC_7, ddr3_dqm1 , bidir , X, 82, 1, Z ),"&
" 82 (BC_2, * , control , 1 ),"&
" 81 (BC_7, ddr3_dqm2 , bidir , X, 80, 1, Z ),"&
" 80 (BC_2, * , control , 1 ),"&
" 79 (BC_7, ddr3_dqm3 , bidir , X, 78, 1, Z ),"&
" 78 (BC_2, * , control , 1 ),"&
" 77 (BC_7, ddr3_cbdqm , bidir , X, 76, 1, Z ),"&
" 76 (BC_2, * , control , 1 ),"&
" 75 (BC_7, ddr3_d00 , bidir , X, 74, 1, Z ),"&
" 74 (BC_2, * , control , 1 ),"&
" 73 (BC_7, ddr3_d01 , bidir , X, 72, 1, Z ),"&
" 72 (BC_2, * , control , 1 ),"&
" 71 (BC_7, ddr3_d02 , bidir , X, 70, 1, Z ),"&
" 70 (BC_2, * , control , 1 ),"&
" 69 (BC_7, ddr3_d03 , bidir , X, 68, 1, Z ),"&
" 68 (BC_2, * , control , 1 ),"&
" 67 (BC_7, ddr3_d04 , bidir , X, 66, 1, Z ),"&
" 66 (BC_2, * , control , 1 ),"&
" 65 (BC_7, ddr3_d05 , bidir , X, 64, 1, Z ),"&
" 64 (BC_2, * , control , 1 ),"&
" 63 (BC_7, ddr3_d06 , bidir , X, 62, 1, Z ),"&
" 62 (BC_2, * , control , 1 ),"&
" 61 (BC_7, ddr3_d07 , bidir , X, 60, 1, Z ),"&
" 60 (BC_2, * , control , 1 ),"&
" 59 (BC_7, ddr3_d08 , bidir , X, 58, 1, Z ),"&
" 58 (BC_2, * , control , 1 ),"&
" 57 (BC_7, ddr3_d09 , bidir , X, 56, 1, Z ),"&
" 56 (BC_2, * , control , 1 ),"&
" 55 (BC_7, ddr3_d10 , bidir , X, 54, 1, Z ),"&
" 54 (BC_2, * , control , 1 ),"&
" 53 (BC_7, ddr3_d11 , bidir , X, 52, 1, Z ),"&
" 52 (BC_2, * , control , 1 ),"&
" 51 (BC_7, ddr3_d12 , bidir , X, 50, 1, Z ),"&
" 50 (BC_2, * , control , 1 ),"&
" 49 (BC_7, ddr3_d13 , bidir , X, 48, 1, Z ),"&
" 48 (BC_2, * , control , 1 ),"&
" 47 (BC_7, ddr3_d14 , bidir , X, 46, 1, Z ),"&
" 46 (BC_2, * , control , 1 ),"&
" 45 (BC_7, ddr3_d15 , bidir , X, 44, 1, Z ),"&
" 44 (BC_2, * , control , 1 ),"&
" 43 (BC_7, ddr3_d16 , bidir , X, 42, 1, Z ),"&
" 42 (BC_2, * , control , 1 ),"&
" 41 (BC_7, ddr3_d17 , bidir , X, 40, 1, Z ),"&
" 40 (BC_2, * , control , 1 ),"&
" 39 (BC_7, ddr3_d18 , bidir , X, 38, 1, Z ),"&
" 38 (BC_2, * , control , 1 ),"&
" 37 (BC_7, ddr3_d19 , bidir , X, 36, 1, Z ),"&
" 36 (BC_2, * , control , 1 ),"&
" 35 (BC_7, ddr3_d20 , bidir , X, 34, 1, Z ),"&
" 34 (BC_2, * , control , 1 ),"&
" 33 (BC_7, ddr3_d21 , bidir , X, 32, 1, Z ),"&
" 32 (BC_2, * , control , 1 ),"&
" 31 (BC_7, ddr3_d22 , bidir , X, 30, 1, Z ),"&
" 30 (BC_2, * , control , 1 ),"&
" 29 (BC_7, ddr3_d23 , bidir , X, 28, 1, Z ),"&
" 28 (BC_2, * , control , 1 ),"&
" 27 (BC_7, ddr3_d24 , bidir , X, 26, 1, Z ),"&
" 26 (BC_2, * , control , 1 ),"&
" 25 (BC_7, ddr3_d25 , bidir , X, 24, 1, Z ),"&
" 24 (BC_2, * , control , 1 ),"&
" 23 (BC_7, ddr3_d26 , bidir , X, 22, 1, Z ),"&
" 22 (BC_2, * , control , 1 ),"&
" 21 (BC_7, ddr3_d27 , bidir , X, 20, 1, Z ),"&
" 20 (BC_2, * , control , 1 ),"&
" 19 (BC_7, ddr3_d28 , bidir , X, 18, 1, Z ),"&
" 18 (BC_2, * , control , 1 ),"&
" 17 (BC_7, ddr3_d29 , bidir , X, 16, 1, Z ),"&
" 16 (BC_2, * , control , 1 ),"&
" 15 (BC_7, ddr3_d30 , bidir , X, 14, 1, Z ),"&
" 14 (BC_2, * , control , 1 ),"&
" 13 (BC_7, ddr3_d31 , bidir , X, 12, 1, Z ),"&
" 12 (BC_2, * , control , 1 ),"&
" 11 (BC_7, ddr3_cb00 , bidir , X, 10, 1, Z ),"&
" 10 (BC_2, * , control , 1 ),"&
" 9 (BC_7, ddr3_cb01 , bidir , X, 8, 1, Z ),"&
" 8 (BC_2, * , control , 1 ),"&
" 7 (BC_7, ddr3_cb02 , bidir , X, 6, 1, Z ),"&
" 6 (BC_2, * , control , 1 ),"&
" 5 (BC_7, ddr3_cb03 , bidir , X, 4, 1, Z ),"&
" 4 (BC_2, * , control , 1 ),"&
" 3 (BC_7, rsv10 , bidir , X, 2, 1, Z ),"&
" 2 (BC_2, * , control , 1 ),"&
" 1 (BC_7, rsv11 , bidir , X, 0, 1, Z ),"&
" 0 (BC_2, * , control , 1 )";
attribute AIO_COMPONENT_CONFORMANCE of TI66AK2G02 : entity is "STD_1149_6_2003";
attribute AIO_EXTEST_Pulse_Execution of TI66AK2G02 : entity is "Wait_Duration tck 15";
attribute AIO_EXTEST_Train_Execution of TI66AK2G02 : entity is "train 30, maximum_time 120.0e-6";
attribute AIO_Pin_Behavior of TI66AK2G02 : entity is
"pcie_txp0 : AC_Select = 688; "&
"pcie_rxp0 : LP_time=10.0e-9 HP_time=500.0e-9";
attribute DESIGN_WARNING of TI66AK2G02 : entity is
" According to simulation, BSD JTAG TAP may not work correctly unless "&
" device has completed RESET sequence first, "&
" including ~1200 CLKIN pulses after rising edge of porn. "&
" Forcing porn low then release and keeping CLKIN ON (sysclk_p/n) "&
" for ~1200 pulses would meet the requirement, also CLKIN needs to be "&
" ON prior to the rising edge of the trstn. "&
" "&
" Note that boundary scan registers with disable result WEAK1 are "&
" open drain type pins, which will require external pull-ups for "&
" test to perform correctly. "&
" "&
" Once device is programmed for IEEE1149.6 operations, AC coupling RX "&
" pins' comparators become edge sensitive. Therefore their boundary "&
" scan captured values are indeterministic until an edge/transition "&
" is detected. ";
end TI66AK2G02;