-- *****************************************************************
-- Intel 21150-AB/BC
-- PCI to PCI Bridge
-- BSDL file v2.00 19-JUL-1999 TME
-- Changed ds21150 references to in21150 mhp
-- V2.00 - Updated file to work with 21150-BC TME
-- *****************************************************************
-- Information in this document is provided in connection with Intel
-- products. No license, express or implied, by estoppel or
-- otherwise, to any intellectual property rights is granted by this
-- document. Except as provided in Intel's Terms and Conditions of
-- Sale for such products, Intel assumes no liability whatsoever,
-- and Intel disclaims any express or implied warranty, relating to
-- sale and/or use of Intel products including liability or
-- warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or
-- other intellectual property right. Intel products are not
-- intended for use in medical, life saving, or life sustaining
-- applications.
--
-- Intel may make changes to specifications and product descriptions
-- at any time, without notice.
--
-- The products covered by this model may contain design defects or
-- errors known as errata which may cause the product to deviate
-- from published specifications. Current characterized errata are
-- available on request.
--
-- Contact your local Intel sales office or your distributor to
-- obtain the latest specifications and before placing your product
-- order.
--
-- Copyright (c) Intel Corporation 1998. Third-party brands and
-- names are the property of their respective owners.
-- *****************************************************************
entity in21150 is
generic (PHYSICAL_PIN_MAP :string := "PQFP_208");
port ( P_AD : inout bit_vector (31 downto 0);
P_CBE_L : inout bit_vector (3 downto 0);
P_PAR: inout bit;
P_FRAME_L: inout bit;
P_IRDY_L: inout bit;
P_TRDY_L: inout bit;
P_DEVSEL_L: inout bit;
P_STOP_L: inout bit;
P_LOCK_L: in bit;
P_IDSEL: in bit;
P_PERR_L: inout bit;
P_SERR_L: out bit;
P_REQ_L: out bit;
P_GNT_L: in bit;
S_AD : inout bit_vector (31 downto 0);
S_CBE_L : inout bit_vector (3 downto 0);
S_PAR: inout bit;
S_FRAME_L: inout bit;
S_IRDY_L: inout bit;
S_TRDY_L: inout bit;
S_DEVSEL_L: inout bit;
S_STOP_L: inout bit;
S_LOCK_L: inout bit;
S_PERR_L: inout bit;
S_SERR_L: in bit;
S_REQ_L: in bit_vector (8 downto 0);
S_GNT_L: out bit_vector (8 downto 0);
S_CLK: in bit;
S_CLK_O: out bit_vector (9 downto 0);
S_CFN_L: in bit;
GPIO: inout bit_vector (3 downto 0);
P_CLK: in bit;
BPCC: in bit;
P_RST_L: in bit;
S_RST_L: out bit;
MSK_IN: in bit;
P_VIO: linkage bit;
S_VIO: linkage bit;
CONFIG66: in bit;
S_M66ENA: out bit;
P_M66ENA: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TCK: in bit;
TRST_L: in bit;
NC: linkage bit_vector (1 to 2);
VDD: linkage bit_vector (1 to 32);
VSS: linkage bit_vector (1 to 32));
use STD_1149_1_1990.all;
-- attribute COMPONENT_CONFORMANCE of in21150 : entity
-- is "STD_1149_1_1990";
attribute PIN_MAP of in21150 : entity is PHYSICAL_PIN_MAP ;
constant PQFP_208 : PIN_MAP_STRING :=
"P_AD: (49,50,55,57,58,60,61,63,67," &
"68,70,71,73,74,76,77,93,95," &
"96,98,99,101,107,109,112, " &
"113,115,116,118,119,121, " &
"122), " &
"P_CBE_L: (64,79,92,110), " &
"P_PAR: 90, " &
"P_FRAME_L: 80, " &
"P_IRDY_L: 82, " &
"P_TRDY_L: 83, " &
"P_DEVSEL_L: 84, " &
"P_STOP_L: 85, " &
"P_LOCK_L: 87, " &
"P_IDSEL: 65, " &
"P_PERR_L: 88, " &
"P_SERR_L: 89, " &
"P_REQ_L: 47, " &
"P_GNT_L: 46, " &
"S_AD: (206,204,203,201,200,198, " &
"197,195,192,191,189,188, " &
"186,185,183,182,165,164, " &
"162,161,159,154,152,150, " &
"147,146,144,143,141,140, " &
"138,137), " &
"S_CBE_L : (194,180,167,149), " &
"S_PAR: 168, " &
"S_FRAME_L: 179, " &
"S_IRDY_L: 177, " &
"S_TRDY_L: 176, " &
"S_DEVSEL_L: 175, " &
"S_STOP_L: 173, " &
"S_LOCK_L: 172, " &
"S_PERR_L: 171, " &
"S_SERR_L: 169, " &
"S_REQ_L: (9,8,7,6,5,4,3,2,207), " &
"S_GNT_L: (19,18,17,16,15,14,13,11, " &
"10), " &
"S_CLK: 21, " &
"S_CLK_O: (42,41,39,38,36,35,33,32, " &
"30,29), " &
"S_CFN_L: 23, " &
"GPIO: (24,25,27,28), " &
"BPCC: 44, " &
"P_CLK: 45, " &
"P_RST_L: 43, " &
"S_RST_L: 22, " &
"MSK_IN: 126, " &
"P_VIO: 124, " &
"S_VIO: 135, " &
"CONFIG66: 125, " &
"S_M66ENA: 153, " &
"P_M66ENA: 102, " &
"TDI: 129, " &
"TDO: 130, " &
"TMS: 132, " &
"TCK: 133, " &
"TRST_L: 134, " &
"NC: (127,128), " &
"VDD: (1,26,34,40,51,53,56,62,69, " &
"75,81,91,97,103,105,108, " &
"114,120,131,139,145,151, " &
"155,157,163,170,178,184, " &
"190,196,202,208), " &
"VSS: (12,20,31,37,48,52,54,59, " &
"66,72,78,86,94,100,104,106," &
"111,117,123,136,142,148, " &
"156,158,160,166,174,181, " &
"187,193,199,205) ";
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_RESET of TRST_L : signal is TRUE;
attribute INSTRUCTION_LENGTH of in21150 : entity is 5 ;
attribute INSTRUCTION_OPCODE of in21150 : entity is
"EXTEST (00000)," &
"BYPASS (11111)," &
"SAMPLE (00001)," &
"HIGHZ (00101)," &
"BSROSC (00010)," &
"BSRDLY (00011)," &
"CLAMP (00100)";
attribute INSTRUCTION_CAPTURE of in21150 : entity is "00001" ;
attribute INSTRUCTION_PRIVATE of in21150 : entity is
"BSROSC,BSRDLY,CLAMP";
attribute REGISTER_ACCESS of in21150 : entity is
"BOUNDARY(EXTEST,SAMPLE)," &
"BYPASS(HIGHZ,BYPASS)";
attribute BOUNDARY_CELLS of in21150 : entity is "BC_1, BC_4, BC_6" ;
attribute BOUNDARY_LENGTH of in21150 : entity is 144 ;
attribute BOUNDARY_REGISTER of in21150 : entity is
-- PORT DESCRIPTION TERMS
-- cell type: BC_*
-- port: port name with index if port description says bit_vector
-- function
-- input = input only
-- bidir = bidirectional
-- control = control cell
-- output2 = two state output
-- output3 = three state output
-- safe = value in control cell to make input = 0 for bidir and controlr
-- ccell = controlling cell number for I/O direction
-- dsval = disabling (input) value
--- num ctype port function safe ccell disval dis_state
--------------------------------------------------------------------
" 0 ( BC_6, S_AD(0), BIDIR, X, 18, 1, Z)," &
" 1 ( BC_6, S_AD(1), BIDIR, X, 18, 1, Z)," &
" 2 ( BC_6, S_AD(2), BIDIR, X, 18, 1, Z)," &
" 3 ( BC_6, S_AD(3), BIDIR, X, 18, 1, Z)," &
" 4 ( BC_6, S_AD(4), BIDIR, X, 18, 1, Z)," &
" 5 ( BC_6, S_AD(5), BIDIR, X, 18, 1, Z)," &
" 6 ( BC_6, S_AD(6), BIDIR, X, 18, 1, Z)," &
" 7 ( BC_6, S_AD(7), BIDIR, X, 18, 1, Z)," &
" 8 ( BC_6, S_CBE_L(0), BIDIR, X, 18, 1, Z)," &
" 9 ( BC_6, S_AD(8), BIDIR, X, 18, 1, Z)," &
" 10 ( BC_6, S_AD(9), BIDIR, X, 18, 1, Z)," &
" 11 ( BC_1, S_M66ENA, OUTPUT3, X, 18, 1, WEAK1)," &
" 12 ( BC_6, S_AD(10), BIDIR, X, 18, 1, Z)," &
" 13 ( BC_6, S_AD(11), BIDIR, X, 18, 1, Z)," &
" 14 ( BC_6, S_AD(12), BIDIR, X, 18, 1, Z)," &
" 15 ( BC_6, S_AD(13), BIDIR, X, 18, 1, Z)," &
" 16 ( BC_6, S_AD(14), BIDIR, X, 18, 1, Z)," &
" 17 ( BC_6, S_AD(15), BIDIR, X, 18, 1, Z)," &
" 18 ( BC_1, *, CONTROL, 1)," &
" 19 ( BC_6, S_CBE_L(1), BIDIR, X, 18, 1, Z)," &
" 20 ( BC_6, S_PAR, BIDIR, X, 18, 1, Z)," &
" 21 ( BC_4, S_SERR_L, INPUT, 0), " &
" 22 ( BC_6, S_PERR_L, BIDIR, X, 25, 1, Z)," &
" 23 ( BC_6, S_LOCK_L, BIDIR, X, 25, 1, Z)," &
" 24 ( BC_6, S_STOP_L, BIDIR, X, 25, 1, Z)," &
" 25 ( BC_1, *, CONTROL, 1)," &
" 26 ( BC_6, S_DEVSEL_L, BIDIR, X, 25, 1, Z)," &
" 27 ( BC_6, S_TRDY_L, BIDIR, X, 25, 1, Z)," &
" 28 ( BC_6, S_IRDY_L, BIDIR, X, 25, 1, Z)," &
" 29 ( BC_6, S_FRAME_L, BIDIR, X, 25, 1, Z)," &
" 30 ( BC_6, S_CBE_L(2), BIDIR, X, 47, 1, Z)," &
" 31 ( BC_6, S_AD(16), BIDIR, X, 47, 1, Z)," &
" 32 ( BC_6, S_AD(17), BIDIR, X, 47, 1, Z)," &
" 33 ( BC_6, S_AD(18), BIDIR, X, 47, 1, Z)," &
" 34 ( BC_6, S_AD(19), BIDIR, X, 47, 1, Z)," &
" 35 ( BC_6, S_AD(20), BIDIR, X, 47, 1, Z)," &
" 36 ( BC_6, S_AD(21), BIDIR, X, 47, 1, Z)," &
" 37 ( BC_6, S_AD(22), BIDIR, X, 47, 1, Z)," &
" 38 ( BC_6, S_AD(23), BIDIR, X, 47, 1, Z)," &
" 39 ( BC_6, S_CBE_L(3), BIDIR, X, 47, 1, Z)," &
" 40 ( BC_6, S_AD(24), BIDIR, X, 47, 1, Z)," &
" 41 ( BC_6, S_AD(25), BIDIR, X, 47, 1, Z)," &
" 42 ( BC_6, S_AD(26), BIDIR, X, 47, 1, Z)," &
" 43 ( BC_6, S_AD(27), BIDIR, X, 47, 1, Z)," &
" 44 ( BC_6, S_AD(28), BIDIR, X, 47, 1, Z)," &
" 45 ( BC_6, S_AD(29), BIDIR, X, 47, 1, Z)," &
" 46 ( BC_6, S_AD(30), BIDIR, X, 47, 1, Z)," &
" 47 ( BC_1, *, CONTROL, 1)," &
" 48 ( BC_6, S_AD(31), BIDIR, X, 47, 1, Z)," &
" 49 ( BC_4, S_REQ_L(0), INPUT, 0), " &
" 50 ( BC_4, S_REQ_L(1), INPUT, 0), " &
" 51 ( BC_4, S_REQ_L(2), INPUT, 0), " &
" 52 ( BC_4, S_REQ_L(3), INPUT, 0), " &
" 53 ( BC_4, S_REQ_L(4), INPUT, 0), " &
" 54 ( BC_4, S_REQ_L(5), INPUT, 0), " &
" 55 ( BC_4, S_REQ_L(6), INPUT, 0), " &
" 56 ( BC_4, S_REQ_L(7), INPUT, 0), " &
" 57 ( BC_4, S_REQ_L(8), INPUT, 0), " &
" 58 ( BC_1, S_GNT_L(0), OUTPUT3, X, 60, 1, Z)," &
" 59 ( BC_1, S_GNT_L(1), OUTPUT3, X, 60, 1, Z)," &
" 60 ( BC_1, *, CONTROL, 1)," &
" 61 ( BC_1, S_GNT_L(2), OUTPUT3, X, 60, 1, Z)," &
" 62 ( BC_1, S_GNT_L(3), OUTPUT3, X, 60, 1, Z)," &
" 63 ( BC_1, S_GNT_L(4), OUTPUT3, X, 60, 1, Z)," &
" 64 ( BC_1, S_GNT_L(5), OUTPUT3, X, 60, 1, Z)," &
" 65 ( BC_1, S_GNT_L(6), OUTPUT3, X, 60, 1, Z)," &
" 66 ( BC_1, S_GNT_L(7), OUTPUT3, X, 60, 1, Z)," &
" 67 ( BC_1, S_GNT_L(8), OUTPUT3, X, 60, 1, Z)," &
" 68 ( BC_4, S_CLK, INPUT, 0), " &
" 69 ( BC_1, S_RST_L, OUTPUT3, X, 77, 1, Z)," &
" 70 ( BC_4, S_CFN_L, INPUT, 0), " &
" 71 ( BC_6, GPIO(3), BIDIR, X, 77, 1, Z)," &
" 72 ( BC_6, GPIO(2), BIDIR, X, 77, 1, Z)," &
" 73 ( BC_6, GPIO(1), BIDIR, X, 77, 1, Z)," &
" 74 ( BC_6, GPIO(0), BIDIR, X, 77, 1, Z)," &
" 75 ( BC_1, S_CLK_O(0), OUTPUT2, X)," &
" 76 ( BC_1, S_CLK_O(1), OUTPUT2, X)," &
" 77 ( BC_1, *, CONTROL, 1)," &
" 78 ( BC_1, S_CLK_O(2), OUTPUT2, X)," &
" 79 ( BC_1, S_CLK_O(3), OUTPUT2, X)," &
" 80 ( BC_1, S_CLK_O(4), OUTPUT2, X)," &
" 81 ( BC_1, S_CLK_O(5), OUTPUT2, X)," &
" 82 ( BC_1, S_CLK_O(6), OUTPUT2, X)," &
" 83 ( BC_1, S_CLK_O(7), OUTPUT2, X)," &
" 84 ( BC_1, S_CLK_O(8), OUTPUT2, X)," &
" 85 ( BC_1, S_CLK_O(9), OUTPUT2, X)," &
" 86 ( BC_4, P_RST_L, INPUT, 0), " &
" 87 ( BC_4, BPCC, INPUT, 0), " &
" 88 ( BC_4, P_CLK, INPUT, 0), " &
" 89 ( BC_4, P_GNT_L, INPUT, 0), " &
" 90 ( BC_1, P_REQ_L, OUTPUT3, X, 91, 1, Z)," &
" 91 ( BC_1, *, CONTROL, 1)," &
" 92 ( BC_6, P_AD(31), BIDIR, X, 110, 1, Z)," &
" 93 ( BC_6, P_AD(30), BIDIR, X, 110, 1, Z)," &
" 94 ( BC_6, P_AD(29), BIDIR, X, 110, 1, Z)," &
" 95 ( BC_6, P_AD(28), BIDIR, X, 110, 1, Z)," &
" 96 ( BC_6, P_AD(27), BIDIR, X, 110, 1, Z)," &
" 97 ( BC_6, P_AD(26), BIDIR, X, 110, 1, Z)," &
" 98 ( BC_6, P_AD(25), BIDIR, X, 110, 1, Z)," &
" 99 ( BC_6, P_AD(24), BIDIR, X, 110, 1, Z)," &
" 100 ( BC_6, P_CBE_L(3), BIDIR, X, 110, 1, Z)," &
" 101 ( BC_4, P_IDSEL, INPUT, 0), " &
" 102 ( BC_6, P_AD(23), BIDIR, X, 110, 1, Z)," &
" 103 ( BC_6, P_AD(22), BIDIR, X, 110, 1, Z)," &
" 104 ( BC_6, P_AD(21), BIDIR, X, 110, 1, Z)," &
" 105 ( BC_6, P_AD(20), BIDIR, X, 110, 1, Z)," &
" 106 ( BC_6, P_AD(19), BIDIR, X, 110, 1, Z)," &
" 107 ( BC_6, P_AD(18), BIDIR, X, 110, 1, Z)," &
" 108 ( BC_6, P_AD(17), BIDIR, X, 110, 1, Z)," &
" 109 ( BC_6, P_AD(16), BIDIR, X, 110, 1, Z)," &
" 110 ( BC_1, *, CONTROL, 1)," &
" 111 ( BC_6, P_CBE_L(2), BIDIR, X, 110, 1, Z)," &
" 112 ( BC_6, P_FRAME_L, BIDIR, X, 117, 1, Z)," &
" 113 ( BC_6, P_IRDY_L, BIDIR, X, 117, 1, Z)," &
" 114 ( BC_6, P_TRDY_L, BIDIR, X, 117, 1, Z)," &
" 115 ( BC_6, P_DEVSEL_L, BIDIR, X, 117, 1, Z)," &
" 116 ( BC_6, P_STOP_L, BIDIR, X, 117, 1, Z)," &
" 117 ( BC_1, *, CONTROL, 1)," &
" 118 ( BC_4, P_LOCK_L, INPUT, 0), " &
" 119 ( BC_6, P_PERR_L, BIDIR, X, 117, 1, Z)," &
" 120 ( BC_1, P_SERR_L, OUTPUT3, X, 117, 1, WEAK1)," &
" 121 ( BC_6, P_PAR, BIDIR, X, 141, 1, Z)," &
" 122 ( BC_6, P_CBE_L(1), BIDIR, X, 141, 1, Z)," &
" 123 ( BC_6, P_AD(15), BIDIR, X, 141, 1, Z)," &
" 124 ( BC_6, P_AD(14), BIDIR, X, 141, 1, Z)," &
" 125 ( BC_6, P_AD(13), BIDIR, X, 141, 1, Z)," &
" 126 ( BC_6, P_AD(12), BIDIR, X, 141, 1, Z)," &
" 127 ( BC_6, P_AD(11), BIDIR, X, 141, 1, Z)," &
" 128 ( BC_6, P_AD(10), BIDIR, X, 141, 1, Z)," &
" 129 ( BC_4, P_M66ENA, INPUT, 0), " &
" 130 ( BC_6, P_AD(9), BIDIR, X, 141, 1, Z)," &
" 131 ( BC_6, P_AD(8), BIDIR, X, 141, 1, Z)," &
" 132 ( BC_6, P_CBE_L(0), BIDIR, X, 141, 1, Z)," &
" 133 ( BC_6, P_AD(7), BIDIR, X, 141, 1, Z)," &
" 134 ( BC_6, P_AD(6), BIDIR, X, 141, 1, Z)," &
" 135 ( BC_6, P_AD(5), BIDIR, X, 141, 1, Z)," &
" 136 ( BC_6, P_AD(4), BIDIR, X, 141, 1, Z)," &
" 137 ( BC_6, P_AD(3), BIDIR, X, 141, 1, Z)," &
" 138 ( BC_6, P_AD(2), BIDIR, X, 141, 1, Z)," &
" 139 ( BC_6, P_AD(1), BIDIR, X, 141, 1, Z)," &
" 140 ( BC_6, P_AD(0), BIDIR, X, 141, 1, Z)," &
" 141 ( BC_1, *, CONTROL, 1), " &
" 142 ( BC_4, CONFIG66, INPUT, 0), " &
" 143 ( BC_4, MSK_IN, INPUT, 0)" ;
end in21150 ;
