-- ***************************************************************
-- Company: Integrated Device Technology, Inc.
--
-- Tundra Document number: 35B804A_BS001_04
--
-- Title: BSDL file of Tsi576
-- Generated by : Andi Sugandi
-- Revised by: Bruno Latulippe
--
-- Release status: formal issue
-- Security level: client use
-- BSDL Version 2001
-- Group ownership: DFT Revision Date:
-- Released by :
-- Revision History:
-- Oct 18, 2006: initial release for version B0
-- Feb 1, 2007: Rename TRI_b signal to VDD_IO
-- Aug 11, 2009: Updated with IDT formatting
-- Oct 30, 2009: Renamed TCK2_P/N, DI as VSS
--
-- BSDL Syntax Checker -> passed oct 30, 2009
--
--
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2a-Build20050202.003 on 10/18/05 10:56:27
-- BSDL Version 2001
-- The default acjt_lvl[4:0] which is controlled by IRbits[29:25] is set to 2'h03,
-- tx_lvl which is controlled by IRbits[38:34] is set to 4'h1F
-- To program acjt_lvl and tx_lvl IRbits[33] has to be set to 0
-- The JTAG ID part number is 572.
entity Tsi576 is
generic (PHYSICAL_PIN_MAP : string := "FCBGA_399_21");
port (
-- Port List
SP0_TD_P : out bit;
SP0_TD_N : out bit;
SP0_RD_P : in bit;
SP0_RD_N : in bit;
SP0_TC_P : out bit;
SP0_TC_N : out bit;
SP0_RC_P : in bit;
SP0_RC_N : in bit;
SP0_TB_P : out bit;
SP0_TB_N : out bit;
SP0_RB_P : in bit;
SP0_RB_N : in bit;
SP0_TA_P : out bit;
SP0_TA_N : out bit;
SP0_RA_P : in bit;
SP0_RA_N : in bit;
SP0_REXT : linkage bit;
SP2_TB_P : out bit;
SP2_TB_N : out bit;
SP2_RB_P : in bit;
SP2_RB_N : in bit;
SP2_TA_P : out bit;
SP2_TA_N : out bit;
SP2_RA_P : in bit;
SP2_RA_N : in bit;
SP2_REXT : linkage bit;
SP4_TB_P : out bit;
SP4_TB_N : out bit;
SP4_RB_P : in bit;
SP4_RB_N : in bit;
SP4_TA_P : out bit;
SP4_TA_N : out bit;
SP4_RA_P : in bit;
SP4_RA_N : in bit;
SP4_REXT : linkage bit;
SP6_TD_P : out bit;
SP6_TD_N : out bit;
SP6_RD_P : in bit;
SP6_RD_N : in bit;
SP6_TC_P : out bit;
SP6_TC_N : out bit;
SP6_RC_P : in bit;
SP6_RC_N : in bit;
SP6_TB_P : out bit;
SP6_TB_N : out bit;
SP6_RB_P : in bit;
SP6_RB_N : in bit;
SP6_TA_P : out bit;
SP6_TA_N : out bit;
SP6_RA_P : in bit;
SP6_RA_N : in bit;
SP6_REXT : linkage bit;
SP10_TB_P : out bit;
SP10_TB_N : out bit;
SP10_RB_P : in bit;
SP10_RB_N : in bit;
SP10_TA_P : out bit;
SP10_TA_N : out bit;
SP10_RA_P : in bit;
SP10_RA_N : in bit;
SP10_REXT : linkage bit;
SP12_TB_P : out bit;
SP12_TB_N : out bit;
SP12_RB_P : in bit;
SP12_RB_N : in bit;
SP12_TA_P : out bit;
SP12_TA_N : out bit;
SP12_RA_P : in bit;
SP12_RA_N : in bit;
SP12_REXT : linkage bit;
P_CLK : in bit;
S_CLK_P : linkage bit;
S_CLK_N : linkage bit;
I2C_SCLK : inout bit;
I2C_SD : inout bit;
I2C_DISABLE : inout bit;
I2C_MA : inout bit;
I2C_SA : inout bit_vector( 1 downto 0 );
I2C_SEL : inout bit;
HARD_RST_B : linkage bit;
INT_B : inout bit;
SW_RST_B : inout bit;
SPY_CLK_0 : linkage bit;
SPY_CLK_1 : linkage bit;
TCK : in bit;
TMS : in bit;
TDI : in bit;
TDO : out bit;
TRST_B : in bit;
BCE : in bit;
DO : out bit;
SP_RX_SWAP : inout bit;
SP_TX_SWAP : inout bit;
SP_IO_SPEED : inout bit_vector( 1 downto 0 );
SP1_PWRDN : inout bit;
SP2_PWRDN : inout bit;
SP3_PWRDN : inout bit;
SP4_PWRDN : inout bit;
SP5_PWRDN : inout bit;
SP6_PWRDN : inout bit;
SP7_PWRDN : inout bit;
SP10_PWRDN : inout bit;
SP11_PWRDN : inout bit;
SP12_PWRDN : inout bit;
SP13_PWRDN : inout bit;
SP0_MODESEL : inout bit;
SP6_MODESEL : inout bit;
MCES : inout bit;
VDD_IO : linkage bit_vector( 11 downto 0 );
VSS_IO : linkage bit_vector( 11 downto 0 );
VSS : linkage bit_vector( 185 downto 0 );
VDD : linkage bit_vector( 31 downto 0 );
SP_VDD : linkage bit_vector( 30 downto 0 );
SP_AVDD : linkage bit_vector( 13 downto 0 );
REF_AVDD : linkage bit_vector( 1 downto 0 ));
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of Tsi576: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of Tsi576: entity is PHYSICAL_PIN_MAP;
constant FCBGA_399_21: PIN_MAP_STRING :=
"SP0_TD_P : l1 , " &
"SP0_TD_N : l2 , " &
"SP0_RD_P : l5 , " &
"SP0_RD_N : l4 , " &
"SP0_TC_P : j2 , " &
"SP0_TC_N : j1 , " &
"SP0_RC_P : j4 , " &
"SP0_RC_N : j5 , " &
"SP0_TB_P : g1 , " &
"SP0_TB_N : g2 , " &
"SP0_RB_P : g5 , " &
"SP0_RB_N : g4 , " &
"SP0_TA_P : e2 , " &
"SP0_TA_N : e1 , " &
"SP0_RA_P : e4 , " &
"SP0_RA_N : e5 , " &
"SP0_REXT : h4 , " &
"SP2_TB_P : y9 , " &
"SP2_TB_N : w9 , " &
"SP2_RB_P : t9 , " &
"SP2_RB_N : u9 , " &
"SP2_TA_P : w7 , " &
"SP2_TA_N : y7 , " &
"SP2_RA_P : u7 , " &
"SP2_RA_N : t7 , " &
"SP2_REXT : u10 , " &
"SP4_TB_P : l20 , " &
"SP4_TB_N : l19 , " &
"SP4_RB_P : l16 , " &
"SP4_RB_N : l17 , " &
"SP4_TA_P : n19 , " &
"SP4_TA_N : n20 , " &
"SP4_RA_P : n17 , " &
"SP4_RA_N : n16 , " &
"SP4_REXT : k17 , " &
"SP6_TD_P : a8 , " &
"SP6_TD_N : b8 , " &
"SP6_RD_P : e8 , " &
"SP6_RD_N : d8 , " &
"SP6_TC_P : b10 , " &
"SP6_TC_N : a10 , " &
"SP6_RC_P : d10 , " &
"SP6_RC_N : e10 , " &
"SP6_TB_P : a12 , " &
"SP6_TB_N : b12 , " &
"SP6_RB_P : e12 , " &
"SP6_RB_N : d12 , " &
"SP6_TA_P : b14 , " &
"SP6_TA_N : a14 , " &
"SP6_RA_P : d14 , " &
"SP6_RA_N : e14 , " &
"SP6_REXT : d11 , " &
"SP10_TB_P : y13 , " &
"SP10_TB_N : w13 , " &
"SP10_RB_P : t13 , " &
"SP10_RB_N : u13 , " &
"SP10_TA_P : w11 , " &
"SP10_TA_N : y11 , " &
"SP10_RA_P : u11 , " &
"SP10_RA_N : t11 , " &
"SP10_REXT : u14 , " &
"SP12_TB_P : g20 , " &
"SP12_TB_N : g19 , " &
"SP12_RB_P : g16 , " &
"SP12_RB_N : g17 , " &
"SP12_TA_P : j19 , " &
"SP12_TA_N : j20 , " &
"SP12_RA_P : j17 , " &
"SP12_RA_N : j16 , " &
"SP12_REXT : f17 , " &
"P_CLK : y1 , " &
"S_CLK_P : b18 , " &
"S_CLK_N : b19 , " &
"I2C_SCLK : y19 , " &
"I2C_SD : w18 , " &
"I2C_DISABLE : u18 , " &
"I2C_MA : w16 , " &
"I2C_SA :(r17 , " & -- I2C_SA[1]
"r16 ), " & -- I2C_SA[0]
"I2C_SEL : t17 , " &
"HARD_RST_B : y3 , " &
"INT_B : u2 , " &
"SW_RST_B : v3 , " &
"SPY_CLK_0 : v1 , " &
"SPY_CLK_1 : v4 , " &
"TCK : y20 , " &
"TMS : u20 , " &
"TDI : v20 , " &
"TDO : v19 , " &
"TRST_B : w20 , " &
"BCE : r20 , " &
"DO : w2 , " &
"SP_RX_SWAP : t19 , " &
"SP_TX_SWAP : t20 , " &
"SP_IO_SPEED :(u16 , " & -- SP_IO_SPEED[1]
"t16 ), " & -- SP_IO_SPEED[0]
"SP1_PWRDN : y16 , " &
"SP2_PWRDN : w17 , " &
"SP3_PWRDN : y17 , " &
"SP4_PWRDN : n2 , " &
"SP5_PWRDN : n3 , " &
"SP6_PWRDN : p1 , " &
"SP7_PWRDN : p3 , " &
"SP10_PWRDN : r2 , " &
"SP11_PWRDN : r3 , " &
"SP12_PWRDN : v5 , " &
"SP13_PWRDN : w5 , " &
"SP0_MODESEL : v16 , " &
"SP6_MODESEL : u5 , " &
"MCES : r19 , " &
"VDD_IO :(y2 , " & -- VDD_IO[11]
"w19 , " & -- VDD_IO[10]
"w4 , " & -- VDD_IO[9]
"v2 , " & -- VDD_IO[8]
"u19 , " & -- VDD_IO[7]
"u17 , " & -- VDD_IO[6]
"u4 , " & -- VDD_IO[5]
"t3 , " & -- VDD_IO[4]
"t2 , " & -- VDD_IO[3]
"r4 , " & -- VDD_IO[2]
"p2 , " & -- VDD_IO[1]
"n4 ), " & -- VDD_IO[0]
"VSS_IO :(n1 , " & -- VSS_IO[11]
"r1 , " & -- VSS_IO[10]
"u1 , " & -- VSS_IO[9]
"w1 , " & -- VSS_IO[8]
"p4 , " & -- VSS_IO[7]
"t18 , " & -- VSS_IO[6]
"v18 , " & -- VSS_IO[5]
"v17 , " & -- VSS_IO[4]
"t1 , " & -- VSS_IO[3]
"t4 , " & -- VSS_IO[2]
"u3 , " & -- VSS_IO[1]
"y18 ), " & -- VSS_IO[0]
"VSS :(y5 , " & -- VSS[185]
"t5 , " & -- VSS[184]
"m3 , " & -- VSS[183]
"y15 , " & -- VSS[182]
"y14 , " & -- VSS[181]
"y12 , " & -- VSS[180]
"y10 , " & -- VSS[179]
"y8 , " & -- VSS[178]
"y6 , " & -- VSS[177]
"y4 , " & -- VSS[176]
"w15 , " & -- VSS[175]
"w12 , " & -- VSS[174]
"w8 , " & -- VSS[173]
"w6 , " & -- VSS[172]
"w3 , " & -- VSS[171] -- DI
"v15 , " & -- VSS[170]
"v14 , " & -- VSS[169]
"v12 , " & -- VSS[168]
"v10 , " & -- VSS[167]
"v8 , " & -- VSS[166]
"v6 , " & -- VSS[165]
"u15 , " & -- VSS[164]
"u12 , " & -- VSS[163]
"u8 , " & -- VSS[162]
"u6 , " & -- VSS[161]
"t15 , " & -- VSS[160]
"t6 , " & -- VSS[159]
"r18 , " & -- VSS[158]
"r15 , " & -- VSS[157]
"r14 , " & -- VSS[156]
"r12 , " & -- VSS[155]
"r10 , " & -- VSS[154]
"r9 , " & -- VSS[153]
"r8 , " & -- VSS[152]
"r7 , " & -- VSS[151]
"r6 , " & -- VSS[150]
"r5 , " & -- VSS[149]
"p20 , " & -- VSS[148]
"p18 , " & -- VSS[147]
"p17 , " & -- VSS[146]
"p16 , " & -- VSS[145]
"p15 , " & -- VSS[144]
"p14 , " & -- VSS[143]
"p12 , " & -- VSS[142]
"p10 , " & -- VSS[141]
"p8 , " & -- VSS[140]
"p6 , " & -- VSS[139]
"p5 , " & -- VSS[138]
"n15 , " & -- VSS[137]
"n13 , " & -- VSS[136]
"n11 , " & -- VSS[135]
"n9 , " & -- VSS[134]
"n7 , " & -- VSS[133]
"n6 , " & -- VSS[132]
"n5 , " & -- VSS[131]
"m20 , " & -- VSS[130]
"m19 , " & -- VSS[129]
"m18 , " & -- VSS[128]
"m17 , " & -- VSS[127]
"m15 , " & -- VSS[126]
"m14 , " & -- VSS[125]
"m12 , " & -- VSS[124]
"m10 , " & -- VSS[123]
"m8 , " & -- VSS[122]
"m6 , " & -- VSS[121]
"m5 , " & -- VSS[120]
"m4 , " & -- VSS[119]
"m1 , " & -- VSS[118]
"l13 , " & -- VSS[117]
"l11 , " & -- VSS[116]
"l9 , " & -- VSS[115]
"l7 , " & -- VSS[114]
"k20 , " & -- VSS[113]
"k18 , " & -- VSS[112]
"k15 , " & -- VSS[111]
"k14 , " & -- VSS[110]
"k12 , " & -- VSS[109]
"k10 , " & -- VSS[108]
"k8 , " & -- VSS[107]
"k6 , " & -- VSS[106]
"k4 , " & -- VSS[105]
"k3 , " & -- VSS[104]
"k2 , " & -- VSS[103]
"k1 , " & -- VSS[102]
"j15 , " & -- VSS[101]
"j13 , " & -- VSS[100]
"j11 , " & -- VSS[99]
"j9 , " & -- VSS[98]
"j7 , " & -- VSS[97]
"j6 , " & -- VSS[96]
"h20 , " & -- VSS[95]
"h19 , " & -- VSS[94]
"h18 , " & -- VSS[93]
"h17 , " & -- VSS[92]
"h14 , " & -- VSS[91]
"h12 , " & -- VSS[90]
"h10 , " & -- VSS[89]
"h8 , " & -- VSS[88]
"h6 , " & -- VSS[87]
"h3 , " & -- VSS[86]
"h1 , " & -- VSS[85]
"g15 , " & -- VSS[84]
"g13 , " & -- VSS[83]
"g11 , " & -- VSS[82]
"g9 , " & -- VSS[81]
"g7 , " & -- VSS[80]
"g6 , " & -- VSS[79]
"f20 , " & -- VSS[78]
"f19 , " & -- VSS[77]
"f18 , " & -- VSS[76]
"f15 , " & -- VSS[75]
"f14 , " & -- VSS[74]
"f13 , " & -- VSS[73]
"f12 , " & -- VSS[72]
"f10 , " & -- VSS[71]
"f9 , " & -- VSS[70]
"f8 , " & -- VSS[69]
"f7 , " & -- VSS[68]
"f6 , " & -- VSS[67]
"f4 , " & -- VSS[66]
"f3 , " & -- VSS[65]
"f2 , " & -- VSS[64]
"f1 , " & -- VSS[63]
"e20 , " & -- VSS[62]
"e19 , " & -- VSS[61]
"e18 , " & -- VSS[60]
"e17 , " & -- VSS[59]
"e16 , " & -- VSS[58]
"e15 , " & -- VSS[57]
"e7 , " & -- VSS[56]
"e6 , " & -- VSS[55]
"d20 , " & -- VSS[54]
"d19 , " & -- VSS[53] -- TCK2_N
"d18 , " & -- VSS[52] -- TCK2_P
"d17 , " & -- VSS[51]
"d16 , " & -- VSS[50]
"d15 , " & -- VSS[49]
"d13 , " & -- VSS[48]
"d9 , " & -- VSS[47]
"d7 , " & -- VSS[46]
"d6 , " & -- VSS[45]
"d5 , " & -- VSS[44]
"d4 , " & -- VSS[43]
"d3 , " & -- VSS[42]
"d1 , " & -- VSS[41]
"c19 , " & -- VSS[40]
"c17 , " & -- VSS[39]
"c16 , " & -- VSS[38]
"c15 , " & -- VSS[37]
"c13 , " & -- VSS[36]
"c11 , " & -- VSS[35]
"c9 , " & -- VSS[34]
"c7 , " & -- VSS[33]
"c6 , " & -- VSS[32]
"c5 , " & -- VSS[31]
"c4 , " & -- VSS[30]
"c3 , " & -- VSS[29]
"c2 , " & -- VSS[28]
"c1 , " & -- VSS[27]
"b20 , " & -- VSS[26]
"b17 , " & -- VSS[25]
"b16 , " & -- VSS[24]
"b13 , " & -- VSS[23]
"b9 , " & -- VSS[22]
"b7 , " & -- VSS[21]
"b6 , " & -- VSS[20]
"b5 , " & -- VSS[19]
"b4 , " & -- VSS[18]
"b3 , " & -- VSS[17]
"b2 , " & -- VSS[16]
"b1 , " & -- VSS[15]
"a20 , " & -- VSS[14]
"a19 , " & -- VSS[13]
"a18 , " & -- VSS[12]
"a17 , " & -- VSS[11]
"a16 , " & -- VSS[10]
"a15 , " & -- VSS[9]
"a13 , " & -- VSS[8]
"a11 , " & -- VSS[7]
"a9 , " & -- VSS[6]
"a7 , " & -- VSS[5]
"a6 , " & -- VSS[4]
"a5 , " & -- VSS[3]
"a4 , " & -- VSS[2]
"a3 , " & -- VSS[1]
"a2 ), " & -- VSS[0]
"VDD :(p13 , " & -- VDD[31]
"p11 , " & -- VDD[30]
"p9 , " & -- VDD[29]
"p7 , " & -- VDD[28]
"n14 , " & -- VDD[27]
"n12 , " & -- VDD[26]
"n10 , " & -- VDD[25]
"n8 , " & -- VDD[24]
"m13 , " & -- VDD[23]
"m11 , " & -- VDD[22]
"m9 , " & -- VDD[21]
"m7 , " & -- VDD[20]
"l14 , " & -- VDD[19]
"l12 , " & -- VDD[18]
"l10 , " & -- VDD[17]
"l8 , " & -- VDD[16]
"k13 , " & -- VDD[15]
"k11 , " & -- VDD[14]
"k9 , " & -- VDD[13]
"k7 , " & -- VDD[12]
"j14 , " & -- VDD[11]
"j12 , " & -- VDD[10]
"j10 , " & -- VDD[9]
"j8 , " & -- VDD[8]
"h13 , " & -- VDD[7]
"h11 , " & -- VDD[6]
"h9 , " & -- VDD[5]
"h7 , " & -- VDD[4]
"g14 , " & -- VDD[3]
"g12 , " & -- VDD[2]
"g10 , " & -- VDD[1]
"g8 ), " & -- VDD[0]
"SP_VDD :(w14 , " & -- SP_VDD[30]
"w10 , " & -- SP_VDD[29]
"v13 , " & -- SP_VDD[28]
"v11 , " & -- SP_VDD[27]
"v9 , " & -- SP_VDD[26]
"v7 , " & -- SP_VDD[25]
"t12 , " & -- SP_VDD[24]
"t8 , " & -- SP_VDD[23]
"p19 , " & -- SP_VDD[22]
"n18 , " & -- SP_VDD[21]
"m16 , " & -- SP_VDD[20]
"m2 , " & -- SP_VDD[19]
"l18 , " & -- SP_VDD[18]
"l3 , " & -- SP_VDD[17]
"k19 , " & -- SP_VDD[16]
"j18 , " & -- SP_VDD[15]
"j3 , " & -- SP_VDD[14]
"h16 , " & -- SP_VDD[13]
"h2 , " & -- SP_VDD[12]
"g18 , " & -- SP_VDD[11]
"g3 , " & -- SP_VDD[10]
"f5 , " & -- SP_VDD[9]
"e13 , " & -- SP_VDD[8]
"e3 , " & -- SP_VDD[7]
"d2 , " & -- SP_VDD[6]
"c14 , " & -- SP_VDD[5]
"c12 , " & -- SP_VDD[4]
"c10 , " & -- SP_VDD[3]
"c8 , " & -- SP_VDD[2]
"b15 , " & -- SP_VDD[1]
"b11 ), " & -- SP_VDD[0]
"SP_AVDD :(t14 , " & -- SP_AVDD[13]
"t10 , " & -- SP_AVDD[12]
"r13 , " & -- SP_AVDD[11]
"r11 , " & -- SP_AVDD[10]
"l15 , " & -- SP_AVDD[9]
"l6 , " & -- SP_AVDD[8]
"k16 , " & -- SP_AVDD[7]
"k5 , " & -- SP_AVDD[6]
"h15 , " & -- SP_AVDD[5]
"h5 , " & -- SP_AVDD[4]
"f16 , " & -- SP_AVDD[3]
"f11 , " & -- SP_AVDD[2]
"e11 , " & -- SP_AVDD[1]
"e9 ), " & -- SP_AVDD[0]
"REF_AVDD :(c26 , " & -- REF_AVDD[1]
"c24 ) " ; -- REF_AVDD[0]
attribute PORT_GROUPING of Tsi576 : entity is
"Differential_Current ( (SP0_TB_P, SP0_TB_N), " &
"(SP0_RB_P, SP0_RB_N), " &
"(SP0_TA_P, SP0_TA_N), " &
"(SP0_RA_P, SP0_RA_N), " &
"(SP0_TC_P, SP0_TC_N), " &
"(SP0_RC_P, SP0_RC_N), " &
"(SP0_TD_P, SP0_TD_N), " &
"(SP0_RD_P, SP0_RD_N), " &
"(SP2_TB_P, SP2_TB_N), " &
"(SP2_RB_P, SP2_RB_N), " &
"(SP2_TA_P, SP2_TA_N), " &
"(SP2_RA_P, SP2_RA_N), " &
"(SP4_TB_P, SP4_TB_N), " &
"(SP4_RB_P, SP4_RB_N), " &
"(SP4_TA_P, SP4_TA_N), " &
"(SP4_RA_P, SP4_RA_N), " &
"(SP6_TB_P, SP6_TB_N), " &
"(SP6_RB_P, SP6_RB_N), " &
"(SP6_TA_P, SP6_TA_N), " &
"(SP6_RA_P, SP6_RA_N), " &
"(SP6_TC_P, SP6_TC_N), " &
"(SP6_RC_P, SP6_RC_N), " &
"(SP6_TD_P, SP6_TD_N), " &
"(SP6_RD_P, SP6_RD_N), " &
"(SP10_TB_P, SP10_TB_N), " &
"(SP10_RB_P, SP10_RB_N), " &
"(SP10_TA_P, SP10_TA_N), " &
"(SP10_RA_P, SP10_RA_N), " &
"(SP12_TB_P, SP12_TB_N), " &
"(SP12_RB_P, SP12_RB_N), " &
"(SP12_TA_P, SP12_TA_N), " &
"(SP12_RA_P, SP12_RA_N)) " ;
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute COMPLIANCE_PATTERNS of Tsi576 : entity is
"(BCE) (1)";
attribute INSTRUCTION_LENGTH of Tsi576: entity is 61;
attribute INSTRUCTION_OPCODE of Tsi576: entity is
"IDCODE (1111111111111111111111111111111111111111111111111111111111110)," &
"BYPASS (0000000000000000000000000000000000000000000000000000000000000, 1111111111111111111111111111111111111111111111111111111111111)," &
"EXTEST (1111111111111111111111000000111111001111111111111111111101000)," &
"EXTEST_PULSE (1111111111111111111111000000111111001111111101111111111101000)," &
"EXTEST_TRAIN (1111111111111111111111000000111111001111111011111111111101000)," &
"SAMPLE (1111111111111111111111000000111111001111111111111111111111000)," &
"PRELOAD (1111111111111111111111000000111111001111111111111111111111000)," &
"CLAMP (1111111111111111111111111110111111001111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of Tsi576: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of Tsi576: entity is
"0010" & -- version
"0000010101110010" & -- part number
"00010110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of Tsi576: entity is
"BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," &
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS ( CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of Tsi576: entity is 183;
attribute BOUNDARY_REGISTER of Tsi576: entity is
-- num cell port function safe [ccell disval rslt]
" 182 (BC_1 , * , control , 0 ) ,"&
" 181 (AC_1 , SP0_TB_P , output3 , X , 182 , 0 , Z ),"&
" 180 (BC_4 , SP0_RB_P , observe_only , X ) ,"&
" 179 (BC_4 , SP0_RB_N , observe_only , X ) ,"&
" 178 (BC_1 , * , control , 0 ) ,"&
" 177 (AC_1 , SP0_TA_P , output3 , X , 178 , 0 , Z ),"&
" 176 (BC_4 , SP0_RA_P , observe_only , X ) ,"&
" 175 (BC_4 , SP0_RA_N , observe_only , X ) ,"&
" 174 (BC_1 , * , control , 0 ) ,"&
" 173 (AC_1 , SP0_TC_P , output3 , X , 174 , 0 , Z ),"&
" 172 (BC_4 , SP0_RC_P , observe_only , X ) ,"&
" 171 (BC_4 , SP0_RC_N , observe_only , X ) ,"&
" 170 (BC_1 , * , control , 0 ) ,"&
" 169 (AC_1 , SP0_TD_P , output3 , X , 170 , 0 , Z ),"&
" 168 (BC_4 , SP0_RD_P , observe_only , X ) ,"&
" 167 (BC_4 , SP0_RD_N , observe_only , X ) ,"&
" 166 (BC_1 , * , control , 0 ) ,"&
" 165 (AC_1 , SP2_TB_P , output3 , X , 166 , 0 , Z ),"&
" 164 (BC_4 , SP2_RB_P , observe_only , X ) ,"&
" 163 (BC_4 , SP2_RB_N , observe_only , X ) ,"&
" 162 (BC_1 , * , control , 0 ) ,"&
" 161 (AC_1 , SP2_TA_P , output3 , X , 162 , 0 , Z ),"&
" 160 (BC_4 , SP2_RA_P , observe_only , X ) ,"&
" 159 (BC_4 , SP2_RA_N , observe_only , X ) ,"&
" 158 (BC_0 , * , internal , 0 ),"&
" 157 (BC_0 , * , internal , 0 ),"&
" 156 (BC_0 , * , internal , 0 ),"&
" 155 (BC_0 , * , internal , 0 ),"&
" 154 (BC_0 , * , internal , 0 ),"&
" 153 (BC_0 , * , internal , 0 ),"&
" 152 (BC_0 , * , internal , 0 ),"&
" 151 (BC_0 , * , internal , 0 ),"&
" 150 (BC_1 , * , control , 0 ) ,"&
" 149 (AC_1 , SP4_TB_P , output3 , X , 150 , 0 , Z ),"&
" 148 (BC_4 , SP4_RB_P , observe_only , X ) ,"&
" 147 (BC_4 , SP4_RB_N , observe_only , X ) ,"&
" 146 (BC_1 , * , control , 0 ) ,"&
" 145 (AC_1 , SP4_TA_P , output3 , X , 146 , 0 , Z ),"&
" 144 (BC_4 , SP4_RA_P , observe_only , X ) ,"&
" 143 (BC_4 , SP4_RA_N , observe_only , X ) ,"&
" 142 (BC_0 , * , internal , 0 ),"&
" 141 (BC_0 , * , internal , 0 ),"&
" 140 (BC_0 , * , internal , 0 ),"&
" 139 (BC_0 , * , internal , 0 ),"&
" 138 (BC_0 , * , internal , 0 ),"&
" 137 (BC_0 , * , internal , 0 ),"&
" 136 (BC_0 , * , internal , 0 ),"&
" 135 (BC_0 , * , internal , 0 ),"&
" 134 (BC_1 , * , control , 0 ) ,"&
" 133 (AC_1 , SP6_TB_P , output3 , X , 134 , 0 , Z ),"&
" 132 (BC_4 , SP6_RB_P , observe_only , X ) ,"&
" 131 (BC_4 , SP6_RB_N , observe_only , X ) ,"&
" 130 (BC_1 , * , control , 0 ) ,"&
" 129 (AC_1 , SP6_TA_P , output3 , X , 130 , 0 , Z ),"&
" 128 (BC_4 , SP6_RA_P , observe_only , X ) ,"&
" 127 (BC_4 , SP6_RA_N , observe_only , X ) ,"&
" 126 (BC_1 , * , control , 0 ) ,"&
" 125 (AC_1 , SP6_TC_P , output3 , X , 126 , 0 , Z ),"&
" 124 (BC_4 , SP6_RC_P , observe_only , X ) ,"&
" 123 (BC_4 , SP6_RC_N , observe_only , X ) ,"&
" 122 (BC_1 , * , control , 0 ) ,"&
" 121 (AC_1 , SP6_TD_P , output3 , X , 122 , 0 , Z ),"&
" 120 (BC_4 , SP6_RD_P , observe_only , X ) ,"&
" 119 (BC_4 , SP6_RD_N , observe_only , X ) ,"&
" 118 (BC_0 , * , internal , 0 ),"&
" 117 (BC_0 , * , internal , 0 ),"&
" 116 (BC_0 , * , internal , 0 ),"&
" 115 (BC_0 , * , internal , 0 ),"&
" 114 (BC_0 , * , internal , 0 ),"&
" 113 (BC_0 , * , internal , 0 ),"&
" 112 (BC_0 , * , internal , 0 ),"&
" 111 (BC_0 , * , internal , 0 ),"&
" 110 (BC_0 , * , internal , 0 ),"&
" 109 (BC_0 , * , internal , 0 ),"&
" 108 (BC_0 , * , internal , 0 ),"&
" 107 (BC_0 , * , internal , 0 ),"&
" 106 (BC_0 , * , internal , 0 ),"&
" 105 (BC_0 , * , internal , 0 ),"&
" 104 (BC_0 , * , internal , 0 ),"&
" 103 (BC_0 , * , internal , 0 ),"&
" 102 (BC_1 , * , control , 0 ) ,"&
" 101 (AC_1 , SP10_TB_P , output3 , X , 102 , 0 , Z ),"&
" 100 (BC_4 , SP10_RB_P , observe_only , X ) ,"&
" 99 (BC_4 , SP10_RB_N , observe_only , X ) ,"&
" 98 (BC_1 , * , control , 0 ) ,"&
" 97 (AC_1 , SP10_TA_P , output3 , X , 98 , 0 , Z ),"&
" 96 (BC_4 , SP10_RA_P , observe_only , X ) ,"&
" 95 (BC_4 , SP10_RA_N , observe_only , X ) ,"&
" 94 (BC_0 , * , internal, 0 ),"&
" 93 (BC_0 , * , internal , 0 ),"&
" 92 (BC_0 , * , internal , 0 ),"&
" 91 (BC_0 , * , internal , 0 ),"&
" 90 (BC_0 , * , internal, 0 ),"&
" 89 (BC_0 , * , internal , 0 ),"&
" 88 (BC_0 , * , internal , 0 ),"&
" 87 (BC_0 , * , internal , 0 ),"&
" 86 (BC_1 , * , control , 0 ) ,"&
" 85 (AC_1 , SP12_TB_P , output3 , X , 86 , 0 , Z ),"&
" 84 (BC_4 , SP12_RB_P , observe_only , X ) ,"&
" 83 (BC_4 , SP12_RB_N , observe_only , X ) ,"&
" 82 (BC_1 , * , control , 0 ) ,"&
" 81 (AC_1 , SP12_TA_P , output3 , X , 82 , 0 , Z ),"&
" 80 (BC_4 , SP12_RA_P , observe_only , X ) ,"&
" 79 (BC_4 , SP12_RA_N , observe_only , X ) ,"&
" 78 (BC_0 , * , internal, 0 ),"&
" 77 (BC_0 , * , internal , 0 ),"&
" 76 (BC_0 , * , internal , 0 ),"&
" 75 (BC_0 , * , internal , 0 ),"&
" 74 (BC_0 , * , internal, 0 ),"&
" 73 (BC_0 , * , internal , 0 ),"&
" 72 (BC_0 , * , internal , 0 ),"&
" 71 (BC_0 , * , internal , 0 ),"&
" 70 (BC_0 , * , internal, 0 ),"&
" 69 (BC_0 , * , internal , 0 ),"&
" 68 (BC_0 , * , internal , 0 ),"&
" 67 (BC_0 , * , internal , 0 ),"&
" 66 (BC_0 , * , internal, 0 ),"&
" 65 (BC_0 , * , internal , 0 ),"&
" 64 (BC_0 , * , internal , 0 ),"&
" 63 (BC_0 , * , internal , 0 ),"&
" 62 (BC_0 , * , internal, 0 ),"&
" 61 (BC_0 , * , internal , 0 ),"&
" 60 (BC_0 , * , internal , 0 ),"&
" 59 (BC_0 , * , internal , 0 ),"&
" 58 (BC_0 , * , internal, 0 ),"&
" 57 (BC_0 , * , internal , 0 ),"&
" 56 (BC_0 , * , internal , 0 ),"&
" 55 (BC_0 , * , internal , 0 ),"&
" 54 (BC_4 , P_CLK , clock , X ) ,"&
" 53 (BC_2 , * , control , 0 ) ,"&
" 52 (LV_BC_7 , I2C_SCLK , bidir , X , 53 , 0 , Z ),"&
" 51 (BC_2 , * , control , 0 ) ,"&
" 50 (LV_BC_7 , I2C_SD , bidir , X , 51 , 0 , Z ),"&
" 49 (BC_2 , * , control , 0 ) ,"&
" 48 (LV_BC_7 , I2C_DISABLE , bidir , X , 49 , 0 , Z ),"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (LV_BC_7 , I2C_MA , bidir , X , 47 , 0 , Z ),"&
" 45 (LV_BC_7 , I2C_SA(1) , bidir , X , 47 , 0 , Z ),"&
" 44 (LV_BC_7 , I2C_SA(0) , bidir , X , 47 , 0 , Z ),"&
" 43 (LV_BC_7 , I2C_SEL , bidir , X , 47 , 0 , Z ),"&
" 42 (BC_2 , * , control , 0 ) ,"&
" 41 (LV_BC_7 , INT_B , bidir , X , 42 , 0 , Z ),"&
" 40 (BC_2 , * , control , 0 ) ,"&
" 39 (LV_BC_7 , SW_RST_B , bidir , X , 40 , 0 , Z ),"&
" 38 (BC_0 , * , internal , 0 ) ,"&
" 37 (BC_2 , * , control , 0 ) ,"&
" 36 (BC_2 , DO , output3 , X , 37 , 0 , Z ),"&
" 35 (BC_2 , * , control , 0 ) ,"&
" 34 (LV_BC_7 , SP_RX_SWAP , bidir , X , 35 , 0 , Z ),"&
" 33 (LV_BC_7 , SP_TX_SWAP , bidir , X , 35 , 0 , Z ),"&
" 32 (LV_BC_7 , SP_IO_SPEED(1) , bidir , X , 35 , 0 , Z ),"&
" 31 (LV_BC_7 , SP_IO_SPEED(0) , bidir , X , 35 , 0 , Z ),"&
" 30 (BC_2 , * , control , 0 ) ,"&
" 29 (LV_BC_7 , SP1_PWRDN , bidir , X , 30 , 0 , Z ),"&
" 28 (LV_BC_7 , SP2_PWRDN , bidir , X , 30 , 0 , Z ),"&
" 27 (LV_BC_7 , SP3_PWRDN , bidir , X , 30 , 0 , Z ),"&
" 26 (BC_2 , * , control , 0 ) ,"&
" 25 (LV_BC_7 , SP4_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 24 (LV_BC_7 , SP5_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 23 (LV_BC_7 , SP6_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 22 (LV_BC_7 , SP7_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 21 (BC_2 , * , control , 0 ) ,"&
" 20 (BC_0 , * , internal , 0 ),"&
" 19 (BC_0 , * , internal , 0 ),"&
" 18 (LV_BC_7 , SP10_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 17 (LV_BC_7 , SP11_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 16 (BC_2 , * , control , 0 ) ,"&
" 15 (LV_BC_7 , SP12_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 14 (LV_BC_7 , SP13_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 13 (BC_0 , * , internal , 0 ),"&
" 12 (BC_0 , * , internal , 0 ),"&
" 11 (LV_BC_7 , SP0_MODESEL , bidir , X , 30 , 0 , Z ),"&
" 10 (BC_0 , * , internal , 0 ) ,"&
" 9 (BC_0 , * , internal , 1 ),"&
" 8 (BC_2 , * , control , 0 ) ,"&
" 7 (BC_0 , * , internal , 1 ),"&
" 6 (LV_BC_7 , SP6_MODESEL , bidir , X , 8 , 0 , Z ),"&
" 5 (BC_0 , * , internal , 0 ),"&
" 4 (BC_0 , * , internal , 1 ),"&
" 3 (BC_0 , * , internal , 1 ),"&
" 2 (BC_0 , * , internal , 0 ),"&
" 1 (BC_2 , * , control , 0 ) ,"&
" 0 (LV_BC_7 , MCES , bidir , X , 1 , 0 , Z ) ";
attribute AIO_COMPONENT_CONFORMANCE of Tsi576: entity is "STD_1149_6_2003";
attribute AIO_Pin_Behavior of Tsi576: entity is
"SP0_TD_P;"&
"SP0_TC_P;"&
"SP0_TB_P;"&
"SP0_TA_P;"&
"SP2_TB_P;"&
"SP2_TA_P;"&
"SP4_TB_P;"&
"SP4_TA_P;"&
"SP6_TD_P;"&
"SP6_TC_P;"&
"SP6_TB_P;"&
"SP6_TA_P;"&
"SP10_TB_P;"&
"SP10_TA_P;"&
"SP12_TB_P;"&
"SP12_TA_P;"&
"SP0_RB_P[180] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RA_P[176] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RC_P[172] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RD_P[168] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RB_P[164] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RA_P[160] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RB_P[148] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RA_P[144] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RB_P[132] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RA_P[128] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RC_P[124] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RD_P[120] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP10_RB_P[100] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP10_RA_P[96] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP12_RB_P[84] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP12_RA_P[80] : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi576;
--package LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI));
--
--end LVS_BSCAN_CELLS;
