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BSDL File: Intel_7200_7300 Download View details  


-- ***************************************************************************
-- Dual-Core Intel(r) Xeon(r) Processor 7200 Series and
-- Quad-Core Intel(r) Xeon(r) Processor 7200 Series 
-- Boundary Scan Descriptor Language (BSDL)Model, Version 1.3
-- This version supports the E-0 stepping of the processor.
--
-- Information in this document is provided in connection with Intel products.
-- No license, express or implied, by estoppel or otherwise, to any
-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or other
-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- The Dual-Core Intel(r) Xeon(r) Processor 7200 Series and
-- Quad-Core Intel(r) Xeon(r) Processor 7200 Series may contain design
-- defects or errors known as errata which may cause the product to
-- deviate from publishedspecifications. Current characterized errata
-- are available on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Copyright (c) Intel Corporation 2007. Third-party brands and names are the
-- property of their respective owners.
-- ***************************************************************************

entity Intel_7200_7300 is

   generic(PHYSICAL_PIN_MAP : string := "FCMPGA6");

   port (
        A20MB           : in      bit;                          -- Compatibility - address 20 mask
        AB              : inout   bit_vector(39 downto 3);      -- Address       - address bus
        ADSB            : inout   bit;                          -- Request       - address strobe
        ADSTBB          : inout   bit_vector(1 downto 0);       -- Request       - address bus strobe
        APB             : inout   bit_vector(1 downto 0);       -- Address       - address bus parity
        BCLK            : in      bit_vector(1 downto 0);       -- Pwr/Clk       - system bus clock
        BINITB          : inout   bit;                          -- Error         - bus initialization error
        BNRB            : inout   bit;                          -- Arbitration   - block next request
        BPMB            : inout   bit_vector(5 downto 0);       -- Diagnostic    - performance monitoring break points
        BPMB_2          : inout   bit_vector(3 downto 0);       -- Diagnostic    - performance monitoring break points
        BPRIB           : in      bit;                          -- Arbitration   - priority agent bus arbitration
        BRB             : inout   bit_vector(1 downto 0);       -- Arbitration   - symmetric agent bus arbitration
        BSEL            : out     bit_vector(2 downto 0);       -- Pwr/Clk       - selects processor input clock frequency
        COMP            : linkage bit_vector(3 downto 0);       -- Pwr/Clk       - slew and impedence compensator
        DB              : inout   bit_vector(63 downto 0);      -- Data          - data bus
        DBSYB           : inout   bit;                          -- Data          - data bus busy
        DEFERB          : in      bit;                          -- Snoop         - defer signal
        DBIB            : inout   bit_vector(3 downto 0);       -- Data          - dynamic data bus inversion
        DPB             : inout   bit_vector(3 downto 0);       -- Data          - data bus parity
        DRDYB           : inout   bit;                          -- Data          - data phase data ready
        DSTBNB          : inout   bit_vector(3 downto 0);       -- Data          - data bus differential strobe
        DSTBPB          : inout   bit_vector(3 downto 0);       -- Data          - data bus differential strobe
        FERRB           : out     bit;                          -- Compatibility - floating point error, pending break event
        FORCEPRB        : in      bit;                          -- Pwr/Clk       - force thermal control circuit
        GTLREF_ADD_MID  : linkage bit;                          -- Analog Pin    - signal reference level for input address bus
        GTLREF_ADD_END  : linkage bit;                          -- Analog Pin    - signal reference level for input address bus
        GTLREF_DATA_MID : linkage bit;                          -- Analog Pin    - signal reference level for input data bus
        GTLREF_DATA_END : linkage bit;                          -- Analog Pin    - signal reference level for input data bus
        HITB            : inout   bit;                          -- Snoop         - snoop hit
        HITMB           : inout   bit;                          -- Snoop         - snoop hit modified
        IERRB           : out     bit;                          -- Error         - internal processor error
        IGNNEB          : in      bit;                          -- Compatibility - ignore numuric errors
        INITB           : in      bit;                          -- Exec Control  - processor initialization
        LINT0           : in      bit;                          -- APIC          - local APIC interrupt, INTR
        LINT1           : in      bit;                          -- APIC          - local APIC interrupt, NMI
        LL_ID           : out     bit_vector(1 downto 0);       -- Pwr/Clk       - loadline slope select
        LOCKB           : inout   bit;                          -- Arbitration   - locked transactions
        MCERRB          : inout   bit;                          -- Error         - machine check error
        PECI            : inout   bit;                          -- Pwr/Clk       - thermal monitor
        PROC_ID         : out     bit_vector(1 downto 0);       --               - processor identification
        PROCHOTB        : out     bit;                          -- Pwr/Clk       - thermal sensor
        PWRGOOD         : in      bit;                          -- Pwr/Clk       - system power good
        REQB            : inout   bit_vector(4 downto 0);       -- Request       - request command
        RESETB          : in      bit;                          -- Control       - system reset
        RSB             : in      bit_vector(2 downto 0);       -- Response      - response status
        RSPB            : in      bit;                          -- Response      - response status parity
        RSVD            : inout   bit_vector(23 downto 0);      -- Reserved      - reserved
        SKTOCCB         : out     bit;                          -- Socket occupied
        SM_CLK          : inout   bit;                          -- SMBus         - SMBus Clock
        SM_DAT          : inout   bit;                          -- SMBus         - SMBus Data
        SM_EP_A         : in      bit_vector(2 downto 0);       -- SMBus         - EEPROM Select Address
        SM_VCC          : in      bit_vector(1 downto 0);       -- Power
        SM_WP           : in      bit;                          -- SMBus         - Write Protect
        SMIB            : in      bit;                          -- Compatibility - system management interrupt
        STPCLKB         : in      bit;                          -- Pwr/Clk       - processor stop clock control
        TCK             : in      bit;                          -- Diagnostic    - tap clock
        TDI             : in      bit;                          -- Diagnostic    - tap data in
        TDO             : out     bit;                          -- Diagnostic    - tap data out  
        TESTHI0         : in      bit;                          -- Reserved      - reserved
        TESTHI1         : in      bit;                          -- Reserved      - reserved
        TESTIN1         : in      bit;                          -- Reserved      - reserved
	  TESTIN2         : in      bit;                          -- Reserved      - reserved	
	  THERMTRIPB      : out     bit;                          -- Pwr/Clk       - thermal sensor
        TMS             : in      bit;                          -- Diagnostic    - tap mode select
        TRDYB           : in      bit;                          -- Response      - target ready
        TRSTB           : in      bit;                          -- Diagnostic    - tap reset
 	  VCC			: linkage bit_vector(158 downto 0);	    -- Power
	  VCCPLL          : linkage bit;                          -- Power         - 
        VCC_SENSE       : linkage bit;                          -- Power         - Sense the die VCC power plane
        VCC_SENSE_2     : linkage bit;                          -- Power         - Sense the die VCC power plane
        VID             : out     bit_vector(6 downto 1);       -- Pwr/Clk       - power supply voltage selection
        VSS			: linkage bit_vector(180 downto 0);	    -- Power
	  VSS_SENSE       : linkage bit;                          -- Power         - Sense the die VSS power plane
        VSS_SENSE_2     : linkage bit;                          -- Power         - Sense the die VSS power plane
	  VTT			: linkage bit_vector(21 downto 0);	    -- Power
	  VTT_SEL		: out	  bit 
        );

  use STD_1149_1_1994.all;
  use Intel_7200_7300_cells.all;

  attribute COMPONENT_CONFORMANCE of Intel_7200_7300 : entity is "STD_1149_1_1993" ;

  attribute PIN_MAP of Intel_7200_7300 : entity is PHYSICAL_PIN_MAP;
  constant FCMPGA6 : PIN_MAP_STRING :=

-- Define PinOut

 "A20MB          :    F27,"                                    &
 "AB             : ( C16, B6, F22, F16, C8, C9, A7, A6, B7,"   &  -- 39 to 31
 "                   C11, D12, E13, B8, A9, D13, E14, C12,"    &  -- 30 to 23
 "                   B11, B10, A10, F15, D15, D16, C14, C15,"  &  -- 22 to 15
 "                   A12, B13, B14, B16, A13, D17, C17, A19,"  &  -- 14 to 7
 "                   C18, B18, A20, A22),"                     &  -- 6 to 3
 "ADSB           :    D19,"                                    &
 "ADSTBB         : ( F14, F17),"                               &  -- 1 to 0
 "APB            : ( D9, E10),"                                &  -- 1 to 0
 "BCLK           : ( W5, Y4),"                                 &  -- 1 to 0
 "BINITB         :    F11,"                                    &
 "BNRB           :    F20,"                                    &
 "BPMB           : ( E4, E8, F5, E7, F8, F6),"                 &  -- 5 to 0
 "BPMB_2         : ( AE3, AE2, AC1, AA4),"                     &  -- 3 to 0
 "BPRIB          :    D23,"                                    &
 "BRB            : (  F12, D20),"                              &  -- 1 to 0
 "BSEL           : ( Y31, AB3, AA3),"                          &  -- 2 to 0
 "COMP           : ( AE16, AE15, E16, D25),"                   &  -- 3 to 0
 "DB             : ( AB6, Y9, AA8, AC5, AC6, AE7, AD7, AC8,"   &  -- 63 to 56
 "                   AB10, AA10, AA11, AB13, AB12, AC14,"      &  -- 55 to 50
 "                   AA14, AA13, AC9, AD8, AD10, AE9, AC11,"   &  -- 49 to 43
 "                   AE10, AC12, AD11, AD14, AD13, AB15,"      &  -- 42 to 37
 "                   AD18, AE13, AC17, AA16, AB16, AB17,"      &  -- 36 to 31
 "                   AD19, AD21, AE20, AE22, AC21, AC20,"      &  -- 30 to 25
 "                   AA18, AC23, AE23, AD24, AC24, AE25,"      &  -- 24 to 19
 "                   AD25, AC26, AE26, AA19, AB19, AB22,"      &  -- 18 to 13
 "                   AB20, AA21, AA22, AB23, AB25, AB26,"      &  -- 12 to 7
 "                   AA24, Y23, AD27, AA25, Y24, AA27, Y26),"  &  -- 6 to 0
 "DBSYB          :    F18,"                                    &
 "DEFERB         :    C23,"                                    &
 "DBIB           : ( AB9, AE12, AD22, AC27),"                  &  -- 3 to 0
 "DPB            : ( AE17, AC15, AE19, AC18),"                 &  -- 3 to 0
 "DRDYB          :    E18,"                                    &
 "DSTBNB         : ( Y12, Y15, Y18, Y21),"                     &  -- 3 to 0
 "DSTBPB         : ( Y11, Y14, Y17, Y20),"                     &  -- 3 to 0
 "FERRB          :    E27,"                                    &
 "FORCEPRB       :    A15,"                                    &
 "GTLREF_ADD_MID :    F9,"                                     &
 "GTLREF_ADD_END :    F23,"                                    &
 "GTLREF_DATA_END:    W9,"                                     &
 "GTLREF_DATA_MID:    W23,"                                    &
 "HITB           :    E22,"                                    &
 "HITMB          :    A23,"                                    &
 "IERRB          :    E5,"                                     &
 "IGNNEB         :    C26,"                                    &
 "INITB          :    D6,"                                     &
 "LINT0          :    B24,"                                    &
 "LINT1          :    G23,"                                    &
 "LL_ID          : ( B28, B31),"                               &  -- 1 to 0
 "LOCKB          :    A17,"                                    &
 "MCERRB         :    D7,"                                     &
 "PECI           :    C28,"                                    &
 "PROC_ID        : ( B29, A30),"                               &  -- 1 to 0
 "PROCHOTB       :    B25,"                                    &
 "PWRGOOD        :   AB7,"                                     &
 "REQB           : ( B22, C20, C21, B21, B19),"                &  -- 4 to 0
 "RESETB         :    Y8,"                                     &
 "RSB            : (  F21, D22, E21),"                         &  -- 2 to 0
 "RSPB           :    C6,"                                     &
 "RSVD           : ( AE30, AE8, AD31, AD30, AD28, AD16, AD6, " &  -- 23 to 17 
 "		         AD4, AC30, AB4, AA28, AA5, Y29, Y28,"     &  -- 16 to 10
 "		         Y27, E2, D29, C31, D27, B30, B4, B1,"     &  -- 9  to 2
 "                   A31, A28),"                               &  -- 1 to 0
 "SKTOCCB        :    A3,"                                     &
 "SM_CLK         :   AC28,"                                    &
 "SM_DAT         :   AC29,"                                    & 
 "SM_EP_A        : ( AB28, AB29, AA29),"                       &  -- 2 to 0
 "SM_VCC         : ( AE29, AE28),"                             &  -- 1 to 0
 "SM_WP          :   AD29,"                                    &
 "SMIB           :    C27,"                                    &
 "STPCLKB        :    D4,"                                     &
 "TCK            :    E24,"                                    &
 "TDI            :    C24,"                                    &
 "TDO            :    E25,"                                    &
 "TESTIN1        :    D1,"                                     &
 "TESTIN2        :    C2,"                                     &
 "TESTHI0        :    A16,"                                    &
 "TESTHI1        :    W3,"                                     &
 "THERMTRIPB     :    F26,"                                    &
 "TMS            :    A25,"                                    &
 "TRDYB          :    E19,"                                    &
 "TRSTB          :    F24,"                                    &
 "VCC		     : (  A8, A14, A18, A24, B20, C4, C22, C30,"   &
 "                    D8, D14, D18, D24, D31, E6, E20, E26,"   &
 "                    E28, E30, F1, F4, F29, F31, G2, G4, G6," &
 "                    G8, G24, G26, G28, G30, H1, H3, H5, H7," &
 "                    H9, H23, H25, H27, H29, H31, J2, J4,"    &
 "                    J6, J8, J24, J26, J28, J30, K1, K3, K5," &
 "                    K7, K9, K23, K25, K27, K29, K31, L2,"    &
 "                    L4, L6, L8, L24, L26, L28, L30, M1,"     &
 "                    M3, M5, M7,M9, M23, M25, M27, M29,"      &  
 "		          M31, N1, N3, N5,N7, N9, N23, N25,"       &
 "		          N27, N29, N31, P2, P4P6, P8, P24, P26,"  &
 "	    	          P28, P30, R1, R3, R5, R7, R9, R23, R25," &
 "	    	          R27, R29, R31, T2, T4, T6, T8, T24, T26,"&
 "	    	          T28, T30, U1, U3, U5, U7, U9, U23, U25," &
 "	    	          U27, U29, U31, V2, V4, V6, V8, V24, V26,"&
 "	    	          V28, V30, W1, W25, W27, W29, W31, Y2,"   &
 "	                Y16, Y22, Y30, AA1, AA6, AA20, AA26,"    &
 "	    	          AA31, AB2, AB8, AB14, AB18, AB24, AB30," &
 "           	    AC3, AC16, AC22, AC31, AD2, AD20, AD26," &
 "                    AE14, AE18, AE24),                     " &
 "VCCPLL         :    AD1,"                                    &
 "VCC_SENSE      :    B27,"                                    &
 "VCC_SENSE_2    :    A26,"                                    &
 "VID            : ( C1, A1, B3, C3, D3, E3),"                 &  -- 6 to 1
 "VSS		     : ( A5, A11, A21, A27, A29, B2, B9, B15,"     &
 "		          B17, B23, C7, C13, C19, C25, C29, D2,"   &
 "       	          D5, D11, D21, D28, D30, E1, E9, E15,"    &
 "	   	          E17, E23, E29, E31, F2, F3, F7, F13,"    &
 "            	    F19, F25, F28, F30, G1, G3, G5, G9,"     &
 "	    	          G25, G27, G29, G31, H2, H4, H6, H8,"     & 
 "	     	          H24, H26, H28, H30, J1, J3, J5, J7, J9," &
 "	    	          J23, J25, J27, J29, J31, K2, K4, K6,"    &
 "	     	          K8, K24, K26, K28, K30, L1, L3, L5, L7," &
 "	     	          L9, L23, L25, L27, L29, L31, M2, M4,"    &
 "	    	          M6, M8, M24, M26, M28, M30, N2, N4, N6," &
 "	    	          N8, N24, N26, N28, N30, P1, P3, P5, P7," &
 "	    	          P9, P23, P25, P27, P29, P31, R2, R4,"    &
 "	    	          R6, R8, R24, R26, R28, R30, T1, T3, T5," &
 "	    	          T7, T9, T23, T25, T27, T29, T31, U2,"    &
 "	    	          U4, U6, U8, U24, U26, U28, U30, V1, V3," &
 "	    	          V5, V7, V9, V23, V25, V27, V29, V31,"    &
 "	     	          W2, W4, W24, W26, W28, W30, Y1, Y3, Y5," &
 "	     	          Y7, Y13, Y19, Y25, AA2, AA9, AA15,"      &
 "	     	          AA17, AA23, AA30, AB1, AB5, AB11, AB21," &
 "	     	          AB27, AB31, AC2, AC7, AC13, AC19, AC25," &
 "	      	    AD3, AD9, AD15, AD17, AD23, AE6, AE11,"  &
 "	      	    AE21, AE27),"                            &
 "VSS_SENSE      :    D26,"                                    &
 "VSS_SENSE_2    :    B26, "					         &
 "VTT_SEL	     :    A2, "					         &
 "VTT		     : ( A4, B5, B12, C5, C10, D10, E11, E12,"     &
 "	               F10, W6, W7, W8, Y6, Y10, AA7, AA12,"     &
 "	     	         AC4, AC10, AD5, AD12, AE4, AE5)";


--
-- Scan Port Identification
--

   attribute Tap_Scan_In    of  TDI   : signal is true;
   attribute Tap_Scan_Mode  of  TMS   : signal is true;
   attribute Tap_Scan_Out   of  TDO   : signal is true;
   attribute Tap_Scan_Reset of  TRSTB : signal is true;
   attribute Tap_Scan_Clock of  TCK   : signal is (16.0e6, both);
   attribute Instruction_Length of Intel_7200_7300: entity is 7;

   attribute Instruction_Opcode of Intel_7200_7300: entity is

      " EXTEST   ( 0000000 ),                                    " &
      " SAMPLE   ( 0000001 ),                                    " &
      " IDCODE   ( 0000010 ),                                    " &
      " CLAMP    ( 0000100 ),                                    " &
      " RUNBIST  ( 0000111 ),                                    " &
      " HIGHZ    ( 0001000 ),                                    " &
      " BYPASS   ( 1111111 ),                                    " &
      " Reserved ( 0000011, 0000101, 0000110, 0001001, 0001010,  " &
      "            0001011, 0001100, 0001101, 0001110, 0001111,  " &
      "            0010000, 0010001, 0010010, 0010011, 0010100,  " &
      "            0010101, 0010110, 0010111, 0011000, 0011001,  " &
      "            0011010, 0011011, 0011100, 0011101, 0011110,  " &
      "            0011111, 0100000, 0100001, 0100010, 0100011,  " &
      "            0100100, 0100101, 0100110, 0100111, 0101000,  " &
      "            0101001, 0101010, 0101011, 0101100, 0101101,  " &
      "            0101110, 0101111, 0110000, 0110001, 0110010,  " &
      "            0110011, 0110100, 0110101, 0110110, 0110111,  " &
      "            0111000, 0111001, 0111010, 0111011, 0111100,  " &
      "            0111101, 0111110, 0111111, 1000000, 1000001,  " &
      "            1000010, 1000011, 1000100, 1000101, 1000110,  " &
      "            1000111, 1001000, 1001001, 1001010, 1001011,  " &
      "            1001100, 1001101, 1001110, 1001111, 1010000,  " &
      "            1010001, 1010010, 1010011, 1010100, 1010101,  " &
      "            1010110, 1010111, 1011000, 1011001, 1011010,  " &
      "            1011011, 1011100, 1011101, 1011110, 1011111,  " &
      "            1100000, 1100001, 1100010, 1100011, 1100100,  " &
      "            1100101, 1100110, 1100111, 1101000, 1101001,  " &
      "            1101010, 1101011, 1101100, 1101101, 1101110,  " &
      "            1101111, 1110000, 1110001, 1110010, 1110011,  " &
      "            1110100, 1110101, 1110110, 1110111, 1111000,  " &
      "            1111001, 1111010, 1111011, 1111100, 1111101,  " &
      "            1111110                                      )" ;
     
  attribute Instruction_Capture of Intel_7200_7300: entity is "0000001";
  attribute Instruction_Private of Intel_7200_7300: entity is "Reserved";

--
-- Dual-Core Intel(r) Xeon(r) Processor 7200 Series and
-- Quad-Core Intel(r) Xeon(r) Processor 7200 Series E-0 IDCODE Register
--

  attribute Idcode_Register of Intel_7200_7300: entity is
          "1001"                  &  --version, E-0 step 
          "0000000001011100"      &  --part number
          "00000001001"           &  --manufacturers identity
          "1";                       --required by the standard

--
-- Dual-Core Intel(r) Xeon(r) Processor 7200 Series and
-- Quad-Core Intel(r) Xeon(r) Processor 7200 Series Data Register Access
--

  attribute Register_Access of Intel_7200_7300: entity is

            "BOUNDARY   (EXTEST, SAMPLE),       " &
            "DEVICE_ID  (IDCODE),               " &
            "BYPASS     (HIGHZ, BYPASS)";
--
-- Dual-Core Intel(r) Xeon(r) Processor 7200 Series and
-- Quad-Core Intel(r) Xeon(r) Processor 7200 Series Boundary Scan cells
--
--    BC_N : Control or bidir
--
--    Dual-Core Intel(r) Xeon(r) Processor 7200 Series and
--    Quad-Core Intel(r) Xeon(r) Processor 7200 Series Boundary Register Description
--    Cell 0 is closest to TDO
--

   attribute BOUNDARY_LENGTH of Intel_7200_7300: entity is 173;
   attribute BOUNDARY_REGISTER of Intel_7200_7300: entity is

--	num         cell   port       function safe [ccell disval rslt]

	"0         (BC_N, *,           control,  0           ),"&
	"1         (BC_N, BPMB(0),     bidir,    X,  0,  0, Z),"&
	"2         (BC_N, BPMB(2),     bidir,    X,  0,  0, Z),"&
	"3         (BC_N, BPMB(1),     bidir,    X,  0,  0, Z),"&
	"4         (BC_N, BPMB(4),     bidir,    X,  0,  0, Z),"&
	"5         (BC_N, BPMB(5),     bidir,    X,  0,  0, Z),"&
	"6         (BC_N, BPMB(3),     bidir,    X,  0,  0, Z),"&
	"7         (BC_N, BINITB,      bidir,    X,  0,  0, Z),"&
	"8         (BC_N, RSPB,        input,    1           ),"& 
	"9         (BC_N, APB(0),      bidir,    X,  0,  0, Z),"&
	"10        (BC_N, APB(1),      bidir,    X,  0,  0, Z),"&
	"11        (BC_N, AB(35),      bidir,    X,  0,  0, Z),"& 
	"12        (BC_N, AB(34),      bidir,    X,  0,  0, Z),"&
	"13        (BC_N, AB(33),      bidir,    X,  0,  0, Z),"&
	"14        (BC_N, AB(32),      bidir,    X,  0,  0, Z),"&
	"15        (BC_N, AB(30),      bidir,    X,  0,  0, Z),"&
	"16        (BC_N, AB(28),      bidir,    X,  0,  0, Z),"&
	"17        (BC_N, AB(31),      bidir,    X,  0,  0, Z),"&
	"18        (BC_N, AB(29),      bidir,    X,  0,  0, Z),"&
	"19        (BC_N, AB(39),      bidir,    X,  0,  0, Z),"&
	"20        (BC_N, AB(27),      bidir,    X,  0,  0, Z),"&
	"21        (BC_N, AB(26),      bidir,    X,  0,  0, Z),"&
	"22        (BC_N, AB(38),      bidir,    X,  0,  0, Z),"& 
	"23        (BC_N, ADSTBB(1),   bidir,    X,  0,  0, Z),"&
	"24        (BC_N, AB(21),      bidir,    X,  0,  0, Z),"&
	"25        (BC_N, AB(24),      bidir,    X,  0,  0, Z),"&
	"26        (BC_N, AB(20),      bidir,    X,  0,  0, Z),"&
	"27        (BC_N, AB(25),      bidir,    X,  0,  0, Z),"&
	"28        (BC_N, AB(18),      bidir,    X,  0,  0, Z),"&
	"29        (BC_N, AB(23),      bidir,    X,  0,  0, Z),"&
	"30        (BC_N, AB(19),      bidir,    X,  0,  0, Z),"&
	"31        (BC_N, AB(22),      bidir,    X,  0,  0, Z),"&
	"32        (BC_N, AB(17),      bidir,    X,  0,  0, Z),"&
	"33        (BC_N, AB(15),      bidir,    X,  0,  0, Z),"&
	"34        (BC_N, AB(16),      bidir,    X,  0,  0, Z),"&
	"35        (BC_N, AB(13),      bidir,    X,  0,  0, Z),"&
	"36        (BC_N, AB(11),      bidir,    X,  0,  0, Z),"&
	"37        (BC_N, AB(14),      bidir,    X,  0,  0, Z),"&
	"38        (BC_N, AB(12),      bidir,    X,  0,  0, Z),"&
	"39        (BC_N, AB(9),       bidir,    X,  0,  0, Z),"&
	"40        (BC_N, AB(8),       bidir,    X,  0,  0, Z),"&
	"41        (BC_N, AB(10),      bidir,    X,  0,  0, Z),"&
	"42        (BC_N, AB(36),      bidir,    X,  0,  0, Z),"&
	"43        (BC_N, AB(37),      bidir,    X,  0,  0, Z),"&
	"44        (BC_N, AB(7),       bidir,    X,  0,  0, Z),"&
	"45        (BC_N, ADSTBB(0),   bidir,    X,  0,  0, Z),"&
	"46        (BC_N, AB(4),       bidir,    X,  0,  0, Z),"&
	"47        (BC_N, REQB(0),     bidir,    X,  0,  0, Z),"&
	"48        (BC_N, AB(6),       bidir,    X,  0,  0, Z),"&
	"49        (BC_N, AB(5),       bidir,    X,  0,  0, Z),"&
	"50        (BC_N, REQB(2),     bidir,    X,  0,  0, Z),"&
	"51        (BC_N, AB(3),       bidir,    X,  0,  0, Z),"&
	"52        (BC_N, REQB(1),     bidir,    X,  0,  0, Z),"&
	"53        (BC_N, REQB(3),     bidir,    X,  0,  0, Z),"&
	"54        (BC_N, REQB(4),     bidir,    X,  0,  0, Z),"&
	"55        (BC_N, MCERRB,      bidir,    X,  0,  0, Z),"&
	"56        (BC_N, BRB(1),      bidir,    X,  0,  0, Z),"&
	"57        (BC_N, TRDYB,       input,    1           ),"&
	"58        (BC_N, BRB(0),      bidir,    X,  0,  0, Z),"&
	"59        (BC_N, ADSB,        bidir,    X,  0,  0, Z),"&
	"60        (BC_N, DBSYB,       bidir,    X,  0,  0, Z),"&
	"61        (BC_N, BNRB,        bidir,    X,  0,  0, Z),"&
	"62        (BC_N, HITMB,       bidir,    X,  0,  0, Z),"&
	"63        (BC_N, RSB(1),      input,    1           ),"&
	"64        (BC_N, RSB(0),      input,    1           ),"&
	"65        (BC_N, HITB,        bidir,    X,  0,  0, Z),"&
	"66        (BC_N, LOCKB,       bidir,    X,  0,  0, Z),"&
	"67        (BC_N, DEFERB,      input,    1           ),"&
	"68        (BC_N, BPRIB,       input,    1           ),"&
	"69        (BC_N, RSB(2),      input,    1           ),"&
	"70        (BC_N, RESETB,      input,    1           ),"&
	"71        (BC_N, PECI,        bidir,    X,  0,  0, Z),"&
	"72        (BC_N, *,           internal, 1           ),"&
	"73        (BC_N, IGNNEB,      input,    1           ),"&
	"74        (BC_N, STPCLKB,     input,    1           ),"&
	"75        (BC_N, INITB,       input,    1           ),"&
	"76        (BC_N, SMIB,        input,    1           ),"&
	"77        (BC_N, FERRB,       output3,  X,  0,  0, Z),"&
	"78        (BC_N, LINT0,       input,    1           ),"&
	"79        (BC_N, TESTHI0,     input,    1           ),"&
	"80        (BC_N, LINT1,       input,    1           ),"&
	"81        (BC_N, TESTHI1,     input,    1           ),"&
	"82        (BC_N, A20MB,       input,    1           ),"&
	"83        (BC_N, THERMTRIPB,  output3,  X,  0,  0, Z),"&
	"84        (BC_N, BCLK(0),     input,    1           ),"&
	"85        (BC_N, DB(62),      bidir,    X, 87,  0, Z),"&
	"86        (BC_N, DB(63),      bidir,    X, 87,  0, Z),"&
	"87        (BC_N, *,           control,  0           ),"&
	"88        (BC_N, DB(59),      bidir,    X, 87,  0, Z),"&
	"89        (BC_N, DB(60),      bidir,    X, 87,  0, Z),"&
	"90        (BC_N, DB(61),      bidir,    X, 87,  0, Z),"&
	"91        (BC_N, DB(56),      bidir,    X, 87,  0, Z),"&
	"92        (BC_N, DBIB(3),     bidir,    X, 87,  0, Z),"&
	"93        (BC_N, DB(58),      bidir,    X, 87,  0, Z),"&
	"94        (BC_N, DB(57),      bidir,    X, 87,  0, Z),"&
	"95        (BC_N, DSTBNB(3),   bidir,    X, 87,  0, Z),"&
	"96        (BC_N, DSTBPB(3),   bidir,    X, 87,  0, Z),"&
	"97        (BC_N, DB(54),      bidir,    X, 87,  0, Z),"&
	"98        (BC_N, DB(50),      bidir,    X, 87,  0, Z),"&
	"99        (BC_N, DB(55),      bidir,    X, 87,  0, Z),"&
	"100       (BC_N, DB(53),      bidir,    X, 87,  0, Z),"&
	"101       (BC_N, DB(49),      bidir,    X, 87,  0, Z),"&
	"102       (BC_N, DB(48),      bidir,    X, 87,  0, Z),"&
	"103       (BC_N, DB(51),      bidir,    X, 87,  0, Z),"&
	"104       (BC_N, DB(52),      bidir,    X, 87,  0, Z),"&
	"105       (BC_N, DB(45),      bidir,    X, 87,  0, Z),"&
	"106       (BC_N, DB(47),      bidir,    X, 87,  0, Z),"&
	"107       (BC_N, DB(44),      bidir,    X, 87,  0, Z),"&
	"108       (BC_N, DB(43),      bidir,    X, 87,  0, Z),"&
	"109       (BC_N, DB(46),      bidir,    X, 87,  0, Z),"&
	"110       (BC_N, DB(42),      bidir,    X, 87,  0, Z),"&
	"111       (BC_N, DBIB(2),     bidir,    X, 87,  0, Z),"&
	"112       (BC_N, DB(41),      bidir,    X, 87,  0, Z),"&
	"113       (BC_N, DB(40),      bidir,    X, 87,  0, Z),"&
	"114       (BC_N, DSTBNB(2),   bidir,    X, 87,  0, Z),"&
	"115       (BC_N, DSTBPB(2),   bidir,    X, 87,  0, Z),"&
	"116       (BC_N, DB(35),      bidir,    X, 87,  0, Z),"&
	"117       (BC_N, DB(39),      bidir,    X, 87,  0, Z),"&
	"118       (BC_N, DB(38),      bidir,    X, 87,  0, Z),"&
	"119       (BC_N, DB(36),      bidir,    X, 87,  0, Z),"&
	"120       (BC_N, DB(34),      bidir,    X, 87,  0, Z),"&
	"121       (BC_N, DB(37),      bidir,    X, 87,  0, Z),"&
	"122       (BC_N, DB(32),      bidir,    X, 87,  0, Z),"&
	"123       (BC_N, DB(33),      bidir,    X, 87,  0, Z),"&
	"124       (BC_N, DPB(3),      bidir,    X, 87,  0, Z),"&
	"125       (BC_N, DPB(0),      bidir,    X, 87,  0, Z),"&
	"126       (BC_N, DPB(2),      bidir,    X, 87,  0, Z),"&
	"127       (BC_N, DPB(1),      bidir,    X, 87,  0, Z),"&
	"128       (BC_N, DB(31),      bidir,    X, 87,  0, Z),"&
	"129       (BC_N, DB(30),      bidir,    X, 87,  0, Z),"&
	"130       (BC_N, DB(28),      bidir,    X, 87,  0, Z),"&
	"131       (BC_N, DB(25),      bidir,    X, 87,  0, Z),"&
	"132       (BC_N, DB(26),      bidir,    X, 87,  0, Z),"&
	"133       (BC_N, DB(29),      bidir,    X, 87,  0, Z),"&
	"134       (BC_N, DB(22),      bidir,    X, 87,  0, Z),"&
	"135       (BC_N, DB(24),      bidir,    X, 87,  0, Z),"&
	"136       (BC_N, DB(27),      bidir,    X, 87,  0, Z),"&
	"137       (BC_N, DSTBNB(1),   bidir,    X, 87,  0, Z),"&
	"138       (BC_N, DSTBPB(1),   bidir,    X, 87,  0, Z),"&
	"139       (BC_N, DB(23),      bidir,    X, 87,  0, Z),"&
	"140       (BC_N, DB(21),      bidir,    X, 87,  0, Z),"&
	"141       (BC_N, DBIB(1),     bidir,    X, 87,  0, Z),"&
	"142       (BC_N, DB(19),      bidir,    X, 87,  0, Z),"&
	"143       (BC_N, DB(18),      bidir,    X, 87,  0, Z),"&
	"144       (BC_N, DB(20),      bidir,    X, 87,  0, Z),"&
	"145       (BC_N, DB(17),      bidir,    X, 87,  0, Z),"&
	"146       (BC_N, DB(16),      bidir,    X, 87,  0, Z),"&
	"147       (BC_N, DB(15),      bidir,    X, 87,  0, Z),"&
	"148       (BC_N, DB(12),      bidir,    X, 87,  0, Z),"&
	"149       (BC_N, DB(14),      bidir,    X, 87,  0, Z),"&
	"150       (BC_N, DB(13),      bidir,    X, 87,  0, Z),"&
	"151       (BC_N, DB(11),      bidir,    X, 87,  0, Z),"&
	"152       (BC_N, DB(9),       bidir,    X, 87,  0, Z),"&
	"153       (BC_N, DB(8),       bidir,    X, 87,  0, Z),"&
	"154       (BC_N, DB(10),      bidir,    X, 87,  0, Z),"&
	"155       (BC_N, DBIB(0),     bidir,    X, 87,  0, Z),"&
	"156       (BC_N, DSTBNB(0),   bidir,    X, 87,  0, Z),"&
	"157       (BC_N, DSTBPB(0),   bidir,    X, 87,  0, Z),"&
	"158       (BC_N, DB(6),       bidir,    X, 87,  0, Z),"&
	"159       (BC_N, DB(5),       bidir,    X, 87,  0, Z),"&
	"160       (BC_N, DB(7),       bidir,    X, 87,  0, Z),"&
	"161       (BC_N, DB(3),       bidir,    X, 87,  0, Z),"&
	"162       (BC_N, DB(2),       bidir,    X, 87,  0, Z),"&
	"163       (BC_N, DB(4),       bidir,    X, 87,  0, Z),"&
	"164       (BC_N, DB(1),       bidir,    X, 87,  0, Z),"&
	"165       (BC_N, *,           internal, X           ),"&
	"166       (BC_N, DB(0),       bidir,    X, 87,  0, Z),"&
	"167       (BC_N, DRDYB,       bidir,    X, 87,  0, Z),"&
	"168       (BC_N, RSVD(5),     bidir,    X, 87,  0, Z),"& 
	"169       (BC_N, RSVD(4),     bidir,    X, 87,  0, Z),"& 
	"170       (BC_N, PROCHOTB,    output3,  X, 87,  0, Z),"&
	"171       (BC_N, IERRB,       output3,  X, 87,  0, Z),"&
	"172       (BC_N, *,           internal, 1           )";

end Intel_7200_7300;


This library contains 7815 BSDL files (for 6182 distinct entities) from 66 vendors
Last BSDL model (PIC24FJ64GA002) was added on Nov 10, 2017 08:41
info@bsdl.info