--$ XILINX$RCSfile: xcs05xl_pc84.bsd,v $
--$ XILINX$Revision: 1.3 $
--
-- BSDL file for device XCS05XL, package PC84
-- Xilinx, Inc. $State: FINAL $ $Date: 2002-01-29 14:11:29-08 $
-- Generated by createBSDL 2.10
--
-- For technical support, contact Xilinx as follows:
-- North America 1-800-255-7778 hotline@xilinx.com
-- United Kingdom +44 870 7350 610 eurosupport@xilinx.com
-- France (33) 1 3463 0100 eurosupport@xilinx.com
-- Germany (49) 89 991 54930 eurosupport@xilinx.com
-- Japan (81) 3-3297-9163 jhotline@xilinx.com
--
-- BSDL verified to conform to 1149.1b-1994 syntax. This device has been
-- tested by the Intellitech 1149.1 Verification Lab using the Intellitech
-- Eclipse(TM) Scan Diagnostic Tool and the Intellitech RCT(TM). This
-- device has been verified to operate according to the BSDL provided,
-- and is compatible with the IEEE 1149.1 standard when the operating
-- instructions in the BSDL are followed.
-- PH: 603-868-7116 or email: scansupport@intellitech.com
--
-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below. Many of these changes are demonstrated by commented-out template
-- lines preceeding the lines they would replace:
--
-- 1. Enable USER instructions as appropriate (see below).
-- 2. For inputs using uncontrolled paths (e.g. PGCK, SGCK), change
-- boundary cell function from 'input' to 'clock' or 'observe_only'.
-- 3. Set disable result of all pads as configured.
-- 4. Set safe state of boundary cells as necessary.
-- 5. Set safe state of INIT output to X, or as necessary (see below).
-- 6. Rename entity if necessary to avoid name collisions.
-- 7. Change INIT port direction from "in" to "inout" (see below).
-- 8. Change COMPLIANCE_PATTERNS to "(LPWRB,PROGRAM) (11)" (see below).
-- 9. Change INIT boundary cells from internal to controlr, output3,
-- and input, respectively (see below).
-- 10. Remove the design warning regarding keeping INIT low.
--
-- NOTE: Post-configuration JTAG is available only if the BSCAN symbol
-- is instantiated in the FPGA design.
-- NOTE: PULLUP symbols must be instantiated on the TMS and TDI pins
-- in the FPGA design to comply with IEEE Std. 1149.1-1993.
entity XCS05XL_PC84 is
generic (PHYSICAL_PIN_MAP : string := "PC84" );
port (
CCLK: linkage bit;
DONE: linkage bit;
GND: linkage bit_vector (1 to 8);
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line so
-- that INIT is of type inout.
-- INIT: inout bit;
INIT: in bit;
IO2: inout bit;
IO3: inout bit;
IO6: inout bit;
IO7: inout bit;
IO10: inout bit;
IO11: inout bit;
IO12: inout bit;
IO13: inout bit;
IO17: inout bit;
IO18: inout bit;
IO23: inout bit;
IO27: inout bit;
IO28: inout bit;
IO31: inout bit;
IO32: inout bit;
IO36: inout bit;
IO37: inout bit;
IO39: inout bit;
IO41: inout bit;
IO42: inout bit;
IO49: inout bit;
IO50: inout bit;
IO52: inout bit;
IO54: inout bit;
IO55: inout bit;
IO59: inout bit;
IO63: inout bit;
IO64: inout bit;
IO68: inout bit;
IO69: inout bit;
IO71: inout bit;
IO72: inout bit;
IO73: inout bit;
IO74: inout bit;
IO80: inout bit;
IO81: inout bit;
IO82: inout bit;
IO86: inout bit;
IO87: inout bit;
IO90: inout bit;
IO91: inout bit;
IO94: inout bit;
IO95: inout bit;
IO98: inout bit;
IO99: inout bit;
IO102: inout bit;
IO103: inout bit;
IO104: inout bit;
IO105: inout bit;
IO111: inout bit;
IO112: inout bit;
IO113: inout bit;
IO114: inout bit;
IO117: inout bit;
IO118: inout bit;
IO121: inout bit;
IO122: inout bit;
LPWRB: in bit;
M0: in bit;
M1: inout bit;
PROGRAM: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
VCC: linkage bit_vector (1 to 8)
); --end port list
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of XCS05XL_PC84 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of XCS05XL_PC84 : entity is PHYSICAL_PIN_MAP;
constant PC84: PIN_MAP_STRING:=
"CCLK:P73," &
"DONE:P53," &
"GND:(P12,P21,P31,P43,P52,P64,P76,P1)," &
"INIT:P41," &
"IO2:P3," &
"IO3:P4," &
"IO6:P5," &
"IO7:P6," &
"IO10:P7," &
"IO11:P8," &
"IO12:P9," &
"IO13:P10," &
"IO17:P13," &
"IO18:P14," &
"IO23:P18," &
"IO27:P19," &
"IO28:P20," &
"IO31:P23," &
"IO32:P24," &
"IO36:P25," &
"IO37:P26," &
"IO39:P27," &
"IO41:P28," &
"IO42:P29," &
"IO49:P35," &
"IO50:P36," &
"IO52:P37," &
"IO54:P38," &
"IO55:P39," &
"IO59:P40," &
"IO63:P44," &
"IO64:P45," &
"IO68:P46," &
"IO69:P47," &
"IO71:P48," &
"IO72:P49," &
"IO73:P50," &
"IO74:P51," &
"IO80:P56," &
"IO81:P57," &
"IO82:P58," &
"IO86:P59," &
"IO87:P60," &
"IO90:P61," &
"IO91:P62," &
"IO94:P65," &
"IO95:P66," &
"IO98:P67," &
"IO99:P68," &
"IO102:P69," &
"IO103:P70," &
"IO104:P71," &
"IO105:P72," &
"IO111:P77," &
"IO112:P78," &
"IO113:P79," &
"IO114:P80," &
"IO117:P81," &
"IO118:P82," &
"IO121:P83," &
"IO122:P84," &
"LPWRB:P34," &
"M0:P32," &
"M1:P30," &
"PROGRAM:P55," &
"TCK:P16," &
"TDI:P15," &
"TDO:P75," &
"TMS:P17," &
"VCC:(P2,P11,P22,P33,P42,P54,P63,P74)";
--end pin map
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.0e6, LOW);
-- This is conservative. Real max is expected to be (~5MHz, BOTH).
attribute COMPLIANCE_PATTERNS of XCS05XL_PC84 : entity is
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the corresponding line
-- below.
-- "(PROGRAM,LPWRB) (11)";
--
-- NOTE: If INIT has been high or floating since the later of power-on
-- and the last rising transition of PROGRAM, then the device may
-- be in configuration mode in which case some JTAG instructions
-- will not be available.
"(INIT,PROGRAM,LPWRB) (011)";
attribute INSTRUCTION_LENGTH of XCS05XL_PC84 : entity is 3;
attribute INSTRUCTION_OPCODE of XCS05XL_PC84 : entity is
"SAMPLE (001)," & -- Internal capture not valid until after config
"IDCODE (110)," &
"READBACK (100)," & -- Not available during configuration
"CONFIGURE (101)," & -- Not available during configuration
"USER2 (011)," & -- Not available until after configuration
"USER1 (010)," & -- Not available until after configuration
"EXTEST (000)," & -- Not available during configuration
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of XCS05XL_PC84 : entity is "X01";
-- MSB of instruction capture is low during configuration.
-- If the device is configured, and a USER instruction is implemented
-- and not private to the FPGA designer, then it should be removed
-- from INSTRUCTION_PRIVATE, and the target register should be defined
-- in REGISTER_ACCESS.
attribute INSTRUCTION_PRIVATE of XCS05XL_PC84 : entity is
"USER1," &
"USER2," &
"READBACK," &
"CONFIGURE";
attribute IDCODE_REGISTER of XCS05XL_PC84 : entity is
"XXXX" & -- version
"0000010" & -- family
"000001010" & -- array size
"00001001001" & -- manufacturer
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of XCS05XL_PC84 : entity is
-- "<reg_name>[<length>] (USER1)," &
-- "<reg_name>[<length>] (USER2)," &
"BYPASS (BYPASS)," &
"DEVICE_ID (IDCODE)," &
"BOUNDARY (SAMPLE,EXTEST)";
attribute BOUNDARY_LENGTH of XCS05XL_PC84 : entity is 247;
attribute BOUNDARY_REGISTER of XCS05XL_PC84 : entity is
-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
" 0 (BC_1, *, internal, X)," &
" 1 (BC_1, *, internal, X)," &
" 2 (BC_1, *, controlr, 1)," &
" 3 (BC_1, IO111, output3, X, 2, 1, PULL1)," &
" 4 (BC_1, IO111, input, X)," &
" 5 (BC_1, *, controlr, 1)," &
" 6 (BC_1, IO112, output3, X, 5, 1, PULL1)," &
" 7 (BC_1, IO112, input, X)," &
" 8 (BC_1, *, controlr, 1)," &
" 9 (BC_1, IO113, output3, X, 8, 1, PULL1)," &
" 10 (BC_1, IO113, input, X)," &
" 11 (BC_1, *, controlr, 1)," &
" 12 (BC_1, IO114, output3, X, 11, 1, PULL1)," &
" 13 (BC_1, IO114, input, X)," &
" 14 (BC_1, *, controlr, 1)," &
" 15 (BC_1, IO117, output3, X, 14, 1, PULL1)," &
" 16 (BC_1, IO117, input, X)," &
" 17 (BC_1, *, controlr, 1)," &
" 18 (BC_1, IO118, output3, X, 17, 1, PULL1)," &
" 19 (BC_1, IO118, input, X)," &
" 20 (BC_1, *, internal, 1)," & -- IO119.T
" 21 (BC_1, *, internal, X)," & -- IO119.O
" 22 (BC_1, *, internal, X)," & -- IO119.I
" 23 (BC_1, *, internal, 1)," & -- IO120.T
" 24 (BC_1, *, internal, X)," & -- IO120.O
" 25 (BC_1, *, internal, X)," & -- IO120.I
" 26 (BC_1, *, controlr, 1)," &
" 27 (BC_1, IO121, output3, X, 26, 1, PULL1)," &
" 28 (BC_1, IO121, input, X)," &
" 29 (BC_1, *, controlr, 1)," &
" 30 (BC_1, IO122, output3, X, 29, 1, PULL1)," &
" 31 (BC_1, IO122, input, X)," &
" 32 (BC_1, *, controlr, 1)," &
" 33 (BC_1, IO2, output3, X, 32, 1, PULL1)," &
" 34 (BC_1, IO2, input, X)," &
" 35 (BC_1, *, controlr, 1)," &
" 36 (BC_1, IO3, output3, X, 35, 1, PULL1)," &
" 37 (BC_1, IO3, input, X)," &
" 38 (BC_1, *, internal, 1)," & -- IO4.T
" 39 (BC_1, *, internal, X)," & -- IO4.O
" 40 (BC_1, *, internal, X)," & -- IO4.I
" 41 (BC_1, *, internal, 1)," & -- IO5.T
" 42 (BC_1, *, internal, X)," & -- IO5.O
" 43 (BC_1, *, internal, X)," & -- IO5.I
" 44 (BC_1, *, controlr, 1)," &
" 45 (BC_1, IO6, output3, X, 44, 1, PULL1)," &
" 46 (BC_1, IO6, input, X)," &
" 47 (BC_1, *, controlr, 1)," &
" 48 (BC_1, IO7, output3, X, 47, 1, PULL1)," &
" 49 (BC_1, IO7, input, X)," &
" 50 (BC_1, *, controlr, 1)," &
" 51 (BC_1, IO10, output3, X, 50, 1, PULL1)," &
" 52 (BC_1, IO10, input, X)," &
" 53 (BC_1, *, controlr, 1)," &
" 54 (BC_1, IO11, output3, X, 53, 1, PULL1)," &
" 55 (BC_1, IO11, input, X)," &
" 56 (BC_1, *, controlr, 1)," &
" 57 (BC_1, IO12, output3, X, 56, 1, PULL1)," &
" 58 (BC_1, IO12, input, X)," &
" 59 (BC_1, *, controlr, 1)," &
" 60 (BC_1, IO13, output3, X, 59, 1, PULL1)," &
" 61 (BC_1, IO13, input, X)," &
" 62 (BC_1, *, controlr, 1)," &
" 63 (BC_1, IO17, output3, X, 62, 1, PULL1)," &
" 64 (BC_1, IO17, input, X)," &
" 65 (BC_1, *, controlr, 1)," &
" 66 (BC_1, IO18, output3, X, 65, 1, PULL1)," &
" 67 (BC_1, IO18, input, X)," &
" 68 (BC_1, *, internal, X)," &
" 69 (BC_1, *, internal, X)," &
" 70 (BC_1, *, internal, X)," &
" 71 (BC_1, *, internal, X)," &
" 72 (BC_1, *, internal, X)," &
" 73 (BC_1, *, internal, X)," &
" 74 (BC_1, *, internal, X)," &
" 75 (BC_1, *, internal, X)," &
" 76 (BC_1, *, internal, X)," &
" 77 (BC_1, *, controlr, 1)," &
" 78 (BC_1, IO23, output3, X, 77, 1, PULL1)," &
" 79 (BC_1, IO23, input, X)," &
" 80 (BC_1, *, internal, 1)," & -- IO25.T
" 81 (BC_1, *, internal, X)," & -- IO25.O
" 82 (BC_1, *, internal, X)," & -- IO25.I
" 83 (BC_1, *, internal, 1)," & -- IO26.T
" 84 (BC_1, *, internal, X)," & -- IO26.O
" 85 (BC_1, *, internal, X)," & -- IO26.I
" 86 (BC_1, *, controlr, 1)," &
" 87 (BC_1, IO27, output3, X, 86, 1, PULL1)," &
" 88 (BC_1, IO27, input, X)," &
" 89 (BC_1, *, controlr, 1)," &
" 90 (BC_1, IO28, output3, X, 89, 1, PULL1)," &
" 91 (BC_1, IO28, input, X)," &
" 92 (BC_1, *, controlr, 1)," &
" 93 (BC_1, IO31, output3, X, 92, 1, PULL1)," &
" 94 (BC_1, IO31, input, X)," &
" 95 (BC_1, *, controlr, 1)," &
" 96 (BC_1, IO32, output3, X, 95, 1, PULL1)," &
" 97 (BC_1, IO32, input, X)," &
" 98 (BC_1, *, internal, 1)," & -- IO33.T
" 99 (BC_1, *, internal, X)," & -- IO33.O
" 100 (BC_1, *, internal, X)," & -- IO33.I
" 101 (BC_1, *, internal, 1)," & -- IO34.T
" 102 (BC_1, *, internal, X)," & -- IO34.O
" 103 (BC_1, *, internal, X)," & -- IO34.I
" 104 (BC_1, *, controlr, 1)," &
" 105 (BC_1, IO36, output3, X, 104, 1, PULL1)," &
" 106 (BC_1, IO36, input, X)," &
" 107 (BC_1, *, controlr, 1)," &
" 108 (BC_1, IO37, output3, X, 107, 1, PULL1)," &
" 109 (BC_1, IO37, input, X)," &
" 110 (BC_1, *, controlr, 1)," &
" 111 (BC_1, IO39, output3, X, 110, 1, PULL1)," &
" 112 (BC_1, IO39, input, X)," &
" 113 (BC_1, *, internal, 1)," & -- IO40.T
" 114 (BC_1, *, internal, X)," & -- IO40.O
" 115 (BC_1, *, internal, X)," & -- IO40.I
" 116 (BC_1, *, controlr, 1)," &
" 117 (BC_1, IO41, output3, X, 116, 1, PULL1)," &
" 118 (BC_1, IO41, input, X)," &
" 119 (BC_1, *, controlr, 1)," &
" 120 (BC_1, IO42, output3, X, 119, 1, PULL1)," &
" 121 (BC_1, IO42, input, X)," &
" 122 (BC_1, *, controlr, 1)," &
" 123 (BC_1, M1, output3, X, 122, 1, PULL1)," &
" 124 (BC_1, M1, input, X)," &
" 125 (BC_1, M0, input, X)," &
" 126 (BC_1, *, controlr, 1)," &
" 127 (BC_1, IO49, output3, X, 126, 1, PULL1)," &
" 128 (BC_1, IO49, input, X)," &
" 129 (BC_1, *, controlr, 1)," &
" 130 (BC_1, IO50, output3, X, 129, 1, PULL1)," &
" 131 (BC_1, IO50, input, X)," &
" 132 (BC_1, *, internal, 1)," & -- IO51.T
" 133 (BC_1, *, internal, X)," & -- IO51.O
" 134 (BC_1, *, internal, X)," & -- IO51.I
" 135 (BC_1, *, controlr, 1)," &
" 136 (BC_1, IO52, output3, X, 135, 1, PULL1)," &
" 137 (BC_1, IO52, input, X)," &
" 138 (BC_1, *, controlr, 1)," &
" 139 (BC_1, IO54, output3, X, 138, 1, PULL1)," &
" 140 (BC_1, IO54, input, X)," &
" 141 (BC_1, *, controlr, 1)," &
" 142 (BC_1, IO55, output3, X, 141, 1, PULL1)," &
" 143 (BC_1, IO55, input, X)," &
" 144 (BC_1, *, internal, 1)," & -- IO57.T
" 145 (BC_1, *, internal, X)," & -- IO57.O
" 146 (BC_1, *, internal, X)," & -- IO57.I
" 147 (BC_1, *, internal, 1)," & -- IO58.T
" 148 (BC_1, *, internal, X)," & -- IO58.O
" 149 (BC_1, *, internal, X)," & -- IO58.I
" 150 (BC_1, *, controlr, 1)," &
" 151 (BC_1, IO59, output3, X, 150, 1, PULL1)," &
" 152 (BC_1, IO59, input, X)," &
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line.
-- Repeat for registers 153 through 155.
-- " 153 (BC_1, *, controlr, 1)," &
" 153 (BC_1, *, internal, 1)," &
-- " 154 (BC_1, INIT, output3, X, 153, 1, PULL1)," &
" 154 (BC_1, *, internal, 0)," &
-- " 155 (BC_1, INIT, input, X)," &
" 155 (BC_1, *, internal, X)," &
" 156 (BC_1, *, controlr, 1)," &
" 157 (BC_1, IO63, output3, X, 156, 1, PULL1)," &
" 158 (BC_1, IO63, input, X)," &
" 159 (BC_1, *, controlr, 1)," &
" 160 (BC_1, IO64, output3, X, 159, 1, PULL1)," &
" 161 (BC_1, IO64, input, X)," &
" 162 (BC_1, *, internal, 1)," & -- IO65.T
" 163 (BC_1, *, internal, X)," & -- IO65.O
" 164 (BC_1, *, internal, X)," & -- IO65.I
" 165 (BC_1, *, internal, 1)," & -- IO66.T
" 166 (BC_1, *, internal, X)," & -- IO66.O
" 167 (BC_1, *, internal, X)," & -- IO66.I
" 168 (BC_1, *, controlr, 1)," &
" 169 (BC_1, IO68, output3, X, 168, 1, PULL1)," &
" 170 (BC_1, IO68, input, X)," &
" 171 (BC_1, *, controlr, 1)," &
" 172 (BC_1, IO69, output3, X, 171, 1, PULL1)," &
" 173 (BC_1, IO69, input, X)," &
" 174 (BC_1, *, controlr, 1)," &
" 175 (BC_1, IO71, output3, X, 174, 1, PULL1)," &
" 176 (BC_1, IO71, input, X)," &
" 177 (BC_1, *, controlr, 1)," &
" 178 (BC_1, IO72, output3, X, 177, 1, PULL1)," &
" 179 (BC_1, IO72, input, X)," &
" 180 (BC_1, *, controlr, 1)," &
" 181 (BC_1, IO73, output3, X, 180, 1, PULL1)," &
" 182 (BC_1, IO73, input, X)," &
" 183 (BC_1, *, controlr, 1)," &
" 184 (BC_1, IO74, output3, X, 183, 1, PULL1)," &
" 185 (BC_1, IO74, input, X)," &
" 186 (BC_1, *, controlr, 1)," &
" 187 (BC_1, IO80, output3, X, 186, 1, PULL1)," &
" 188 (BC_1, IO80, input, X)," &
" 189 (BC_1, *, controlr, 1)," &
" 190 (BC_1, IO81, output3, X, 189, 1, PULL1)," &
" 191 (BC_1, IO81, input, X)," &
" 192 (BC_1, *, controlr, 1)," &
" 193 (BC_1, IO82, output3, X, 192, 1, PULL1)," &
" 194 (BC_1, IO82, input, X)," &
" 195 (BC_1, *, internal, 1)," & -- IO83.T
" 196 (BC_1, *, internal, X)," & -- IO83.O
" 197 (BC_1, *, internal, X)," & -- IO83.I
" 198 (BC_1, *, controlr, 1)," &
" 199 (BC_1, IO86, output3, X, 198, 1, PULL1)," &
" 200 (BC_1, IO86, input, X)," &
" 201 (BC_1, *, controlr, 1)," &
" 202 (BC_1, IO87, output3, X, 201, 1, PULL1)," &
" 203 (BC_1, IO87, input, X)," &
" 204 (BC_1, *, internal, 1)," & -- IO88.T
" 205 (BC_1, *, internal, X)," & -- IO88.O
" 206 (BC_1, *, internal, X)," & -- IO88.I
" 207 (BC_1, *, internal, 1)," & -- IO89.T
" 208 (BC_1, *, internal, X)," & -- IO89.O
" 209 (BC_1, *, internal, X)," & -- IO89.I
" 210 (BC_1, *, controlr, 1)," &
" 211 (BC_1, IO90, output3, X, 210, 1, PULL1)," &
" 212 (BC_1, IO90, input, X)," &
" 213 (BC_1, *, controlr, 1)," &
" 214 (BC_1, IO91, output3, X, 213, 1, PULL1)," &
" 215 (BC_1, IO91, input, X)," &
" 216 (BC_1, *, controlr, 1)," &
" 217 (BC_1, IO94, output3, X, 216, 1, PULL1)," &
" 218 (BC_1, IO94, input, X)," &
" 219 (BC_1, *, controlr, 1)," &
" 220 (BC_1, IO95, output3, X, 219, 1, PULL1)," &
" 221 (BC_1, IO95, input, X)," &
" 222 (BC_1, *, internal, 1)," & -- IO96.T
" 223 (BC_1, *, internal, X)," & -- IO96.O
" 224 (BC_1, *, internal, X)," & -- IO96.I
" 225 (BC_1, *, internal, 1)," & -- IO97.T
" 226 (BC_1, *, internal, X)," & -- IO97.O
" 227 (BC_1, *, internal, X)," & -- IO97.I
" 228 (BC_1, *, controlr, 1)," &
" 229 (BC_1, IO98, output3, X, 228, 1, PULL1)," &
" 230 (BC_1, IO98, input, X)," &
" 231 (BC_1, *, controlr, 1)," &
" 232 (BC_1, IO99, output3, X, 231, 1, PULL1)," &
" 233 (BC_1, IO99, input, X)," &
" 234 (BC_1, *, controlr, 1)," &
" 235 (BC_1, IO102, output3, X, 234, 1, PULL1)," &
" 236 (BC_1, IO102, input, X)," &
" 237 (BC_1, *, controlr, 1)," &
" 238 (BC_1, IO103, output3, X, 237, 1, PULL1)," &
" 239 (BC_1, IO103, input, X)," &
" 240 (BC_1, *, controlr, 1)," &
" 241 (BC_1, IO104, output3, X, 240, 1, PULL1)," &
" 242 (BC_1, IO104, input, X)," &
" 243 (BC_1, *, controlr, 1)," &
" 244 (BC_1, IO105, output3, X, 243, 1, PULL1)," &
" 245 (BC_1, IO105, input, X)," &
" 246 (BC_1, *, internal, X)";
--end boundary register
attribute DESIGN_WARNING of XCS05XL_PC84 : entity is
"LPWRB, CLK and DONE are not represented in BOUNDARY_REGISTER." &
"This BSDL file must be modified by the FPGA designer in order to" &
"reflect post-configuration behavior (if any)." &
"If INIT has been high or floating since power-on or the last" &
"rising edge of PROGRAM, then the device may be in" &
"configuration mode in which case this file is not valid." &
"The output and tristate capture values are not valid until after" &
"the device is configured." &
"The fast output mux (where used) is not captured properly." &
"The tristate control is not captured properly when GTS is activated." &
"Some pins have both controlled and uncontrolled input paths.";
end XCS05XL_PC84;