--------------------------------------------------------------------------------
-- Freescale Boundary Scan Description Language --
--------------------------------------------------------------------------------
-- Boundary Scan Description Language (IEEE 1149.1b) --
-- --
-- Device : MPC8541 Revision 1.1 --
-- File Version : C --
-- File Name : MPC8541.R1C --
-- File created : Dec. 14, 2006 --
-- Package type : FC-PBGA 783 pins --
-- Voltage Level : 1.2V --
-- BSDL_status : preliminary --
-- 1149.1 Device Test : tested --
-- System Level Test : tested --
-- --
--------------------------------------------------------------------------------
-- Revision History: --
-- A - Original version --
-- B - For chip revision 1.1 - Thirteen PCI2 pins now have weak internal --
-- pullups always enabled. The pins are: PCI2_C_BE_L(3:0), PCI2_GNT_L(0), --
-- PCI2_FRAME_L, PCI2_DEVSEL_L, PCI2_IRDY_L, PCI2_PAR, PCI2_PERR_L, --
-- PCI2_SERR_L, PCI2_STOP_L, PCI2_TRDY_L --
-- C - Added pins for: TSEC1_RXD[4:7], TSEC1_TXD[4:7], TSEC2_RXD[4:7], --
-- TSEC2_TXD[4:7] to the defined pins list --
-- --
-- --
-- NOTE: Active low ports are designated with a "_L" suffix. --
-- --
-- NOTE: The IEEE 1149.1 standard optional instructions CLAMP, HIGHZ and --
-- IDCODE are supported. --
-- --
-- NOTE: Some busses are broken out bitwise because different pin elements --
-- have different port directions --
-- --
-- NOTE: For assistance with this file, contact your sales office. --
-- --
-- --
--------------------------------------------------------------------------------
-- --
--============================================================================--
-- IMPORTANT NOTICE --
-- This information is provided on an AS IS basis and without warranty. --
-- IN NO EVENT SHALL FREESCALE BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL --
-- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF --
-- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR CUSTOMERS --
-- OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES WHETHER EXPRESS, --
-- IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY --
-- OR FITNESS FOR PARTICULAR PURPOSE. --
-- --
-- Freescale does not represent or warrant that the information furnished --
-- hereunder is free of infringement of any third party patents, --
-- copyrights, trade secrets, or other intellectual property rights. --
-- Freescale does not represent or warrant that the information is free of --
-- defect, or that it meets any particular standard, requirements or need --
-- of the user of the infomation or their customers. --
-- --
-- Freescale reserves the right to change the information in this file --
-- without notice. The BSDL files are also available at: --
-- --
-- http://www.freescale.com --
-- --
--============================================================================--
entity MPC8541 is
generic (PHYSICAL_PIN_MAP : string := "PBGA");
-- PORT DESCRIPTION TERMS
-- in = input only
-- out = three-state output (0, Z, 1)
-- buffer = two-state output (0, 1)
-- inout = bidirectional
-- linkage = OTHER (vdd, vss, analog)
-- bit = single pin
-- bit_vector = group of pins with suffix 0 to n
port (
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST_L: in bit;
LSSD_MODE_L: in bit;
TEST_SEL0: in bit;
TEST_SEL1: in bit;
ASLEEP: inout bit;
CKSTP_IN_L: in bit;
CKSTP_OUT_L: out bit;
CLK_OUT: out bit;
DMA_DACK_L: out bit_vector(0 to 1);
DMA_DDONE_L: out bit_vector(0 to 1);
DMA_DREQ_L: in bit_vector(0 to 1);
EC_GTX_CLK125: in bit;
EC_MDC: inout bit;
EC_MDIO: inout bit;
HRESET_L: in bit;
HRESET_REQ_L: inout bit;
IIC_SCL: inout bit;
IIC_SDA: inout bit;
IRQ: in bit_vector(0 to 7);
IRQ_10: inout bit;
IRQ_11: inout bit;
IRQ_8: inout bit;
IRQ_9: in bit;
IRQ_OUT_L: out bit;
L1_TSTCLK: in bit;
L2_TSTCLK: in bit;
LA: inout bit_vector(27 to 31);
LAD: inout bit_vector(0 to 31);
LALE: inout bit;
LBCTL: inout bit;
LCKE: out bit;
LCLK: out bit_vector(0 to 2);
LCS_L: out bit_vector(0 to 4);
LCS_L_5: inout bit;
LCS_L_6: out bit;
LCS_L_7: out bit;
LDP: inout bit_vector(0 to 3);
LGPL0: inout bit;
LGPL1: inout bit;
LGPL2: inout bit;
LGPL3: inout bit;
LGPL4: inout bit;
LGPL5: inout bit;
LSYNC_IN: in bit;
LSYNC_OUT: out bit;
LWE_L: inout bit_vector(0 to 3);
MA: inout bit_vector(0 to 14);
MBA: inout bit_vector(0 to 1);
MCAS_L: inout bit;
MCK: out bit_vector(0 to 5);
MCKE_0: inout bit;
MCKE_1: out bit;
MCK_L: out bit_vector(0 to 5);
MCP_L: in bit;
MCS_L: inout bit_vector(0 to 3);
MDM: inout bit_vector(0 to 8);
MDQ: inout bit_vector(0 to 63);
MDQS: inout bit_vector(0 to 8);
MDVAL: inout bit;
MECC: inout bit_vector(0 to 7);
MRAS_L: inout bit;
MSRCID_0: inout bit;
MSRCID_1: inout bit;
MSRCID_2: out bit;
MSRCID_3: out bit;
MSRCID_4: inout bit;
MSYNC_IN: in bit;
MSYNC_OUT: out bit;
MWE_L: inout bit;
PA : inout bit_vector(8 to 31);
PB : inout bit_vector(18 to 31);
PC0: inout bit;
PC1: inout bit;
PC : inout bit_vector(4 to 29);
PD7: inout bit;
PD: inout bit_vector(14 to 25);
PD29: inout bit;
PD30: inout bit;
PD31: inout bit;
PCI1_AD: inout bit_vector(31 downto 0);
PCI1_CLK: in bit;
PCI1_C_BE_L: inout bit_vector(3 downto 0);
PCI1_DEVSEL_L: inout bit;
PCI1_FRAME_L: inout bit;
PCI1_GNT_L: inout bit_vector(4 downto 0);
PCI1_IDSEL: in bit;
PCI1_IRDY_L: inout bit;
PCI1_PAR: inout bit;
PCI1_PERR_L: inout bit;
PCI1_REQ_L_0: inout bit;
PCI1_REQ_L_1: in bit;
PCI1_REQ_L_2: in bit;
PCI1_REQ_L_3: in bit;
PCI1_REQ_L_4: in bit;
PCI1_SERR_L: inout bit;
PCI1_STOP_L: inout bit;
PCI1_TRDY_L: inout bit;
PCI2_AD: inout bit_vector(31 downto 0);
PCI2_CLK: in bit;
PCI2_C_BE_L: inout bit_vector(3 downto 0);
PCI2_DEVSEL_L: inout bit;
PCI2_FRAME_L: inout bit;
PCI2_GNT_L: inout bit_vector(4 downto 0);
PCI2_IDSEL: in bit;
PCI2_IRDY_L: inout bit;
PCI2_PAR: inout bit;
PCI2_PERR_L: inout bit;
PCI2_REQ_L_0: inout bit;
PCI2_REQ_L_1: in bit;
PCI2_REQ_L_2: in bit;
PCI2_REQ_L_3: in bit;
PCI2_REQ_L_4: in bit;
PCI2_SERR_L: inout bit;
PCI2_STOP_L: inout bit;
PCI2_TRDY_L: inout bit;
RTC: in bit;
SRESET_L: in bit;
SYSCLK: in bit;
TRIG_IN: in bit;
TRIG_OUT: inout bit;
TSEC1_COL: in bit;
TSEC1_CRS: in bit;
TSEC1_GTX_CLK: out bit;
TSEC1_RXD_0: inout bit;
TSEC1_RXD_1: inout bit;
TSEC1_RXD_2: inout bit;
TSEC1_RXD_3: inout bit;
TSEC1_RXD_4: in bit;
TSEC1_RXD_5: in bit;
TSEC1_RXD_6: in bit;
TSEC1_RXD_7: in bit;
TSEC1_RX_CLK: in bit;
TSEC1_RX_DV: in bit;
TSEC1_RX_ER: in bit;
TSEC1_TXD_0: inout bit;
TSEC1_TXD_1: inout bit;
TSEC1_TXD_2: inout bit;
TSEC1_TXD_3: inout bit;
TSEC1_TXD_4: out bit;
TSEC1_TXD_5: out bit;
TSEC1_TXD_6: out bit;
TSEC1_TXD_7: out bit;
TSEC1_TX_CLK: in bit;
TSEC1_TX_EN: out bit;
TSEC1_TX_ER: out bit;
TSEC2_COL: in bit;
TSEC2_CRS: in bit;
TSEC2_GTX_CLK: out bit;
TSEC2_RXD: in bit_vector(7 downto 0);
TSEC2_RX_CLK: in bit;
TSEC2_RX_DV: in bit;
TSEC2_RX_ER: in bit;
TSEC2_TXD_0: inout bit;
TSEC2_TXD_1: inout bit;
TSEC2_TXD_2: inout bit;
TSEC2_TXD_3: inout bit;
TSEC2_TXD_4: out bit;
TSEC2_TXD_5: out bit;
TSEC2_TXD_6: out bit;
TSEC2_TXD_7: out bit;
TSEC2_TX_CLK: in bit;
TSEC2_TX_EN: out bit;
TSEC2_TX_ER: out bit;
UART_CTS_L: in bit_vector(0 to 1);
UART_RTS_L: out bit_vector(0 to 1);
UART_SIN: in bit_vector(0 to 1);
UART_SOUT: out bit_vector(0 to 1);
UDE_L: in bit;
-- Linkage pins
THERM0: linkage bit;
THERM1: linkage bit;
MVREF: linkage bit;
GND: linkage bit_vector(0 to 97);
OVDD: linkage bit_vector(0 to 41);
GVDD: linkage bit_vector(0 to 40);
VDD: linkage bit_vector(0 to 15);
AVDD: linkage bit_vector(0 to 4);
LVDD: linkage bit_vector(0 to 3);
SENSEVDD: linkage bit;
SENSEVSS: linkage bit;
SPARE01: linkage bit;
SPARE02: linkage bit;
SPARE10: linkage bit;
SPARE13: linkage bit;
NC: linkage bit_vector(0 to 65)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of MPC8541 : entity is "STD_1149_1_2001";
attribute PIN_MAP of MPC8541 : entity is PHYSICAL_PIN_MAP;
constant PBGA: PIN_MAP_STRING :=
"ASLEEP : AG18, "&
"CKSTP_IN_L : M11, "&
"CKSTP_OUT_L : G1, "&
"CLK_OUT : AF22, "&
"DMA_DACK_L : (H6, G5), "&
"DMA_DDONE_L : (H7, G6), "&
"DMA_DREQ_L : (H5, G4), "&
"EC_GTX_CLK125 : E2, "&
"EC_MDC : F1, "&
"EC_MDIO : E1, "&
"HRESET_L : AH16, "&
"HRESET_REQ_L : AG20, "&
"IIC_SCL : AH23, "&
"IIC_SDA : AH22, "&
"IRQ : (AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25), "&
"IRQ_8 : AB20, "&
"IRQ_9 : Y20, "&
"IRQ_10 : AF26, "&
"IRQ_11 : AH24, "&
"IRQ_OUT_L : AB21, "&
"L1_TSTCLK : AB22, "&
"L2_TSTCLK : AG22, "&
"LA : (U18, T18, T19, T20, T21), "&
"LAD : (AD26, AD27, AD28, AC26, AC27, AC28, AA22, AA23, "&
" AA26, Y21, Y22, Y26, W20, W22, W26, V19, "&
" T22, R24, R23, R22, R21, R18, P26, P25, "&
" P20, P19, P18, N22, N23, N24, N25, N26), "&
"LALE : V21, "&
"LBCTL : V20, "&
"LCKE : U23, "&
"LCLK : (U27, U28, V18), "&
"LCS_L : (Y27, Y28, W27, W28, R27), "&
"LCS_L_5 : R28, "&
"LCS_L_6 : P27, "&
"LCS_L_7 : P28, "&
"LDP : (AA27, AA28, T26, P21), "&
"LGPL0 : U19, "&
"LGPL1 : U22, "&
"LGPL2 : V28, "&
"LGPL3 : V27, "&
"LGPL4 : V23, "&
"LGPL5 : V22, "&
"LSSD_MODE_L : AG19, "&
"LSYNC_IN : T27, "&
"LSYNC_OUT : T28, "&
"LWE_L : (AB28, AB27, T23, P24), "&
"MA : (N19, B21, F21, K21, M21, C23, A23, B24, "&
" H23, G24, K19, B25, D27, J14, J13), "&
"MBA : (B18, B19), "&
"MCAS_L : J16, "&
"MCK : (J20, H25, A15, D20, F28, K14), "&
"MCK_L : (F20, G27, B15, E20, F27, L14), "&
"MCKE_0 : E26, "&
"MCKE_1 : E28, "&
"MCP_L : AG17, "&
"MCS_L : (H16, G16, J15, H15), "&
"MDM : (L24, H28, F24, L21, E18, E16, G14, B13, M19), "&
"MDQ : (M26, L27, L22, K24, M24, M23, K27, K26, "&
" K22, J28, F26, E27, J26, J23, H26, G26, "&
" C26, E25, C24, E23, D26, C25, A24, D23, "&
" B23, F22, J21, G21, G22, D22, H21, E21, "&
" N18, J18, D18, L17, M18, L18, C18, A18, "&
" K17, K16, C16, B16, G17, L16, A16, L15, "&
" G15, E15, C14, K13, C15, D15, E14, D14, "&
" D13, E13, D12, A11, F13, H13, A13, B12), "&
"MDQS : (L26, J25, D25, A22, H18, F16, F14, C13, C20), "&
"MDVAL : F4, "&
"MECC : (N20, M20, L19, E19, C21, A21, G19, A19), "&
"MRAS_L : F17, "&
"MSRCID_0 : J9, "&
"MSRCID_1 : G3, "&
"MSRCID_2 : F3, "&
"MSRCID_3 : F5, "&
"MSRCID_4 : F2, "&
"MSYNC_IN : M28, "&
"MSYNC_OUT : N28, "&
"MVREF : N27, "&
"MWE_L : D17, "&
"PA : (J7, J8, K8, K7, K6, K3, K2, K1, "&
" L1, L2, L3, L4, L5, L8, L9, L10, "&
" L11, M10, M9, M8, M7, M6, M3, M2), "&
"PB : (P7, P6, P5, P4, P3, P2, P1, R1, "&
" R2, R3, R4, R5, R6, R7), "&
"PC0 : R8, "&
"PC1 : R9, "&
"pc : (T9, T6, T5, T4, T1, U1, U2, U3, "&
" U4, U7, U8, U9, U10, V9, V6, V5, V4, "&
" V3, V2, V1, W1, W2, W3, W6, W7, W8), "&
"PD7 : Y4, "&
"PD : (AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, "&
" AC4, AC3, AC2, AC1), "&
"PD29 : AD6, "&
"PD30 : AE3, "&
"PD31 : AE2, "&
"PCI1_AD : (AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, "&
" AD9, AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, "&
" AF11, AG11, AH11, V12, W12, Y12, AB12, AD12, "&
" AE12, AG12, AH12, V13, Y13, AB13, AC13), "&
"PCI1_C_BE_L : (AH8, AB10, AD11, AC12), "&
"PCI1_CLK : AH25, "&
"PCI1_DEVSEL_L : AH10, "&
"PCI1_FRAME_L : AC10, "&
"PCI1_GNT_L : (AG6, AF6, AH5, AG5, AE6), "&
"PCI1_IDSEL : AA9, "&
"PCI1_IRDY_L : AD10, "&
"PCI1_PAR : AA11, "&
"PCI1_PERR_L : W11, "&
"PCI1_REQ_L_0 : AF5, "&
"PCI1_REQ_L_1 : AF3, "&
"PCI1_REQ_L_2 : AE4, "&
"PCI1_REQ_L_3 : AG4, "&
"PCI1_REQ_L_4 : AE5, "&
"PCI1_SERR_L : Y11, "&
"PCI1_STOP_L : V11, "&
"PCI1_TRDY_L : AG10, "&
"PCI2_AD : (AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14, "&
" V15, W15, Y15, AA15, AB15, AC15, AD15, AG15, AH15, "&
" V16, W16, AB16, AC16, AD16, AE16, AF16, V17, W17, "&
" Y17, AA17, AB17, AE17, AF17, AF18), "&
"PCI2_C_BE_L : (AG13, AH13, V14, W14), "&
"PCI2_CLK : AH27, "&
"PCI2_DEVSEL_L : AD13, "&
"PCI2_FRAME_L : AE13, "&
"PCI2_GNT_L : (AD19, AE19, AE18, AD18, AC18), "&
"PCI2_IDSEL : AC22, "&
"PCI2_IRDY_L : AD20, "&
"PCI2_PAR : Y14, "&
"PCI2_PERR_L : AC20, "&
"PCI2_REQ_L_0 : AD21, "&
"PCI2_REQ_L_1 : AE21, "&
"PCI2_REQ_L_2 : AD22, "&
"PCI2_REQ_L_3 : AE22, "&
"PCI2_REQ_L_4 : AC23, "&
"PCI2_SERR_L : AE20, "&
"PCI2_STOP_L : AC21, "&
"PCI2_TRDY_L : AC19, "&
"RTC : AB23, "&
"SENSEVDD : L12, "&
"SENSEVSS : K12, "&
"SPARE01 : T11, "&
"SPARE02 : U11, "&
"SPARE10 : AF1, "&
"SPARE13 : C1, "&
"SRESET_L : AF20, "&
"SYSCLK : AH21, "&
"TCK : AF21, "&
"TDI : AG21, "&
"TDO : AF19, "&
"TEST_SEL0 : AH20, "&
"TEST_SEL1 : AG26, "&
"THERM0 : AG2, "&
"THERM1 : AH3, "&
"TMS : AF23, "&
"TRIG_IN : N12, "&
"TRIG_OUT : G2, "&
"TRST_L : AG23, "&
"TSEC1_COL : G7, "&
"TSEC1_CRS : C3, "&
"TSEC1_GTX_CLK : B6, "&
"TSEC1_RX_CLK : D6, "&
"TSEC1_RX_DV : D2, "&
"TSEC1_RX_ER : E5, "&
"TSEC1_RXD_0 : E6, "&
"TSEC1_RXD_1 : F6, "&
"TSEC1_RXD_2 : A5, "&
"TSEC1_RXD_3 : B5, "&
"TSEC1_RXD_4 : D5, "&
"TSEC1_RXD_5 : D3, "&
"TSEC1_RXD_6 : B4, "&
"TSEC1_RXD_7 : D4, "&
"TSEC1_TX_CLK : C6, "&
"TSEC1_TX_EN : C8, "&
"TSEC1_TX_ER : B8, "&
"TSEC1_TXD_0 : E8, "&
"TSEC1_TXD_1 : G8, "&
"TSEC1_TXD_2 : A7, "&
"TSEC1_TXD_3 : B7, "&
"TSEC1_TXD_4 : C7, "&
"TSEC1_TXD_5 : D7, "&
"TSEC1_TXD_6 : F7, "&
"TSEC1_TXD_7 : A6, "&
"TSEC2_COL : F8, "&
"TSEC2_CRS : D9, "&
"TSEC2_GTX_CLK : C10, "&
"TSEC2_RX_CLK : E10, "&
"TSEC2_RX_DV : H8, "&
"TSEC2_RX_ER : A8, "&
"TSEC2_RXD : (F9, E9, C9, B9, A9, H9, G10, F10), "&
"TSEC2_TX_CLK : D10, "&
"TSEC2_TX_EN : B11, "&
"TSEC2_TX_ER : D11, "&
"TSEC2_TXD_0 : E11, "&
"TSEC2_TXD_1 : G11, "&
"TSEC2_TXD_2 : H11, "&
"TSEC2_TXD_3 : J11, "&
"TSEC2_TXD_4 : K11, "&
"TSEC2_TXD_5 : J10, "&
"TSEC2_TXD_6 : A10, "&
"TSEC2_TXD_7 : B10, "&
"UART_CTS_L : (Y2, Y3), "&
"UART_RTS_L : (Y1, AD1), "&
"UART_SIN : (P11, AD5), "&
"UART_SOUT : (N6, AD2), "&
"UDE_L : AG16, "&
"AVDD : (AH19, AH18, AH17, AE28, AF28), "&
"GND : (A12, A17, AA13, AA6, AB11, AB19, AB4, AC6, "&
" AC9, AD17, AD3, AD8, AF10, AF13, AF15, AF2, "&
" AF27, AF4, AG3, AG7, B14, B20, B26, B27, "&
" B3, C11, C17, C19, C2, C22, C27, C4, "&
" D8, E12, E24, E3, F11, F18, F23, G12, "&
" G25, G9, H12, H14, H17, H20, H22, H27, "&
" H4, J19, J24, K18, K23, K28, K5, K9, "&
" L20, L25, L6, M12, M14, M16, M22, M27, "&
" M4, N13, N15, N17, N2, P12, P14, P16, "&
" P23, R13, R15, R17, R20, R26, T10, T12, "&
" T14, T16, T3, T8, U13, U15, U16, U17, "&
" U21, U6, V10, V26, V7, W18, W23, W5, "&
" Y16, Y8), "&
"GVDD : (A14, A20, A25, A26, A27, A28, B17, B22, "&
" B28, C12, C28, D16, D19, D21, D24, D28, "&
" E17, E22, F12, F15, F19, F25, G13, G18, "&
" G20, G23, G28, H19, H24, J12, J17, J22, "&
" J27, K15, K20, K25, L13, L23, L28, M25, "&
" N21), "&
"LVDD : (A4, C5, E7, H10), "&
"OVDD : (AA12, AA16, AA20, AA5, AB26, AB7, AB9, AC11, "&
" AC17, AC5, AD4, AE1, AE10, AE15, AE8, AF12, "&
" AF7, AG27, AH4, D1, E4, H3, K10, K4, "&
" L7, M5, N3, P22, R19, R25, T2, T7, "&
" U20, U26, U5, V8, W13, W19, W21, W4, "&
" Y23, Y7), "&
"VDD : (M13, M15, M17, N14, N16, P13, P15, P17, "&
" R12, R14, R16, T13, T15, T17, U12, U14), "&
"NC : (AA24, AA25, AA3, AA4, AA7, AA8, AB24, AB25, "&
" AC24, AC25, AD23, AD24, AD25, AE23, AE24, AE25, "&
" AE26, AE27, AF24, AF25, H1, H2, J1, J2, "&
" J3, J4, J5, J6, M1, N1, N10, N11, "&
" N4, N5, N7, N8, N9, P10, P8, P9, "&
" R10, R11, T24, T25, U24, U25, V24, V25, "&
" W24, W25, W9, Y24, Y25, Y5, Y6, Y9, "&
" AH26, AH28, AG28, AH1, AG1, AH2, B1, B2, "&
" A2, A3)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (30.0e6, BOTH);
attribute TAP_SCAN_RESET of TRST_L : signal is true;
attribute COMPLIANCE_PATTERNS of MPC8541 : entity is
"(LSSD_MODE_L, TEST_SEL0, TEST_SEL1) (100)";
attribute INSTRUCTION_LENGTH of MPC8541 : entity is 8;
attribute INSTRUCTION_OPCODE of MPC8541 : entity is
-- Public instructions:
"EXTEST (00000000), "& -- Hex 00
"SAMPLE (11110000), "& -- Hex F0
"PRELOAD (11110000), "& -- Hex F0
"BYPASS (11111111), "& -- Hex FF
"HIGHZ (11110010), "& -- Hex F2
"CLAMP (11110001), "& -- Hex F1
"IDCODE (11110011), "& -- Hex F3
-- Private instructions:
"PRIVATE000(11111110), "&
"PRIVATE001(00000101), "&
"PRIVATE002(00000110), "&
"PRIVATE003(00000111), "&
"PRIVATE004(00000011), "&
"PRIVATE005(00000100), "&
"PRIVATE006(00110000), "&
"PRIVATE007(00001010), "&
"PRIVATE008(00110001), "&
"PRIVATE009(00110010), "&
"PRIVATE010(00110011), "&
"PRIVATE011(00110100), "&
"PRIVATE012(00110101), "&
"PRIVATE013(00110110), "&
"PRIVATE014(00110111), "&
"PRIVATE015(01000100), "&
"PRIVATE016(00001001), "&
"PRIVATE017(00001011), "&
"PRIVATE018(00001100), "&
"PRIVATE019(00001110), "&
"PRIVATE020(00010000), "&
"PRIVATE021(00010001), "&
"PRIVATE022(00010010), "&
"PRIVATE023(00010011), "&
"PRIVATE024(00010100)";
attribute INSTRUCTION_CAPTURE of MPC8541 : entity is "xxxxxx01";
-- Use of some private opcodes can result in damage to the circuit,
-- board, or system.
attribute INSTRUCTION_PRIVATE of MPC8541 : entity is
"PRIVATE000, PRIVATE001, PRIVATE002, PRIVATE003, "&
"PRIVATE004, PRIVATE005, PRIVATE006, PRIVATE007, "&
"PRIVATE008, PRIVATE009, PRIVATE010, PRIVATE011, "&
"PRIVATE012, PRIVATE013, PRIVATE014, PRIVATE015, "&
"PRIVATE016, PRIVATE017, PRIVATE018, PRIVATE019, "&
"PRIVATE020, PRIVATE021, PRIVATE022, PRIVATE023, "&
"PRIVATE024";
attribute IDCODE_REGISTER of MPC8541 : entity is
-- IDCODE is 0007201D
"0000" & -- Version
"0000000001110010" & -- Part number
"00000001110" & -- Manufacturer Identity
"1"; -- Mandatory LSB
attribute REGISTER_ACCESS of MPC8541 : entity is
"BYPASS(BYPASS),"&
"BOUNDARY (SAMPLE)";
attribute BOUNDARY_LENGTH of MPC8541 : entity is 740;
attribute BOUNDARY_REGISTER of MPC8541 : entity is
-- PORT DESCRIPTION TERMS
-- cell type: BC_6 bidirectional else BC_2
-- port: port name with index if port description says bit_vector
-- function
-- input = input only
-- bidir = bidirectional
-- control = control cell
-- buffer = output only
-- output3 = three state ouput
-- observe_only = observe only
-- safe = value in control cell to make input = 0 for bidir and controlr
-- ccell = controlling cell number for I/O direction
-- dsval = disabling (input) value
-- rslt = result if disabled (input = Z)
-- tdo = first cell shifted out during ShiftDR
-- num cell port function safe ccell dsval rslt
"0 (BC_6, PA(8), bidir, X, 1, 0, Z)," &
"1 (BC_2, *, control, 0), " &
"2 (BC_6, PA(9), bidir, X, 3, 0, Z)," &
"3 (BC_2, *, control, 0), " &
"4 (BC_6, PA(15), bidir, X, 5, 0, Z)," &
"5 (BC_2, *, control, 0), " &
"6 (BC_6, PA(10), bidir, X, 7, 0, Z)," &
"7 (BC_2, *, control, 0), " &
"8 (BC_6, PA(11), bidir, X, 9, 0, Z)," &
"9 (BC_2, *, control, 0), " &
"10 (BC_6, PA(14), bidir, X, 11, 0, Z)," &
"11 (BC_2, *, control, 0), " &
"12 (BC_6, PA(12), bidir, X, 13, 0, Z)," &
"13 (BC_2, *, control, 0), " &
"14 (BC_6, PA(13), bidir, X, 15, 0, Z)," &
"15 (BC_2, *, control, 0), " &
"16 (BC_6, PA(21), bidir, X, 17, 0, Z)," &
"17 (BC_2, *, control, 0), " &
"18 (BC_6, PA(17), bidir, X, 19, 0, Z)," &
"19 (BC_2, *, control, 0), " &
"20 (BC_6, PA(19), bidir, X, 21, 0, Z)," &
"21 (BC_2, *, control, 0), " &
"22 (BC_6, PA(23), bidir, X, 23, 0, Z)," &
"23 (BC_2, *, control, 0), " &
"24 (BC_6, PA(20), bidir, X, 25, 0, Z)," &
"25 (BC_2, *, control, 0), " &
"26 (BC_6, PA(16), bidir, X, 27, 0, Z)," &
"27 (BC_2, *, control, 0), " &
"28 (BC_6, PA(18), bidir, X, 29, 0, Z)," &
"29 (BC_2, *, control, 0), " &
"30 (BC_6, PA(22), bidir, X, 31, 0, Z)," &
"31 (BC_2, *, control, 0), " &
"32 (BC_6, PA(24), bidir, X, 33, 0, Z)," &
"33 (BC_2, *, control, 0), " &
"34 (BC_6, PA(26), bidir, X, 35, 0, Z)," &
"35 (BC_2, *, control, 0), " &
"36 (BC_6, PA(27), bidir, X, 37, 0, Z)," &
"37 (BC_2, *, control, 0), " &
"38 (BC_6, PA(25), bidir, X, 39, 0, Z)," &
"39 (BC_2, *, control, 0), " &
"40 (BC_6, PA(30), bidir, X, 41, 0, Z)," &
"41 (BC_2, *, control, 0), " &
"42 (BC_6, PA(28), bidir, X, 43, 0, Z)," &
"43 (BC_2, *, control, 0), " &
"44 (BC_6, PA(29), bidir, X, 45, 0, Z)," &
"45 (BC_2, *, control, 0), " &
"46 (BC_6, PB(19), bidir, X, 47, 0, Z)," &
"47 (BC_2, *, control, 0), " &
"48 (BC_6, PB(18), bidir, X, 49, 0, Z)," &
"49 (BC_2, *, control, 0), " &
"50 (BC_6, PB(20), bidir, X, 51, 0, Z)," &
"51 (BC_2, *, control, 0), " &
"52 (BC_6, PA(31), bidir, X, 53, 0, Z)," &
"53 (BC_2, *, control, 0), " &
"54 (BC_6, PB(24), bidir, X, 55, 0, Z)," &
"55 (BC_2, *, control, 0), " &
"56 (BC_6, PB(23), bidir, X, 57, 0, Z)," &
"57 (BC_2, *, control, 0), " &
"58 (BC_6, PB(22), bidir, X, 59, 0, Z)," &
"59 (BC_2, *, control, 0), " &
"60 (BC_6, PB(21), bidir, X, 61, 0, Z)," &
"61 (BC_2, *, control, 0), " &
"62 (BC_6, PB(29), bidir, X, 63, 0, Z)," &
"63 (BC_2, *, control, 0), " &
"64 (BC_6, PB(28), bidir, X, 65, 0, Z)," &
"65 (BC_2, *, control, 0), " &
"66 (BC_6, PB(25), bidir, X, 67, 0, Z)," &
"67 (BC_2, *, control, 0), " &
"68 (BC_6, PB(26), bidir, X, 69, 0, Z)," &
"69 (BC_2, *, control, 0), " &
"70 (BC_6, PB(31), bidir, X, 71, 0, Z)," &
"71 (BC_2, *, control, 0), " &
"72 (BC_6, PB(30), bidir, X, 73, 0, Z)," &
"73 (BC_2, *, control, 0), " &
"74 (BC_6, PC0, bidir, X, 75, 0, Z)," &
"75 (BC_2, *, control, 0), " &
"76 (BC_6, PB(27), bidir, X, 77, 0, Z)," &
"77 (BC_2, *, control, 0), " &
"78 (BC_6, PC(5), bidir, X, 79, 0, Z)," &
"79 (BC_2, *, control, 0), " &
"80 (BC_6, PC(4), bidir, X, 81, 0, Z)," &
"81 (BC_2, *, control, 0), " &
"82 (BC_6, PC(6), bidir, X, 83, 0, Z)," &
"83 (BC_2, *, control, 0), " &
"84 (BC_6, PC1, bidir, X, 85, 0, Z)," &
"85 (BC_2, *, control, 0), " &
"86 (BC_6, PC(11), bidir, X, 87, 0, Z)," &
"87 (BC_2, *, control, 0), " &
"88 (BC_6, PC(10), bidir, X, 89, 0, Z)," &
"89 (BC_2, *, control, 0), " &
"90 (BC_6, PC(8), bidir, X, 91, 0, Z)," &
"91 (BC_2, *, control, 0), " &
"92 (BC_6, PC(7), bidir, X, 93, 0, Z)," &
"93 (BC_2, *, control, 0), " &
"94 (BC_6, PC(15), bidir, X, 95, 0, Z)," &
"95 (BC_2, *, control, 0), " &
"96 (BC_6, PC(14), bidir, X, 97, 0, Z)," &
"97 (BC_2, *, control, 0), " &
"98 (BC_6, PC(12), bidir, X, 99, 0, Z)," &
"99 (BC_2, *, control, 0), " &
"100 (BC_6, PC(9), bidir, X, 101, 0, Z)," &
"101 (BC_2, *, control, 0), " &
"102 (BC_6, PC(17), bidir, X, 103, 0, Z)," &
"103 (BC_2, *, control, 0), " &
"104 (BC_6, PC(16), bidir, X, 105, 0, Z)," &
"105 (BC_2, *, control, 0), " &
"106 (BC_6, PC(18), bidir, X, 107, 0, Z)," &
"107 (BC_2, *, control, 0), " &
"108 (BC_6, PC(13), bidir, X, 109, 0, Z)," &
"109 (BC_2, *, control, 0), " &
"110 (BC_6, PC(23), bidir, X, 111, 0, Z)," &
"111 (BC_2, *, control, 0), " &
"112 (BC_6, PC(22), bidir, X, 113, 0, Z)," &
"113 (BC_2, *, control, 0), " &
"114 (BC_6, PC(20), bidir, X, 115, 0, Z)," &
"115 (BC_2, *, control, 0), " &
"116 (BC_6, PC(19), bidir, X, 117, 0, Z)," &
"117 (BC_2, *, control, 0), " &
"118 (BC_6, PC(27), bidir, X, 119, 0, Z)," &
"119 (BC_2, *, control, 0), " &
"120 (BC_6, PC(26), bidir, X, 121, 0, Z)," &
"121 (BC_2, *, control, 0), " &
"122 (BC_6, PC(24), bidir, X, 123, 0, Z)," &
"123 (BC_2, *, control, 0), " &
"124 (BC_6, PC(21), bidir, X, 125, 0, Z)," &
"125 (BC_2, *, control, 0), " &
"126 (BC_6, PC(29), bidir, X, 127, 0, Z)," &
"127 (BC_2, *, control, 0), " &
"128 (BC_6, PC(28), bidir, X, 129, 0, Z)," &
"129 (BC_2, *, control, 0), " &
"130 (BC_6, PD(14), bidir, X, 131, 0, Z)," &
"131 (BC_2, *, control, 0), " &
"132 (BC_6, PC(25), bidir, X, 133, 0, Z)," &
"133 (BC_2, *, control, 0), " &
"134 (BC_6, PD(18), bidir, X, 135, 0, Z)," &
"135 (BC_2, *, control, 0), " &
"136 (BC_6, PD(17), bidir, X, 137, 0, Z)," &
"137 (BC_2, *, control, 0), " &
"138 (BC_6, PD(15), bidir, X, 139, 0, Z)," &
"139 (BC_2, *, control, 0), " &
"140 (BC_6, PD7, bidir, X, 141, 0, Z)," &
"141 (BC_2, *, control, 0), " &
"142 (BC_6, PD(22), bidir, X, 143, 0, Z)," &
"143 (BC_2, *, control, 0), " &
"144 (BC_6, PD(21), bidir, X, 145, 0, Z)," &
"145 (BC_2, *, control, 0), " &
"146 (BC_6, PD(19), bidir, X, 147, 0, Z)," &
"147 (BC_2, *, control, 0), " &
"148 (BC_6, PD(16), bidir, X, 149, 0, Z)," &
"149 (BC_2, *, control, 0), " &
"150 (BC_6, PD29, bidir, X, 151, 0, Z)," &
"151 (BC_2, *, control, 0), " &
"152 (BC_6, PD(25), bidir, X, 153, 0, Z)," &
"153 (BC_2, *, control, 0), " &
"154 (BC_6, PD(23), bidir, X, 155, 0, Z)," &
"155 (BC_2, *, control, 0), " &
"156 (BC_6, PD(20), bidir, X, 157, 0, Z)," &
"157 (BC_2, *, control, 0), " &
"158 (BC_6, PD31, bidir, X, 159, 0, Z)," &
"159 (BC_2, *, control, 0), " &
"160 (BC_6, PD30, bidir, X, 161, 0, Z)," &
"161 (BC_2, *, control, 0), " &
"162 (BC_6, PD(24), bidir, X, 163, 0, Z)," &
"163 (BC_2, *, control, 0), " &
"164 (BC_6, EC_MDC, bidir, 0, 165, 0, Z), " &
"165 (BC_2, *, control, 0), " &
"166 (BC_6, EC_MDIO, bidir, 0, 167, 0, Z), " &
"167 (BC_2, *, control, 0), " &
"168 (BC_2, MSRCID_3, output3, 0, 172, 0, Z), " &
"169 (BC_6, MSRCID_0, bidir, 0, 170, 0, Z), " &
"170 (BC_2, *, control, 0), " &
"171 (BC_2, MSRCID_2, output3, 0, 172, 0, Z), " &
"172 (BC_2, *, control, 0), " &
"173 (BC_6, MSRCID_1, bidir, 0, 170, 0, Z), " &
"174 (BC_6, MSRCID_4, bidir, 0, 170, 0, Z), " &
"175 (BC_6, MDVAL, bidir, 0, 176, 0, Z), " &
"176 (BC_2, *, control, 0), " &
"177 (BC_2, DMA_DDONE_L(0), output3, 0, 178, 0, Z), " &
"178 (BC_2, *, control, 0), " &
"179 (BC_2, DMA_DDONE_L(1), output3, 0, 180, 0, Z), " &
"180 (BC_2, *, control, 0), " &
"181 (BC_2, DMA_DREQ_L(1), input, X), " &
"182 (BC_2, DMA_DREQ_L(0), input, X), " &
"183 (BC_2, DMA_DACK_L(1), output3, 0, 185, 0, Z), " &
"184 (BC_2, DMA_DACK_L(0), output3, 0, 185, 0, Z), " &
"185 (BC_2, *, control, 0), " &
"186 (BC_2, CKSTP_IN_L, input, X), " &
"187 (BC_2, CKSTP_OUT_L, output3, 0, 188, 0, Z), " &
"188 (BC_2, *, control, 0), " &
"189 (BC_2, TRIG_IN, input, X), " &
"190 (BC_6, TRIG_OUT, bidir, 0, 191, 0, Z), " &
"191 (BC_2, *, control, 0), " &
"192 (BC_2, UART_SOUT(1), output3, 0, 198, 0, Z), " &
"193 (BC_2, UART_CTS_L(1), input, X), " &
"194 (BC_2, UART_RTS_L(1), output3, 0, 201, 0, Z), " &
"195 (BC_2, UART_SIN(1), input, X), " &
"196 (BC_2, UART_SIN(0), input, X), " &
"197 (BC_2, UART_SOUT(0), output3, 0, 198, 0, Z), " &
"198 (BC_2, *, control, 0), " &
"199 (BC_2, UART_CTS_L(0), input, X), " &
"200 (BC_2, UART_RTS_L(0), output3, 0, 201, 0, Z), " &
"201 (BC_2, *, control, 0), " &
"202 (BC_2, PCI1_IDSEL, input, X), " &
"203 (BC_6, PCI1_AD(27), bidir, 0, 211, 0, Z), " &
"204 (BC_2, PCI1_REQ_L_3, input, X), " &
"205 (BC_6, PCI1_GNT_L(0), bidir, 0, 206, 0, Z), " &
"206 (BC_2, *, control, 0), " &
"207 (BC_2, PCI1_REQ_L_1, input, X), " &
"208 (BC_6, PCI1_STOP_L, bidir, 0, 209, 0, Z), " &
"209 (BC_2, *, control, 0), " &
"210 (BC_6, PCI1_AD(30), bidir, 0, 211, 0, Z), " &
"211 (BC_2, *, control, 0), " &
"212 (BC_6, PCI1_GNT_L(1), bidir, 0, 213, 0, Z), " &
"213 (BC_2, *, control, 0), " &
"214 (BC_6, PCI1_AD(18), bidir, 0, 211, 0, Z), " &
"215 (BC_2, PCI1_REQ_L_2, input, X), " &
"216 (BC_6, PCI1_GNT_L(3), bidir, 0, 217, 0, Z), " &
"217 (BC_2, *, control, 0), " &
"218 (BC_6, PCI1_GNT_L(2), bidir, 0, 219, 0, Z), " &
"219 (BC_2, *, control, 0), " &
"220 (BC_6, PCI1_REQ_L_0, bidir, 0, 221, 0, Z), " &
"221 (BC_2, *, control, 0), " &
"222 (BC_2, PCI1_REQ_L_4, input, X), " &
"223 (BC_6, PCI1_AD(16), bidir, 0, 224, 0, Z), " &
"224 (BC_2, *, control, 0), " &
"225 (BC_6, PCI1_AD(31), bidir, 0, 224, 0, Z), " &
"226 (BC_6, PCI1_PERR_L, bidir, 0, 227, 0, Z), " &
"227 (BC_2, *, control, 0), " &
"228 (BC_6, PCI1_AD(17), bidir, 0, 224, 0, Z), " &
"229 (BC_6, PCI1_C_BE_L(2), bidir, 0, 230, 0, Z), " &
"230 (BC_2, *, control, 0), " &
"231 (BC_6, PCI1_AD(25), bidir, 0, 233, 0, Z), " &
"232 (BC_6, PCI1_AD(29), bidir, 0, 233, 0, Z), " &
"233 (BC_2, *, control, 0), " &
"234 (BC_6, PCI1_AD(26), bidir, 0, 233, 0, Z), " &
"235 (BC_6, PCI1_AD(10), bidir, 0, 233, 0, Z), " &
"236 (BC_6, PCI1_PAR, bidir, 0, 237, 0, Z), " &
"237 (BC_2, *, control, 0), " &
"238 (BC_6, PCI1_GNT_L(4), bidir, 0, 239, 0, Z), " &
"239 (BC_2, *, control, 0), " &
"240 (BC_6, PCI1_AD(11), bidir, 0, 244, 0, Z), " &
"241 (BC_6, PCI1_AD(22), bidir, 0, 244, 0, Z), " &
"242 (BC_6, PCI1_C_BE_L(3), bidir, 0, 230, 0, Z), " &
"243 (BC_6, PCI1_AD(23), bidir, 0, 244, 0, Z), " &
"244 (BC_2, *, control, 0), " &
"245 (BC_6, PCI1_SERR_L, bidir, 0, 246, 0, Z), " &
"246 (BC_2, *, control, 0), " &
"247 (BC_6, PCI1_IRDY_L, bidir, 0, 248, 0, Z), " &
"248 (BC_2, *, control, 0), " &
"249 (BC_6, PCI1_AD(20), bidir, 0, 244, 0, Z), " &
"250 (BC_6, PCI1_FRAME_L, bidir, 0, 251, 0, Z), " &
"251 (BC_2, *, control, 0), " &
"252 (BC_6, PCI1_AD(28), bidir, 0, 253, 0, Z), " &
"253 (BC_2, *, control, 0), " &
"254 (BC_6, PCI1_AD(21), bidir, 0, 253, 0, Z), " &
"255 (BC_6, PCI1_AD(19), bidir, 0, 253, 0, Z), " &
"256 (BC_6, PCI1_AD(24), bidir, 0, 253, 0, Z), " &
"257 (BC_6, PCI1_TRDY_L, bidir, 0, 258, 0, Z), " &
"258 (BC_2, *, control, 0), " &
"259 (BC_6, PCI1_DEVSEL_L, bidir, 0, 260, 0, Z), " &
"260 (BC_2, *, control, 0), " &
"261 (BC_6, PCI1_AD(15), bidir, 0, 262, 0, Z), " &
"262 (BC_2, *, control, 0), " &
"263 (BC_6, PCI1_AD(9), bidir, 0, 262, 0, Z), " &
"264 (BC_6, PCI1_C_BE_L(1), bidir, 0, 267, 0, Z), " &
"265 (BC_6, PCI1_AD(3), bidir, 0, 262, 0, Z), " &
"266 (BC_6, PCI1_C_BE_L(0), bidir, 0, 267, 0, Z), " &
"267 (BC_2, *, control, 0), " &
"268 (BC_6, PCI1_AD(8), bidir, 0, 269, 0, Z), " &
"269 (BC_2, *, control, 0), " &
"270 (BC_6, PCI1_AD(5), bidir, 0, 269, 0, Z), " &
"271 (BC_6, PCI1_AD(2), bidir, 0, 269, 0, Z), " &
"272 (BC_6, PCI1_AD(12), bidir, 0, 269, 0, Z), " &
"273 (BC_6, PCI1_AD(13), bidir, 0, 275, 0, Z), " &
"274 (BC_6, PCI1_AD(0), bidir, 0, 275, 0, Z), " &
"275 (BC_2, *, control, 0), " &
"276 (BC_6, PCI1_AD(14), bidir, 0, 275, 0, Z), " &
"277 (BC_6, PCI1_AD(1), bidir, 0, 275, 0, Z), " &
"278 (BC_6, PCI1_AD(6), bidir, 0, 287, 0, Z), " &
"279 (BC_6, PCI2_C_BE_L(3), bidir, 0, 289, 0, PULL1), " &
"280 (BC_6, PCI1_AD(7), bidir, 0, 287, 0, Z), " &
"281 (BC_6, PCI2_FRAME_L, bidir, 0, 282, 0, PULL1), " &
"282 (BC_2, *, control, 0), " &
"283 (BC_6, PCI2_DEVSEL_L, bidir, 0, 284, 0, PULL1), " &
"284 (BC_2, *, control, 0), " &
"285 (BC_6, PCI2_C_BE_L(2), bidir, 0, 289, 0, PULL1), " &
"286 (BC_6, PCI1_AD(4), bidir, 0, 287, 0, Z), " &
"287 (BC_2, *, control, 0), " &
"288 (BC_6, PCI2_C_BE_L(0), bidir, 0, 289, 0, PULL1), " &
"289 (BC_2, *, control, 0), " &
"290 (BC_6, PCI2_PAR, bidir, 0, 291, 0, PULL1), " &
"291 (BC_2, *, control, 0), " &
"292 (BC_6, PCI2_AD(28), bidir, 0, 297, 0, Z), " &
"293 (BC_6, PCI2_C_BE_L(1), bidir, 0, 289, 0, PULL1), " &
"294 (BC_6, PCI2_AD(29), bidir, 0, 297, 0, Z), " &
"295 (BC_6, PCI2_AD(30), bidir, 0, 297, 0, Z), " &
"296 (BC_6, PCI2_AD(24), bidir, 0, 297, 0, Z), " &
"297 (BC_2, *, control, 0), " &
"298 (BC_6, PCI2_AD(31), bidir, 0, 299, 0, Z), " &
"299 (BC_2, *, control, 0), " &
"300 (BC_6, PCI2_AD(25), bidir, 0, 299, 0, Z), " &
"301 (BC_6, PCI2_AD(26), bidir, 0, 299, 0, Z), " &
"302 (BC_6, PCI2_AD(18), bidir, 0, 299, 0, Z), " &
"303 (BC_6, PCI2_AD(27), bidir, 0, 306, 0, Z), " &
"304 (BC_6, PCI2_AD(17), bidir, 0, 306, 0, Z), " &
"305 (BC_6, PCI2_AD(16), bidir, 0, 306, 0, Z), " &
"306 (BC_2, *, control, 0), " &
"307 (BC_6, PCI2_AD(19), bidir, 0, 306, 0, Z), " &
"308 (BC_6, PCI2_AD(15), bidir, 0, 316, 0, Z), " &
"309 (BC_6, PCI2_AD(20), bidir, 0, 310, 0, Z), " &
"310 (BC_2, *, control, 0), " &
"311 (BC_6, PCI2_AD(21), bidir, 0, 310, 0, Z), " &
"312 (BC_6, PCI2_AD(9), bidir, 0, 316, 0, Z), " &
"313 (BC_6, PCI2_AD(22), bidir, 0, 310, 0, Z), " &
"314 (BC_2, UDE_L, input, X), " &
"315 (BC_6, PCI2_AD(8), bidir, 0, 316, 0, Z), " &
"316 (BC_2, *, control, 0), " &
"317 (BC_6, PCI2_AD(10), bidir, 0, 321, 0, Z), " &
"318 (BC_6, PCI2_AD(23), bidir, 0, 310, 0, Z), " &
"319 (BC_6, PCI2_AD(11), bidir, 0, 321, 0, Z), " &
"320 (BC_6, PCI2_AD(12), bidir, 0, 321, 0, Z), " &
"321 (BC_2, *, control, 0), " &
"322 (BC_2, IRQ(4), input, X), " &
"323 (BC_2, IRQ(5), input, X), " &
"324 (BC_6, IRQ_10, bidir, 0, 325, 0, Z), " &
"325 (BC_2, *, control, 0), " &
"326 (BC_2, L1_TSTCLK, input, X), " &
"327 (BC_6, PCI2_AD(7), bidir, 0, 333, 0, Z), " &
"328 (BC_2, IRQ_9, input, X), " &
"329 (BC_2, IRQ(1), input, X), " &
"330 (BC_2, IRQ(6), input, X), " &
"331 (BC_2, RTC, input, X), " &
"332 (BC_6, PCI2_AD(6), bidir, 0, 333, 0, Z), " &
"333 (BC_2, *, control, 0), " &
"334 (BC_2, L2_TSTCLK, input, X), " &
"335 (BC_2, IRQ(2), input, X), " &
"336 (BC_2, IRQ(0), input, X), " &
"337 (BC_2, IRQ_OUT_L, output3, 0, 338, 0, Z), " &
"338 (BC_2, *, control, 0), " &
"339 (BC_6, PCI2_AD(5), bidir, 0, 333, 0, Z), " &
"340 (BC_6, PCI2_AD(1), bidir, 0, 333, 0, Z), " &
"341 (BC_6, PCI2_AD(2), bidir, 0, 349, 0, Z), " &
"342 (BC_6, PCI2_AD(0), bidir, 0, 349, 0, Z), " &
"343 (BC_6, IRQ_11, bidir, 0, 344, 0, Z), " &
"344 (BC_2, *, control, 0), " &
"345 (BC_6, PCI2_AD(13), bidir, 0, 346, 0, Z), " &
"346 (BC_2, *, control, 0), " &
"347 (BC_6, PCI2_AD(3), bidir, 0, 349, 0, Z), " &
"348 (BC_6, PCI2_AD(4), bidir, 0, 349, 0, Z), " &
"349 (BC_2, *, control, 0), " &
"350 (BC_6, PCI2_AD(14), bidir, 0, 346, 0, Z), " &
"351 (BC_6, IRQ_8, bidir, 0, 352, 0, Z), " &
"352 (BC_2, *, control, 0), " &
"353 (BC_2, IRQ(7), input, X), " &
"354 (BC_2, IRQ(3), input, X), " &
"355 (BC_2, PCI2_REQ_L_4, input, X), " &
"356 (BC_6, PCI2_REQ_L_0, bidir, 0, 357, 0, Z), " &
"357 (BC_2, *, control, 0), " &
"358 (BC_2, PCI2_REQ_L_1, input, X), " &
"359 (BC_2, PCI2_REQ_L_2, input, X), " &
"360 (BC_6, PCI2_PERR_L, bidir, 0, 361, 0, PULL1), " &
"361 (BC_2, *, control, 0), " &
"362 (BC_2, PCI2_REQ_L_3, input, X), " &
"363 (BC_6, PCI2_IRDY_L, bidir, 0, 364, 0, PULL1), " &
"364 (BC_2, *, control, 0), " &
"365 (BC_2, PCI2_IDSEL, input, X), " &
"366 (BC_6, PCI2_SERR_L, bidir, 0, 367, 0, PULL1), " &
"367 (BC_2, *, control, 0), " &
"368 (BC_6, PCI2_STOP_L, bidir, 0, 369, 0, PULL1), " &
"369 (BC_2, *, control, 0), " &
"370 (BC_6, PCI2_TRDY_L, bidir, 0, 371, 0, PULL1), " &
"371 (BC_2, *, control, 0), " &
"372 (BC_6, PCI2_GNT_L(0), bidir, 0, 373, 0, PULL1), " &
"373 (BC_2, *, control, 0), " &
"374 (BC_6, PCI2_GNT_L(4), bidir, 0, 375, 0, Z), " &
"375 (BC_2, *, control, 0), " &
"376 (BC_6, PCI2_GNT_L(1), bidir, 0, 377, 0, Z), " &
"377 (BC_2, *, control, 0), " &
"378 (BC_6, PCI2_GNT_L(2), bidir, 0, 379, 0, Z), " &
"379 (BC_2, *, control, 0), " &
"380 (BC_6, PCI2_GNT_L(3), bidir, 0, 381, 0, Z), " &
"381 (BC_2, *, control, 0), " &
"382 (BC_6, LWE_L(1), bidir, 0, 383, 0, Z), " &
"383 (BC_2, *, control, 0), " &
"384 (BC_6, LAD(8), bidir, 0, 385, 0, Z), " &
"385 (BC_2, *, control, 0), " &
"386 (BC_6, LBCTL, bidir, 0, 387, 0, Z), " &
"387 (BC_2, *, control, 0), " &
"388 (BC_6, LAD(13), bidir, 0, 385, 0, Z), " &
"389 (BC_6, LAD(2), bidir, 0, 385, 0, Z), " &
"390 (BC_6, LAD(5), bidir, 0, 393, 0, Z), " &
"391 (BC_6, LAD(10), bidir, 0, 393, 0, Z), " &
"392 (BC_6, LAD(4), bidir, 0, 393, 0, Z), " &
"393 (BC_2, *, control, 0), " &
"394 (BC_6, LAD(12), bidir, 0, 395, 0, Z), " &
"395 (BC_2, *, control, 0), " &
"396 (BC_6, LAD(1), bidir, 0, 395, 0, Z), " &
"397 (BC_6, LAD(3), bidir, 0, 395, 0, Z), " &
"398 (BC_6, LAD(7), bidir, 0, 395, 0, Z), " &
"399 (BC_6, LAD(6), bidir, 0, 403, 0, Z), " &
"400 (BC_6, LAD(9), bidir, 0, 403, 0, Z), " &
"401 (BC_6, LAD(15), bidir, 0, 403, 0, Z), " &
"402 (BC_6, LAD(0), bidir, 0, 403, 0, Z), " &
"403 (BC_2, *, control, 0), " &
"404 (BC_6, LALE, bidir, 0, 405, 0, Z), " &
"405 (BC_2, *, control, 0), " &
"406 (BC_6, LWE_L(0), bidir, 0, 407, 0, Z), " &
"407 (BC_2, *, control, 0), " &
"408 (BC_6, LDP(0), bidir, 0, 409, 0, Z), " &
"409 (BC_2, *, control, 0), " &
"410 (BC_6, LDP(1), bidir, 0, 409, 0, Z), " &
"411 (BC_6, LGPL5, bidir, 0, 412, 0, Z), " &
"412 (BC_2, *, control, 0), " &
"413 (BC_6, LAD(11), bidir, 0, 419, 0, Z), " &
"414 (BC_2, LCS_L(0), output3, 0, 415, 0, Z), " &
"415 (BC_2, *, control, 0), " &
"416 (BC_6, LGPL4, bidir, 0, 417, 0, Z), " &
"417 (BC_2, *, control, 0), " &
"418 (BC_6, LAD(14), bidir, 0, 419, 0, Z), " &
"419 (BC_2, *, control, 0), " &
"420 (BC_2, LCS_L(1), output3, 0, 421, 0, Z), " &
"421 (BC_2, *, control, 0), " &
"422 (BC_2, LCS_L(3), output3, 0, 421, 0, Z), " &
"423 (BC_6, IIC_SDA, bidir, 0, 424, 0, Z), " &
"424 (BC_2, *, control, 0), " &
"425 (BC_6, HRESET_REQ_L, bidir, 0, 426, 0, Z), " &
"426 (BC_2, *, control, 0), " &
"427 (BC_2, MCP_L, input, X), " &
"428 (BC_2, SRESET_L, input, X), " &
"429 (BC_6, IIC_SCL, bidir, 0, 430, 0, Z), " &
"430 (BC_2, *, control, 0), " &
"431 (BC_2, HRESET_L, input, X), " &
"432 (BC_6, ASLEEP, bidir, 0, 433, 0, Z), " &
"433 (BC_2, *, control, 0), " &
"434 (BC_2, SYSCLK, input, X), " &
"435 (BC_2, LCS_L(2), output3, 0, 421, 0, Z), " &
"436 (BC_6, LA(30), bidir, 0, 437, 0, Z), " &
"437 (BC_2, *, control, 0), " &
"438 (BC_6, LGPL3, bidir, 0, 439, 0, Z), " &
"439 (BC_2, *, control, 0), " &
"440 (BC_2, CLK_OUT, output3, 0, 441, 0, Z), " &
"441 (BC_2, *, control, 0), " &
"442 (BC_6, LWE_L(2), bidir, 0, 443, 0, Z), " &
"443 (BC_2, *, control, 0), " &
"444 (BC_2, LCLK(2), output3, 0, 445, 0, Z), " &
"445 (BC_2, *, control, 0), " &
"446 (BC_6, LA(31), bidir, 0, 437, 0, Z), " &
"447 (BC_6, LGPL2, bidir, 0, 448, 0, Z), " &
"448 (BC_2, *, control, 0), " &
"449 (BC_6, LAD(16), bidir, 0, 450, 0, Z), " &
"450 (BC_2, *, control, 0), " &
"451 (BC_6, LGPL1, bidir, 0, 452, 0, Z), " &
"452 (BC_2, *, control, 0), " &
"453 (BC_2, LCKE, output3, 0, 454, 0, Z), " &
"454 (BC_2, *, control, 0), " &
"455 (BC_6, LGPL0, bidir, 0, 456, 0, Z), " &
"456 (BC_2, *, control, 0), " &
"457 (BC_6, LDP(2), bidir, 0, 458, 0, Z), " &
"458 (BC_2, *, control, 0), " &
"459 (BC_6, LAD(21), bidir, 0, 450, 0, Z), " &
"460 (BC_6, LA(29), bidir, 0, 470, 0, Z), " &
"461 (BC_6, LA(27), bidir, 0, 470, 0, Z), " &
"462 (BC_2, LCLK(0), output3, 0, 463, 0, Z), " &
"463 (BC_2, *, control, 0), " &
"464 (BC_6, LAD(19), bidir, 0, 472, 0, Z), " &
"465 (BC_2, LCLK(1), output3, 0, 463, 0, Z), " &
"466 (BC_2, LCS_L(4), output3, 0, 467, 0, Z), " &
"467 (BC_2, *, control, 0), " &
"468 (BC_6, LAD(17), bidir, 0, 472, 0, Z), " &
"469 (BC_6, LA(28), bidir, 0, 470, 0, Z), " &
"470 (BC_2, *, control, 0), " &
"471 (BC_6, LAD(20), bidir, 0, 472, 0, Z), " &
"472 (BC_2, *, control, 0), " &
"473 (BC_6, LAD(18), bidir, 0, 472, 0, Z), " &
"474 (BC_2, PCI1_CLK, input, X), " &
"475 (BC_6, LCS_L_5, bidir, 0, 476, 0, Z), " &
"476 (BC_2, *, control, 0), " &
"477 (BC_2, LSYNC_IN, input, X), " &
"478 (BC_2, LCS_L_7, output3, 0, 479, 0, Z), " &
"479 (BC_2, *, control, 0), " &
"480 (BC_2, LSYNC_OUT, output3, 0, 481, 0, Z), " &
"481 (BC_2, *, control, 0), " &
"482 (BC_2, LCS_L_6, output3, 0, 483, 0, Z), " &
"483 (BC_2, *, control, 0), " &
"484 (BC_6, LAD(23), bidir, 0, 486, 0, Z), " &
"485 (BC_6, LAD(22), bidir, 0, 486, 0, Z), " &
"486 (BC_2, *, control, 0), " &
"487 (BC_6, LWE_L(3), bidir, 0, 443, 0, Z), " &
"488 (BC_6, LAD(24), bidir, 0, 489, 0, Z), " &
"489 (BC_2, *, control, 0), " &
"490 (BC_6, LAD(25), bidir, 0, 489, 0, Z), " &
"491 (BC_6, LDP(3), bidir, 0, 458, 0, Z), " &
"492 (BC_6, LAD(30), bidir, 0, 489, 0, Z), " &
"493 (BC_6, LAD(29), bidir, 0, 497, 0, Z), " &
"494 (BC_6, LAD(27), bidir, 0, 497, 0, Z), " &
"495 (BC_6, LAD(26), bidir, 0, 497, 0, Z), " &
"496 (BC_6, LAD(28), bidir, 0, 497, 0, Z), " &
"497 (BC_2, *, control, 0), " &
"498 (BC_2, PCI2_CLK, input, X), " &
"499 (BC_6, LAD(31), bidir, 0, 497, 0, Z), " &
"500 (BC_6, MDQ(4), bidir, 0, 502, 0, Z), " &
"501 (BC_6, MDQ(0), bidir, 0, 502, 0, Z), " &
"502 (BC_2, *, control, 0), " &
"503 (BC_2, MSYNC_IN, input, X), " &
"504 (BC_1, MSYNC_OUT, output3, 0, 505, 0, Z), " &
"505 (BC_2, *, control, 0), " &
"506 (BC_6, MDQ(5), bidir, 0, 502, 0, Z), " &
"507 (BC_6, MDQS(0), bidir, 0, 521, 0, Z), " &
"508 (BC_6, MDQ(1), bidir, 0, 502, 0, Z), " &
"509 (BC_6, MDM(0), bidir, 0, 510, 0, Z), " &
"510 (BC_2, *, control, 0), " &
"511 (BC_6, MA(4), bidir, 0, 514, 0, Z), " &
"512 (BC_6, MDQ(6), bidir, 0, 517, 0, Z), " &
"513 (BC_6, MA(0), bidir, 0, 514, 0, Z), " &
"514 (BC_2, *, control, 0), " &
"515 (BC_6, MDQ(3), bidir, 0, 517, 0, Z), " &
"516 (BC_6, MDQ(9), bidir, 0, 517, 0, Z), " &
"517 (BC_2, *, control, 0), " &
"518 (BC_6, MDQ(2), bidir, 0, 517, 0, Z), " &
"519 (BC_6, MDQ(7), bidir, 0, 525, 0, Z), " &
"520 (BC_6, MDQS(1), bidir, 0, 521, 0, Z), " &
"521 (BC_2, *, control, 0), " &
"522 (BC_6, MDQ(14), bidir, 0, 525, 0, Z), " &
"523 (BC_6, MDM(1), bidir, 0, 510, 0, Z), " &
"524 (BC_6, MDQ(12), bidir, 0, 525, 0, Z), " &
"525 (BC_2, *, control, 0), " &
"526 (BC_6, MDQ(8), bidir, 0, 525, 0, Z), " &
"527 (BC_6, MDQ(10), bidir, 0, 528, 0, Z), " &
"528 (BC_2, *, control, 0), " &
"529 (BC_6, MDQ(15), bidir, 0, 528, 0, Z), " &
"530 (BC_6, MDQ(13), bidir, 0, 528, 0, Z), " &
"531 (BC_1, MCK_L(4), output3, 0, 535, 0, Z), " &
"532 (BC_1, MCK(1), output3, 0, 533, 0, Z), " &
"533 (BC_2, *, control, 0), " &
"534 (BC_1, MCK(4), output3, 0, 535, 0, Z), " &
"535 (BC_2, *, control, 0), " &
"536 (BC_6, MDQ(11), bidir, 0, 528, 0, Z), " &
"537 (BC_1, MCKE_1, output3, 0, 538, 0, Z), " &
"538 (BC_2, *, control, 0), " &
"539 (BC_6, MA(8), bidir, 0, 543, 0, Z), " &
"540 (BC_6, MA(3), bidir, 0, 543, 0, Z), " &
"541 (BC_1, MCK_L(1), output3, 0, 533, 0, Z), " &
"542 (BC_6, MA(12), bidir, 0, 543, 0, Z), " &
"543 (BC_2, *, control, 0), " &
"544 (BC_6, MDM(2), bidir, 0, 545, 0, Z), " &
"545 (BC_2, *, control, 0), " &
"546 (BC_6, MCKE_0, bidir, 0, 547, 0, Z), " &
"547 (BC_2, *, control, 0), " &
"548 (BC_6, MA(9), bidir, 0, 543, 0, Z), " &
"549 (BC_6, MDQ(20), bidir, 0, 554, 0, Z), " &
"550 (BC_6, MDQS(2), bidir, 0, 521, 0, Z), " &
"551 (BC_6, MDQ(17), bidir, 0, 554, 0, Z), " &
"552 (BC_6, MDQ(21), bidir, 0, 554, 0, Z), " &
"553 (BC_6, MDQ(19), bidir, 0, 554, 0, Z), " &
"554 (BC_2, *, control, 0), " &
"555 (BC_6, MA(10), bidir, 0, 570, 0, Z), " &
"556 (BC_6, MDQ(16), bidir, 0, 557, 0, Z), " &
"557 (BC_2, *, control, 0), " &
"558 (BC_6, MDQ(22), bidir, 0, 557, 0, Z), " &
"559 (BC_6, MDM(3), bidir, 0, 545, 0, Z), " &
"560 (BC_6, MDQ(23), bidir, 0, 557, 0, Z), " &
"561 (BC_6, MDQ(18), bidir, 0, 557, 0, Z), " &
"562 (BC_6, MDQ(28), bidir, 0, 564, 0, Z), " &
"563 (BC_6, MDQ(25), bidir, 0, 564, 0, Z), " &
"564 (BC_2, *, control, 0), " &
"565 (BC_6, MDQ(30), bidir, 0, 564, 0, Z), " &
"566 (BC_6, MDQ(26), bidir, 0, 564, 0, Z), " &
"567 (BC_6, MA(2), bidir, 0, 570, 0, Z), " &
"568 (BC_6, MA(7), bidir, 0, 570, 0, Z), " &
"569 (BC_6, MA(11), bidir, 0, 570, 0, Z), " &
"570 (BC_2, *, control, 0), " &
"571 (BC_6, MDQ(27), bidir, 0, 574, 0, Z), " &
"572 (BC_6, MDQ(31), bidir, 0, 574, 0, Z), " &
"573 (BC_6, MDQ(24), bidir, 0, 574, 0, Z), " &
"574 (BC_2, *, control, 0), " &
"575 (BC_6, MDQ(29), bidir, 0, 574, 0, Z), " &
"576 (BC_6, MA(5), bidir, 0, 581, 0, Z), " &
"577 (BC_1, MCK_L(0), output3, 0, 579, 0, Z), " &
"578 (BC_1, MCK(0), output3, 0, 579, 0, Z), " &
"579 (BC_2, *, control, 0), " &
"580 (BC_6, MA(6), bidir, 0, 581, 0, Z), " &
"581 (BC_2, *, control, 0), " &
"582 (BC_6, MDQS(3), bidir, 0, 601, 0, Z), " &
"583 (BC_6, MECC(2), bidir, 0, 591, 0, Z), " &
"584 (BC_6, MDM(8), bidir, 0, 585, 0, Z), " &
"585 (BC_2, *, control, 0), " &
"586 (BC_1, MCK(3), output3, 0, 587, 0, Z), " &
"587 (BC_2, *, control, 0), " &
"588 (BC_1, MCK_L(3), output3, 0, 587, 0, Z), " &
"589 (BC_6, MECC(6), bidir, 0, 591, 0, Z), " &
"590 (BC_6, MECC(4), bidir, 0, 591, 0, Z), " &
"591 (BC_2, *, control, 0), " &
"592 (BC_6, MECC(1), bidir, 0, 591, 0, Z), " &
"593 (BC_6, MECC(0), bidir, 0, 594, 0, Z), " &
"594 (BC_2, *, control, 0), " &
"595 (BC_6, MECC(3), bidir, 0, 594, 0, Z), " &
"596 (BC_6, MBA(1), bidir, 0, 611, 0, Z), " &
"597 (BC_6, MDQS(8), bidir, 0, 601, 0, Z), " &
"598 (BC_6, MECC(5), bidir, 0, 594, 0, Z), " &
"599 (BC_6, MA(1), bidir, 0, 581, 0, Z), " &
"600 (BC_6, MDQS(4), bidir, 0, 601, 0, Z), " &
"601 (BC_2, *, control, 0), " &
"602 (BC_6, MECC(7), bidir, 0, 594, 0, Z), " &
"603 (BC_6, MDQ(35), bidir, 0, 604, 0, Z), " &
"604 (BC_2, *, control, 0), " &
"605 (BC_6, MDQ(37), bidir, 0, 604, 0, Z), " &
"606 (BC_6, MDQ(33), bidir, 0, 604, 0, Z), " &
"607 (BC_6, MDQ(36), bidir, 0, 609, 0, Z), " &
"608 (BC_6, MDQ(32), bidir, 0, 609, 0, Z), " &
"609 (BC_2, *, control, 0), " &
"610 (BC_6, MBA(0), bidir, 0, 611, 0, Z), " &
"611 (BC_2, *, control, 0), " &
"612 (BC_6, MDM(4), bidir, 0, 585, 0, Z), " &
"613 (BC_6, MRAS_L, bidir, 0, 614, 0, Z), " &
"614 (BC_2, *, control, 0), " &
"615 (BC_6, MDQ(38), bidir, 0, 609, 0, Z), " &
"616 (BC_2, *, control, 0), " &
"617 (BC_6, MCAS_L, bidir, 0, 618, 0, Z), " &
"618 (BC_2, *, control, 0), " &
"619 (BC_6, MDQ(34), bidir, 0, 616, 0, Z), " &
"620 (BC_6, MDQ(39), bidir, 0, 616, 0, Z), " &
"621 (BC_6, MCS_L(1), bidir, 0, 624, 0, Z), " &
"622 (BC_6, MDQ(40), bidir, 0, 616, 0, Z), " &
"623 (BC_6, MCS_L(0), bidir, 0, 624, 0, Z), " &
"624 (BC_2, *, control, 0), " &
"625 (BC_6, MWE_L, bidir, 0, 626, 0, Z), " &
"626 (BC_2, *, control, 0), " &
"627 (BC_6, MDQ(41), bidir, 0, 630, 0, Z), " &
"628 (BC_6, MDQS(5), bidir, 0, 658, 0, Z), " &
"629 (BC_6, MDQ(44), bidir, 0, 630, 0, Z), " &
"630 (BC_2, *, control, 0), " &
"631 (BC_6, MDQ(45), bidir, 0, 630, 0, Z), " &
"632 (BC_6, MDQ(42), bidir, 0, 639, 0, Z), " &
"633 (BC_6, MDQ(43), bidir, 0, 639, 0, Z), " &
"634 (BC_6, MDQ(47), bidir, 0, 639, 0, Z), " &
"635 (BC_6, MDM(5), bidir, 0, 636, 0, Z), " &
"636 (BC_2, *, control, 0), " &
"637 (BC_6, MCS_L(3), bidir, 0, 624, 0, Z), " &
"638 (BC_6, MDQ(48), bidir, 0, 639, 0, Z), " &
"639 (BC_2, *, control, 0), " &
"640 (BC_6, MCS_L(2), bidir, 0, 624, 0, Z), " &
"641 (BC_6, MDQ(46), bidir, 0, 643, 0, Z), " &
"642 (BC_6, MDQ(52), bidir, 0, 643, 0, Z), " &
"643 (BC_2, *, control, 0), " &
"644 (BC_1, MCK_L(2), output3, 0, 652, 0, Z), " &
"645 (BC_6, MDQ(53), bidir, 0, 643, 0, Z), " &
"646 (BC_6, MDQ(49), bidir, 0, 643, 0, Z), " &
"647 (BC_6, MDQ(55), bidir, 0, 649, 0, Z), " &
"648 (BC_6, MDQ(54), bidir, 0, 649, 0, Z), " &
"649 (BC_2, *, control, 0), " &
"650 (BC_6, MDQ(50), bidir, 0, 649, 0, Z), " &
"651 (BC_1, MCK(2), output3, 0, 652, 0, Z), " &
"652 (BC_2, *, control, 0), " &
"653 (BC_6, MDQ(51), bidir, 0, 649, 0, Z), " &
"654 (BC_6, MA(13), bidir, 0, 655, 0, Z), " &
"655 (BC_2, *, control, 0), " &
"656 (BC_6, MDM(6), bidir, 0, 636, 0, Z), " &
"657 (BC_6, MDQS(6), bidir, 0, 658, 0, Z), " &
"658 (BC_2, *, control, 0), " &
"659 (BC_6, MDQS(7), bidir, 0, 658, 0, Z), " &
"660 (BC_6, MDQ(56), bidir, 0, 665, 0, Z), " &
"661 (BC_6, MDM(7), bidir, 0, 636, 0, Z), " &
"662 (BC_6, MDQ(62), bidir, 0, 665, 0, Z), " &
"663 (BC_6, MDQ(57), bidir, 0, 665, 0, Z), " &
"664 (BC_6, MDQ(60), bidir, 0, 665, 0, Z), " &
"665 (BC_2, *, control, 0), " &
"666 (BC_1, MCK_L(5), output3, 0, 668, 0, Z), " &
"667 (BC_1, MCK(5), output3, 0, 668, 0, Z), " &
"668 (BC_2, *, control, 0), " &
"669 (BC_6, MDQ(59), bidir, 0, 672, 0, Z), " &
"670 (BC_6, MA(14), bidir, 0, 655, 0, Z), " &
"671 (BC_6, MDQ(58), bidir, 0, 672, 0, Z), " &
"672 (BC_2, *, control, 0), " &
"673 (BC_6, MDQ(63), bidir, 0, 672, 0, Z), " &
"674 (BC_6, MDQ(61), bidir, 0, 672, 0, Z), " &
"675 (BC_2, TSEC2_RXD(3), input, X), " &
"676 (BC_2, TSEC2_TX_EN, output3, 0, 677, 0, Z), " &
"677 (BC_2, *, control, 0), " &
"678 (BC_6, TSEC2_TXD_0, bidir, 0, 679, 0, Z), " &
"679 (BC_2, *, control, 0), " &
"680 (BC_2, TSEC2_RXD(5), input, X), " &
"681 (BC_2, TSEC2_RXD(4), input, X), " &
"682 (BC_2, TSEC2_TXD_6, output3, 0, 683, 0, Z), " &
"683 (BC_2, *, control, 0), " &
"684 (BC_2, TSEC2_TX_ER, output3, 0, 685, 0, Z), " &
"685 (BC_2, *, control, 0), " &
"686 (BC_2, TSEC2_RXD(0), input, X), " &
"687 (BC_2, TSEC1_TX_ER, output3, 0, 688, 0, Z), " &
"688 (BC_2, *, control, 0), " &
"689 (BC_2, TSEC2_TXD_7, output3, 0, 683, 0, Z), " &
"690 (BC_2, TSEC2_GTX_CLK, output3, 0, 691, 0, Z), " &
"691 (BC_2, *, control, 0), " &
"692 (BC_2, TSEC2_RXD(6), input, X), " &
"693 (BC_6, TSEC1_TXD_2, bidir, 0, 694, 0, Z), " &
"694 (BC_2, *, control, 0), " &
"695 (BC_2, TSEC2_TX_CLK, input, X), " &
"696 (BC_6, TSEC2_TXD_1, bidir, 0, 679, 0, Z), " &
"697 (BC_2, TSEC2_RXD(7), input, X), " &
"698 (BC_2, TSEC2_RXD(1), input, X), " &
"699 (BC_2, TSEC2_RX_CLK, input, X), " &
"700 (BC_2, TSEC2_RX_ER, input, X), " &
"701 (BC_2, TSEC1_TXD_5, output3, 0, 720, 0, Z), " &
"702 (BC_2, TSEC1_GTX_CLK, output3, 0, 703, 0, Z), " &
"703 (BC_2, *, control, 0), " &
"704 (BC_2, TSEC1_TX_EN, output3, 0, 705, 0, Z), " &
"705 (BC_2, *, control, 0), " &
"706 (BC_6, TSEC2_TXD_2, bidir, 0, 707, 0, Z), " &
"707 (BC_2, *, control, 0), " &
"708 (BC_2, TSEC1_RXD_5, input, X), " &
"709 (BC_2, TSEC1_TX_CLK, input, X), " &
"710 (BC_2, TSEC2_CRS, input, X), " &
"711 (BC_6, TSEC1_TXD_3, bidir, 0, 694, 0, Z), " &
"712 (BC_2, TSEC1_RXD_6, input, X), " &
"713 (BC_2, TSEC2_TXD_4, output3, 0, 714, 0, Z), " &
"714 (BC_2, *, control, 0), " &
"715 (BC_2, TSEC1_TXD_7, output3, 0, 720, 0, Z), " &
"716 (BC_6, TSEC2_TXD_3, bidir, 0, 707, 0, Z), " &
"717 (BC_2, TSEC1_TXD_6, output3, 0, 720, 0, Z), " &
"718 (BC_2, TSEC2_RX_DV, input, X), " &
"719 (BC_2, TSEC1_TXD_4, output3, 0, 720, 0, Z), " &
"720 (BC_2, *, control, 0), " &
"721 (BC_6, TSEC1_TXD_0, bidir, 0, 722, 0, Z), " &
"722 (BC_2, *, control, 0), " &
"723 (BC_2, TSEC1_CRS, input, X), " &
"724 (BC_6, TSEC1_RXD_0, bidir, 0, 725, 0, Z), " &
"725 (BC_2, *, control, 0), " &
"726 (BC_6, TSEC1_RXD_2, bidir, 0, 725, 0, Z), " &
"727 (BC_6, TSEC1_RXD_3, bidir, 0, 725, 0, Z), " &
"728 (BC_6, TSEC1_RXD_1, bidir, 0, 725, 0, Z), " &
"729 (BC_2, TSEC1_RX_DV, input, X), " &
"730 (BC_2, TSEC2_COL, input, X), " &
"731 (BC_2, TSEC1_RX_CLK, input, X), " &
"732 (BC_2, TSEC1_RX_ER, input, X), " &
"733 (BC_6, TSEC1_TXD_1, bidir, 0, 722, 0, Z), " &
"734 (BC_2, TSEC1_RXD_7, input, X), " &
"735 (BC_2, TSEC2_RXD(2), input, X), " &
"736 (BC_2, TSEC1_COL, input, X), " &
"737 (BC_2, TSEC1_RXD_4, input, X), " &
"738 (BC_2, TSEC2_TXD_5, output3, 0, 714, 0, Z), " &
"739 (BC_2, EC_GTX_CLK125, input, X) ";
-- tdi
end MPC8541;
