----------------------------------------------------------------------
-- BSDL Description for TMS470MFx100PZ --
-- Revised 22 April 2013 --
----------------------------------------------------------------------
-- Supported Devices: TMS470MFx100PZ Revision 1.0 --
----------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- : Marley Morrell --
-- BSDL Revision : 1.0 Released --
-- BSDL Revision : 0.1 originally created --
-- --
-- BSDL Status : Released --
-- Date Created : 07 October 2009 --
-- Revision : 1.0 --
----------------------------------------------------------------------
-- --
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-- Copyright (c) 2012, Texas Instruments Incorporated --
-------------------------------------------------------------------
entity TMS470MFx100PZ is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "PZ1");
-- This section declares all the ports in the design.
port (
MIBSPI2nSCS_0 : inout bit;
MIBSPI2nSCS_1 : inout bit;
MIBSPI2nSCS_2 : inout bit;
MIBSPI2nSCS_3 : inout bit;
GIOA_INT_4 : inout bit;
GIOA_INT_5 : inout bit;
CAN1TX : inout bit;
CAN1RX : inout bit;
GIOA_INT_6 : inout bit;
GIOA_INT_7 : inout bit;
MIBSPI2CLK : inout bit;
MIBSPI2SIMO : inout bit;
MIBSPI2SOMI : inout bit;
LIN_SCI1TX : inout bit;
LIN_SCI1RX : inout bit;
LIN_SCI2TX : inout bit;
LIN_SCI2RX : inout bit;
MIBSPI1nSCS_7 : inout bit;
MIBSPI1nSCS_6 : inout bit;
MIBSPI1nSCS_5 : inout bit;
MIBSPI1nSCS_4 : inout bit;
MIBSPI1nSCS_3 : inout bit;
MIBSPI1nSCS_2 : inout bit;
MIBSPI1nSCS_1 : inout bit;
MIBSPI1nSCS_0 : inout bit;
MIBSPI1CLK : inout bit;
MIBSPI1SIMO : inout bit;
MIBSPI1SOMI : inout bit;
CAN2TX : inout bit;
CAN2RX : inout bit;
HET_0 : inout bit;
HET_1 : inout bit;
TCK : in bit;
TDO : out bit;
TDI : in bit;
TMSC : in bit;
nTRST : in bit;
HET_2 : inout bit;
HET_3 : inout bit;
HET_4 : inout bit;
HET_5 : inout bit;
HET_6 : inout bit;
HET_7 : inout bit;
HET_8 : inout bit;
HET_9 : inout bit;
HET_10 : inout bit;
HET_11 : inout bit;
HET_12 : inout bit;
HET_13 : inout bit;
HET_14 : inout bit;
HET_15 : inout bit;
ADEVT : inout bit;
nPORRST : in bit;
MIBSPI2nENA : inout bit;
ECLK : inout bit;
TEST : in bit;
nRST : inout bit;
VCCIOR_1 : linkage bit;
ADIN_12 : linkage bit;
ADIN_4 : linkage bit;
ADIN_1 : linkage bit;
ADIN_2 : linkage bit;
VCCIOR_2 : linkage bit;
VCCAD : linkage bit;
ADIN_15 : linkage bit;
VCC_3 : linkage bit;
ADIN_14 : linkage bit;
ADIN_5 : linkage bit;
VCCIOR_5 : linkage bit;
ADIN_8 : linkage bit;
VCCIOR_6 : linkage bit;
ADIN_7 : linkage bit;
VSS_3 : linkage bit;
VCC_0 : linkage bit;
ADIN_10 : linkage bit;
ADIN_9 : linkage bit;
ADIN_13 : linkage bit;
FLTP1 : linkage bit;
FLTP2 : linkage bit;
VSS_7 : linkage bit;
AD_REFHI : linkage bit;
ADIN_3 : linkage bit;
VSS_4 : linkage bit;
VSS_1 : linkage bit;
VSS_6 : linkage bit;
ADIN_6 : linkage bit;
nENZ : linkage bit;
VSSAD : linkage bit;
VSS_5 : linkage bit;
OSCOUT : linkage bit;
ADIN_11 : linkage bit;
VCC_2 : linkage bit;
VSS_2 : linkage bit;
VCC_1 : linkage bit;
VCCIOR_4 : linkage bit;
VCCIOR_3 : linkage bit;
VCCP1 : linkage bit;
OSCIN : linkage bit;
VSS_0 : linkage bit;
AD_REFLO : linkage bit;
ADIN_0 : linkage bit
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of TMS470MFx100PZ: entity is "STD_1149_1_2001";
attribute PIN_MAP of TMS470MFx100PZ: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port.
constant PZ2: PIN_MAP_STRING :=
"MIBSPI2nSCS_0 : 1," &
"MIBSPI2nSCS_1 : 2," &
"MIBSPI2nSCS_2 : 3," &
"MIBSPI2nSCS_3 : 4," &
"GIOA_INT_4 : 5," &
"GIOA_INT_5 : 6," &
"CAN1TX : 7," &
"CAN1RX : 8," &
"VSS_0 : 9," &
"OSCIN : 10," &
"OSCOUT : 11," &
"VCC_0 : 12," &
"VSS_1 : 13," &
"VCCIOR_1 : 14," &
"GIOA_INT_6 : 15," &
"GIOA_INT_7 : 16," &
"MIBSPI2CLK : 17," &
"MIBSPI2SIMO : 18," &
"MIBSPI2SOMI : 19," &
"VCCIOR_2 : 20," &
"VSS_2 : 21," &
"LIN_SCI1TX : 22," &
"LIN_SCI1RX : 23," &
"LIN_SCI2TX : 24," &
"LIN_SCI2RX : 25," &
"MIBSPI1nSCS_7 : 26," &
"MIBSPI1nSCS_6 : 27," &
"MIBSPI1nSCS_5 : 28," &
"MIBSPI1nSCS_4 : 29," &
"MIBSPI1nSCS_3 : 30," &
"MIBSPI1nSCS_2 : 31," &
"MIBSPI1nSCS_1 : 32," &
"MIBSPI1nSCS_0 : 33," &
"MIBSPI1CLK : 34," &
"MIBSPI1SIMO : 35," &
"MIBSPI1SOMI : 36," &
"CAN2TX : 37," &
"CAN2RX : 38," &
"HET_0 : 39," &
"HET_1 : 40," &
"VCC_1 : 41," &
"VSS_3 : 42," &
"VCCIOR_3 : 43," &
"TCK : 44," &
"TDO : 45," &
"TDI : 46," &
"TMSC : 47," &
"nTRST : 48," &
"HET_2 : 49," &
"HET_3 : 50," &
"VSS_4 : 51," &
"VCCIOR_4 : 52," &
"HET_4 : 53," &
"HET_5 : 54," &
"HET_6 : 55," &
"HET_7 : 56," &
"HET_8 : 57," &
"HET_9 : 58," &
"HET_10 : 59," &
"HET_11 : 60," &
"HET_12 : 61," &
"HET_13 : 62," &
"HET_14 : 63," &
"HET_15 : 64," &
"VCCIOR_5 : 65," &
"VSS_5 : 66," &
"VCC_2 : 67," &
"ADEVT : 68," &
"ADIN_0 : 69," &
"ADIN_1 : 70," &
"ADIN_2 : 71," &
"ADIN_3 : 72," &
"ADIN_4 : 73," &
"ADIN_5 : 74," &
"ADIN_6 : 75," &
"ADIN_7 : 76," &
"ADIN_8 : 77," &
"ADIN_9 : 78," &
"ADIN_10 : 79," &
"ADIN_11 : 80," &
"ADIN_12 : 81," &
"AD_REFHI : 82," &
"AD_REFLO : 83," &
"VSSAD : 84," &
"VCCAD : 85," &
"ADIN_13 : 86," &
"ADIN_14 : 87," &
"ADIN_15 : 88," &
"nPORRST : 89," &
"MIBSPI2nENA : 90," &
"nENZ : 91," &
"VCC_3 : 92," &
"VSS_6 : 93," &
"VCCIOR_6 : 94," &
"VCCP1 : 95," &
"ECLK : 96," &
"TEST : 97," &
"FLTP1 : 98," &
"nRST : NC0," &
"FLTP2 : 99," &
"VSS_7 : 100";
constant PZ1: PIN_MAP_STRING :=
"MIBSPI2nSCS_0 : 1," &
"MIBSPI2nSCS_1 : 2," &
"MIBSPI2nSCS_2 : 3," &
"MIBSPI2nSCS_3 : 4," &
"GIOA_INT_4 : 5," &
"GIOA_INT_5 : 6," &
"CAN1TX : 7," &
"CAN1RX : 8," &
"VSS_0 : 9," &
"OSCIN : 10," &
"OSCOUT : 11," &
"VCC_0 : 12," &
"VSS_1 : 13," &
"VCCIOR_1 : 14," &
"GIOA_INT_6 : 15," &
"GIOA_INT_7 : 16," &
"MIBSPI2CLK : 17," &
"MIBSPI2SIMO : 18," &
"MIBSPI2SOMI : 19," &
"VCCIOR_2 : 20," &
"VSS_2 : 21," &
"LIN_SCI1TX : 22," &
"LIN_SCI1RX : 23," &
"LIN_SCI2TX : 24," &
"LIN_SCI2RX : 25," &
"MIBSPI1nSCS_7 : 26," &
"MIBSPI1nSCS_6 : 27," &
"MIBSPI1nSCS_5 : 28," &
"MIBSPI1nSCS_4 : 29," &
"MIBSPI1nSCS_3 : 30," &
"MIBSPI1nSCS_2 : 31," &
"MIBSPI1nSCS_1 : 32," &
"MIBSPI1nSCS_0 : 33," &
"MIBSPI1CLK : 34," &
"MIBSPI1SIMO : 35," &
"MIBSPI1SOMI : 36," &
"CAN2TX : 37," &
"CAN2RX : 38," &
"HET_0 : 39," &
"HET_1 : 40," &
"VCC_1 : 41," &
"VSS_3 : 42," &
"VCCIOR_3 : 43," &
"TCK : 44," &
"TDO : 45," &
"TDI : 46," &
"TMSC : 47," &
"nTRST : 48," &
"HET_2 : 49," &
"HET_3 : 50," &
"VSS_4 : 51," &
"VCCIOR_4 : 52," &
"HET_4 : 53," &
"HET_5 : 54," &
"HET_6 : 55," &
"HET_7 : 56," &
"HET_8 : 57," &
"HET_9 : 58," &
"HET_10 : 59," &
"HET_11 : 60," &
"HET_12 : 61," &
"HET_13 : 62," &
"HET_14 : 63," &
"HET_15 : 64," &
"VCCIOR_5 : 65," &
"VSS_5 : 66," &
"VCC_2 : 67," &
"ADEVT : 68," &
"ADIN_0 : 9," &
"ADIN_1 : 70," &
"ADIN_2 : 71," &
"ADIN_3 : 72," &
"ADIN_4 : 73," &
"ADIN_5 : 74," &
"ADIN_6 : 75," &
"ADIN_7 : 6," &
"ADIN_8 : 77," &
"ADIN_9 : 78," &
"ADIN_10 : 79," &
"ADIN_11 : 80," &
"ADIN_12 : 81," &
"AD_REFHI : 82," &
"AD_REFLO : 83," &
"VSSAD : 84," &
"VCCAD : 85," &
"ADIN_13 : 86," &
"ADIN_14 : 87," &
"ADIN_15 : 88," &
"nPORRST : 89," &
"MIBSPI2nENA : 90," &
"nENZ : 91," &
"VCC_3 : 92," &
"VSS_6 : 93," &
"VCCIOR_6 : 94," &
"VCCP1 : 95," &
"ECLK : 96," &
"TEST : 97," &
"nRST : 98," &
"FLTP2 : NC1," &
"FLTP1 : 99," &
"VSS_7 : 100";
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in
-- the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMSC : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of nTRST: signal is true;
-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
attribute COMPLIANCE_PATTERNS of TMS470MFx100PZ: entity is
"(nPORRST, TEST) (10)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of TMS470MFx100PZ: entity is 6;
-- Specifies the boundary-scan instructions implemented in the design and their
-- opcodes.
attribute INSTRUCTION_OPCODE of TMS470MFx100PZ: entity is
"IDCODE (000100),"&
"BYPASS (111111)," &
"EXTEST (011000)," &
"SAMPLE (011011)," &
"PRELOAD (011011)," &
"HIGHZ (011110)";
-- Specifies the bit pattern that is loaded into the instruction register when
-- the TAP controller passes through the Capture-IR state. The standard mandates
-- that the two LSBs must be "01". The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of TMS470MFx100PZ: entity is "000001";
attribute IDCODE_REGISTER of TMS470MFx100PZ : entity is
"XXXX" & -- Version
"1011100011011000" & -- Part Number
"00000010111" & -- Manufacturer ID
"1"; -- Required by the IEEE Std 1149.1 - 1990
-- This section specifies the test data register placed between TDI and TDO for
-- each implemented instruction.
attribute REGISTER_ACCESS of TMS470MFx100PZ: entity is
"BYPASS (BYPASS, HIGHZ)," &
"DEVICE_ID (IDCODE), " &
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of TMS470MFx100PZ: entity is 113;
-- The following list specifies the characteristics of each cell in the boundary
-- scan register from TDI to TDO. The following is a description of the label
-- fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not have a port
-- name.
-- function: Is the function of the cell as defined by the standard. Is one
-- of input, output2, output3, bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be loaded with
-- for safe operation when the software might otherwise choose a
-- random value.
-- ccell : The control cell number. Specifies the control cell that
-- drives the output enable for this port.
-- disval : Specifies the value that is loaded into the control cell to
-- disable the output enable for the corresponding port.
-- rslt : Resulting state. Shows the state of the driver when it is
-- disabled.
attribute BOUNDARY_REGISTER of TMS470MFx100PZ: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"112 ( BC_2, *, internal, X), " &
"111 ( BC_2, *, internal, X), " &
"110 ( BC_2, *, control, 1), " &
"109 ( BC_7, MIBSPI2nSCS_0, bidir, X, 110, 1, Z), " &
"108 ( BC_2, *, internal, X), " &
"107 ( BC_2, *, internal, X), " &
"106 ( BC_2, *, control, 1), " &
"105 ( BC_7, MIBSPI2nSCS_1, bidir, X, 106, 1, Z), " &
"104 ( BC_2, *, internal, X), " &
"103 ( BC_2, *, internal, X), " &
"102 ( BC_2, *, control, 1), " &
"101 ( BC_7, MIBSPI2nSCS_2, bidir, X, 102, 1, Z), " &
"100 ( BC_2, *, internal, X), " &
"99 ( BC_2, *, internal, X), " &
"98 ( BC_2, *, control, 1), " &
"97 ( BC_7, MIBSPI2nSCS_3, bidir, X, 98, 1, Z), " &
"96 ( BC_2, *, control, 1), " &
"95 ( BC_7, GIOA_INT_4, bidir, X, 96, 1, Z), " &
"94 ( BC_2, *, control, 1), " &
"93 ( BC_7, GIOA_INT_5, bidir, X, 94, 1, Z), " &
"92 ( BC_2, *, control, 1), " &
"91 ( BC_7, CAN1TX, bidir, X, 92, 1, Z), " &
"90 ( BC_2, *, control, 1), " &
"89 ( BC_7, CAN1RX, bidir, X, 90, 1, Z), " &
"88 ( BC_2, *, control, 1), " &
"87 ( BC_7, GIOA_INT_6, bidir, X, 88, 1, Z), " &
"86 ( BC_2, *, control, 1), " &
"85 ( BC_7, GIOA_INT_7, bidir, X, 86, 1, Z), " &
"84 ( BC_2, *, control, 1), " &
"83 ( BC_7, MIBSPI2CLK, bidir, X, 84, 1, Z), " &
"82 ( BC_2, *, control, 1), " &
"81 ( BC_7, MIBSPI2SIMO, bidir, X, 82, 1, Z), " &
"80 ( BC_2, *, control, 1), " &
"79 ( BC_7, MIBSPI2SOMI, bidir, X, 80, 1, Z), " &
"78 ( BC_2, *, control, 1), " &
"77 ( BC_7, LIN_SCI1TX, bidir, X, 78, 1, Z), " &
"76 ( BC_2, *, control, 1), " &
"75 ( BC_7, LIN_SCI1RX, bidir, X, 76, 1, Z), " &
"74 ( BC_2, *, control, 1), " &
"73 ( BC_7, LIN_SCI2TX, bidir, X, 74, 1, Z), " &
"72 ( BC_2, *, control, 1), " &
"71 ( BC_7, LIN_SCI2RX, bidir, X, 72, 1, Z), " &
"70 ( BC_2, *, control, 1), " &
"69 ( BC_7, MIBSPI1nSCS_7, bidir, X, 70, 1, Z), " &
"68 ( BC_2, *, control, 1), " &
"67 ( BC_7, MIBSPI1nSCS_6, bidir, X, 68, 1, Z), " &
"66 ( BC_2, *, control, 1), " &
"65 ( BC_7, MIBSPI1nSCS_5, bidir, X, 66, 1, Z), " &
"64 ( BC_2, *, control, 1), " &
"63 ( BC_7, MIBSPI1nSCS_4, bidir, X, 64, 1, Z), " &
"62 ( BC_2, *, control, 1), " &
"61 ( BC_7, MIBSPI1nSCS_3, bidir, X, 62, 1, Z), " &
"60 ( BC_2, *, control, 1), " &
"59 ( BC_7, MIBSPI1nSCS_2, bidir, X, 60, 1, Z), " &
"58 ( BC_2, *, control, 1), " &
"57 ( BC_7, MIBSPI1nSCS_1, bidir, X, 58, 1, Z), " &
"56 ( BC_2, *, control, 1), " &
"55 ( BC_7, MIBSPI1nSCS_0, bidir, X, 56, 1, Z), " &
"54 ( BC_2, *, control, 1), " &
"53 ( BC_7, MIBSPI1CLK, bidir, X, 54, 1, Z), " &
"52 ( BC_2, *, control, 1), " &
"51 ( BC_7, MIBSPI1SIMO, bidir, X, 52, 1, Z), " &
"50 ( BC_2, *, control, 1), " &
"49 ( BC_7, MIBSPI1SOMI, bidir, X, 50, 1, Z), " &
"48 ( BC_2, *, control, 1), " &
"47 ( BC_7, CAN2TX, bidir, X, 48, 1, Z), " &
"46 ( BC_2, *, control, 1), " &
"45 ( BC_7, CAN2RX, bidir, X, 46, 1, Z), " &
"44 ( BC_2, *, control, 1), " &
"43 ( BC_7, HET_0, bidir, X, 44, 1, Z), " &
"42 ( BC_2, *, control, 1), " &
"41 ( BC_7, HET_1, bidir, X, 42, 1, Z), " &
"40 ( BC_2, *, control, 1), " &
"39 ( BC_7, HET_2, bidir, X, 40, 1, Z), " &
"38 ( BC_2, *, control, 1), " &
"37 ( BC_7, HET_3, bidir, X, 38, 1, Z), " &
"36 ( BC_2, *, control, 1), " &
"35 ( BC_7, HET_4, bidir, X, 36, 1, Z), " &
"34 ( BC_2, *, control, 1), " &
"33 ( BC_7, HET_5, bidir, X, 34, 1, Z), " &
"32 ( BC_2, *, control, 1), " &
"31 ( BC_7, HET_6, bidir, X, 32, 1, Z), " &
"30 ( BC_2, *, control, 1), " &
"29 ( BC_7, HET_7, bidir, X, 30, 1, Z), " &
"28 ( BC_2, *, control, 1), " &
"27 ( BC_7, HET_8, bidir, X, 28, 1, Z), " &
"26 ( BC_2, *, control, 1), " &
"25 ( BC_7, HET_9, bidir, X, 26, 1, Z), " &
"24 ( BC_2, *, control, 1), " &
"23 ( BC_7, HET_10, bidir, X, 24, 1, Z), " &
"22 ( BC_2, *, control, 1), " &
"21 ( BC_7, HET_11, bidir, X, 22, 1, Z), " &
"20 ( BC_2, *, control, 1), " &
"19 ( BC_7, HET_12, bidir, X, 20, 1, Z), " &
"18 ( BC_2, *, control, 1), " &
"17 ( BC_7, HET_13, bidir, X, 18, 1, Z), " &
"16 ( BC_2, *, control, 1), " &
"15 ( BC_7, HET_14, bidir, X, 16, 1, Z), " &
"14 ( BC_2, *, control, 1), " &
"13 ( BC_7, HET_15, bidir, X, 14, 1, Z), " &
"12 ( BC_2, *, control, 1), " &
"11 ( BC_7, ADEVT, bidir, X, 12, 1, Z), " &
"10 ( BC_2, *, control, 1), " &
"9 ( BC_7, MIBSPI2nENA, bidir, X, 10, 1, Z), " &
"8 ( BC_2, *, control, 1), " &
"7 ( BC_7, ECLK, bidir, X, 8, 1, Z), " &
"6 ( BC_2, *, control, 1), " &
"5 ( BC_7, nRST, bidir, X, 6, 1, Z), " &
"4 ( BC_2, *, internal, 1), " &
"3 ( BC_2, *, internal, 1), " &
"2 ( BC_2, *, internal, 1), " &
"1 ( BC_2, *, internal, 1), " &
"0 ( BC_2, *, internal, 1) ";
attribute DESIGN_WARNING of TMS470MFx100PZ : entity is
"According to simulation, BSD JTAG TAP may not work correctly unless "&
" device has completed RESET sequence first. "&
"Forcing PORz low then release (no clock pulses required) would meet "&
" the requirement. "&
" "&
"In order to enter bscan mode correctly, TMS must be low at the "&
"rising edge of TRSTz and at least one cycle after TRSTz is high. ";
end TMS470MFx100PZ;