--------------------------------------------------------------------------------
-- Freescale Boundary Scan Description Language --
--------------------------------------------------------------------------------
-- Boundary Scan Description Language (IEEE 1149.6) --
-- --
-- Device : T2080 Revision 1.1 --
-- File Version : B --
-- File Name : T2080.R1B --
-- File created : July 13, 2015 --
-- Package type : FC-PBGA --
-- --
--------------------------------------------------------------------------------
-- Revision History: --
-- A - Original version --
-- B - Corrected OPCODE list for PRIVATE instructions --
-- --
-- NOTE: Active low ports are designated with a "_B" suffix. --
-- --
-- NOTE: The IEEE 1149.1 standard optional instructions HIGHZ, CLAMP, and --
-- IDCODE are supported. --
-- --
-- NOTE: The IEEE 1149.6 standard instructions EXTEST_TRAIN and EXTEST_PULSE --
-- are supported. This part is not fully 1149.6 compliant. Due to the --
-- configurable electrical levels that the SerDes channels can operate --
-- with, usage of a Public instruction, IOCONFIG, is required to be --
-- used before 1149.6 instructions in order to ensure their correct --
-- operation. --
-- --
-- WARNING: Incorrect or missing usage of the IOCONFIG can cause erroneous --
-- behavior of 1149.6 instructions. Please refer to Applications Note --
-- AN4788. --
-- --
-- WARNING: After Update-IR or Update-DR states while in the EXTEST, --
-- EXTEST_TRAIN, EXTEST_PULSE, or CLAMP instructions, usage of a --
-- transition through the optional Run-Test-Idle state to allow for --
-- the timing for input setup or output hold on non-TAP pins to be --
-- satisfied is recommended. --
-- --
-- NOTE: For assistance with this file, contact your sales office. --
-- --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- --
--============================================================================--
-- IMPORTANT NOTICE --
-- This information is provided on an AS IS basis and without warranty. --
-- IN NO EVENT SHALL FREESCALE BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL --
-- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF --
-- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR CUSTOMERS --
-- OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES WHETHER EXPRESS, --
-- IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY --
-- OR FITNESS FOR PARTICULAR PURPOSE. --
-- --
-- FREESCALE does not represent or warrant that the information furnished --
-- hereunder is free of infringement of any third party patents, --
-- copyrights, trade secrets, or other intellectual property rights. --
-- --
-- FREESCALE does not represent or warrant that the information is free of --
-- defect, or that it meets any particular standard, requirements or need --
-- of the user of the information or their customers. --
-- --
-- FREESCALE reserves the right to change the information in this file --
-- without notice. The BSDL files are also available at: --
-- --
-- http://www.freescale.com --
-- --
--============================================================================--
--
-- Device: T2080
-- Package Type: PBGA
--
entity T2080 is
generic (PHYSICAL_PIN_MAP : string := "PBGA");
-- PORT DESCRIPTION TERMS
-- in = input only
-- out = three-state output (0, Z, 1)
-- buffer = two-state output (0, 1)
-- inout = bidirectional
-- linkage = OTHER (vdd, vss, analog)
--
-- bit = single pin
-- bit_vector = group of pins with suffix 0 to n
port (
ASLEEP: inout bit;
CKSTP_OUT_B: inout bit;
CLK_OUT: inout bit;
D1_MA00: out bit;
D1_MA01: out bit;
D1_MA02: out bit;
D1_MA03: out bit;
D1_MA04: out bit;
D1_MA05: out bit;
D1_MA06: out bit;
D1_MA07: out bit;
D1_MA08: out bit;
D1_MA09: out bit;
D1_MA10: out bit;
D1_MA11: out bit;
D1_MA12: out bit;
D1_MA13: out bit;
D1_MA14: out bit;
D1_MA15: out bit;
D1_MAPAR_ERR_B: inout bit;
D1_MAPAR_OUT: out bit;
D1_MBA0: out bit;
D1_MBA1: out bit;
D1_MBA2: out bit;
D1_MCAS_B: out bit;
D1_MCK0: out bit;
D1_MCK0_B: out bit;
D1_MCK1: out bit;
D1_MCK1_B: out bit;
D1_MCK2: out bit;
D1_MCK2_B: out bit;
D1_MCK3: out bit;
D1_MCK3_B: out bit;
D1_MCKE0: out bit;
D1_MCKE1: out bit;
D1_MCKE2: out bit;
D1_MCKE3: out bit;
D1_MCS0_B: out bit;
D1_MCS1_B: out bit;
D1_MCS2_B: out bit;
D1_MCS3_B: out bit;
D1_MDM0: out bit;
D1_MDM1: out bit;
D1_MDM2: out bit;
D1_MDM3: out bit;
D1_MDM4: out bit;
D1_MDM5: out bit;
D1_MDM6: out bit;
D1_MDM7: out bit;
D1_MDM8: out bit;
D1_MDQ00: inout bit;
D1_MDQ01: inout bit;
D1_MDQ02: inout bit;
D1_MDQ03: inout bit;
D1_MDQ04: inout bit;
D1_MDQ05: inout bit;
D1_MDQ06: inout bit;
D1_MDQ07: inout bit;
D1_MDQ08: inout bit;
D1_MDQ09: inout bit;
D1_MDQ10: inout bit;
D1_MDQ11: inout bit;
D1_MDQ12: inout bit;
D1_MDQ13: inout bit;
D1_MDQ14: inout bit;
D1_MDQ15: inout bit;
D1_MDQ16: inout bit;
D1_MDQ17: inout bit;
D1_MDQ18: inout bit;
D1_MDQ19: inout bit;
D1_MDQ20: inout bit;
D1_MDQ21: inout bit;
D1_MDQ22: inout bit;
D1_MDQ23: inout bit;
D1_MDQ24: inout bit;
D1_MDQ25: inout bit;
D1_MDQ26: inout bit;
D1_MDQ27: inout bit;
D1_MDQ28: inout bit;
D1_MDQ29: inout bit;
D1_MDQ30: inout bit;
D1_MDQ31: inout bit;
D1_MDQ32: inout bit;
D1_MDQ33: inout bit;
D1_MDQ34: inout bit;
D1_MDQ35: inout bit;
D1_MDQ36: inout bit;
D1_MDQ37: inout bit;
D1_MDQ38: inout bit;
D1_MDQ39: inout bit;
D1_MDQ40: inout bit;
D1_MDQ41: inout bit;
D1_MDQ42: inout bit;
D1_MDQ43: inout bit;
D1_MDQ44: inout bit;
D1_MDQ45: inout bit;
D1_MDQ46: inout bit;
D1_MDQ47: inout bit;
D1_MDQ48: inout bit;
D1_MDQ49: inout bit;
D1_MDQ50: inout bit;
D1_MDQ51: inout bit;
D1_MDQ52: inout bit;
D1_MDQ53: inout bit;
D1_MDQ54: inout bit;
D1_MDQ55: inout bit;
D1_MDQ56: inout bit;
D1_MDQ57: inout bit;
D1_MDQ58: inout bit;
D1_MDQ59: inout bit;
D1_MDQ60: inout bit;
D1_MDQ61: inout bit;
D1_MDQ62: inout bit;
D1_MDQ63: inout bit;
D1_MDQS0: inout bit;
D1_MDQS0_B: inout bit;
D1_MDQS1: inout bit;
D1_MDQS1_B: inout bit;
D1_MDQS2: inout bit;
D1_MDQS2_B: inout bit;
D1_MDQS3: inout bit;
D1_MDQS3_B: inout bit;
D1_MDQS4: inout bit;
D1_MDQS4_B: inout bit;
D1_MDQS5: inout bit;
D1_MDQS5_B: inout bit;
D1_MDQS6: inout bit;
D1_MDQS6_B: inout bit;
D1_MDQS7: inout bit;
D1_MDQS7_B: inout bit;
D1_MDQS8: inout bit;
D1_MDQS8_B: inout bit;
D1_MECC0: inout bit;
D1_MECC1: inout bit;
D1_MECC2: inout bit;
D1_MECC3: inout bit;
D1_MECC4: inout bit;
D1_MECC5: inout bit;
D1_MECC6: inout bit;
D1_MECC7: inout bit;
D1_MODT0: out bit;
D1_MODT1: out bit;
D1_MODT2: out bit;
D1_MODT3: out bit;
D1_MRAS_B: out bit;
D1_MWE_B: out bit;
DDRCLK: in bit;
DMA1_DACK0_B: inout bit;
DMA1_DDONE0_B: inout bit;
DMA1_DREQ0_B: inout bit;
DMA2_DACK0_B: inout bit;
DMA2_DDONE0_B: inout bit;
DMA2_DREQ0_B: inout bit;
EC1_GTX_CLK: inout bit;
EC1_GTX_CLK125: inout bit;
EC1_RXD0: inout bit;
EC1_RXD1: inout bit;
EC1_RXD2: inout bit;
EC1_RXD3: inout bit;
EC1_RX_CLK: inout bit;
EC1_RX_CTL: inout bit;
EC1_TXD0: inout bit;
EC1_TXD1: inout bit;
EC1_TXD2: inout bit;
EC1_TXD3: inout bit;
EC1_TX_CTL: inout bit;
EC2_GTX_CLK: inout bit;
EC2_GTX_CLK125: inout bit;
EC2_RXD0: inout bit;
EC2_RXD1: inout bit;
EC2_RXD2: inout bit;
EC2_RXD3: inout bit;
EC2_RX_CLK: inout bit;
EC2_RX_CTL: inout bit;
EC2_TXD0: inout bit;
EC2_TXD1: inout bit;
EC2_TXD2: inout bit;
EC2_TXD3: inout bit;
EC2_TX_CTL: inout bit;
EMI1_MDC: inout bit;
EMI1_MDIO: inout bit;
EMI2_MDC: out bit;
EMI2_MDIO: out bit;
EVT0_B: inout bit;
EVT1_B: inout bit;
EVT2_B: inout bit;
EVT3_B: inout bit;
EVT4_B: inout bit;
HRESET_B: inout bit;
IFC_A16: inout bit;
IFC_A17: inout bit;
IFC_A18: inout bit;
IFC_A19: inout bit;
IFC_A20: inout bit;
IFC_A21: inout bit;
IFC_A22: inout bit;
IFC_A23: inout bit;
IFC_A24: inout bit;
IFC_A25: inout bit;
IFC_A26: inout bit;
IFC_A27: inout bit;
IFC_A28: inout bit;
IFC_A29: inout bit;
IFC_A30: inout bit;
IFC_A31: inout bit;
IFC_AD00: inout bit;
IFC_AD01: inout bit;
IFC_AD02: inout bit;
IFC_AD03: inout bit;
IFC_AD04: inout bit;
IFC_AD05: inout bit;
IFC_AD06: inout bit;
IFC_AD07: inout bit;
IFC_AD08: inout bit;
IFC_AD09: inout bit;
IFC_AD10: inout bit;
IFC_AD11: inout bit;
IFC_AD12: inout bit;
IFC_AD13: inout bit;
IFC_AD14: inout bit;
IFC_AD15: inout bit;
IFC_AVD: inout bit;
IFC_BCTL: inout bit;
IFC_CLE: inout bit;
IFC_CLK0: inout bit;
IFC_CLK1: inout bit;
IFC_CS0_B: inout bit;
IFC_CS1_B: inout bit;
IFC_CS2_B: inout bit;
IFC_CS3_B: inout bit;
IFC_CS4_B: inout bit;
IFC_CS5_B: inout bit;
IFC_CS6_B: inout bit;
IFC_CS7_B: inout bit;
IFC_NDDDR_CLK: inout bit;
IFC_NDDQS: inout bit;
IFC_OE_B: inout bit;
IFC_PAR0: inout bit;
IFC_PAR1: inout bit;
IFC_PERR_B: inout bit;
IFC_RB0_B: inout bit;
IFC_RB1_B: inout bit;
IFC_TE: inout bit;
IFC_WE0_B: inout bit;
IFC_WP0_B: inout bit;
IIC1_SCL: inout bit;
IIC1_SDA: inout bit;
IIC2_SCL: inout bit;
IIC2_SDA: inout bit;
IIC3_SCL: inout bit;
IIC3_SDA: inout bit;
IIC4_SCL: inout bit;
IIC4_SDA: inout bit;
IRQ00: inout bit;
IRQ01: inout bit;
IRQ02: inout bit;
IRQ03: inout bit;
IRQ04: inout bit;
IRQ05: inout bit;
IRQ06: inout bit;
IRQ07: inout bit;
IRQ08: inout bit;
IRQ09: inout bit;
IRQ10: inout bit;
IRQ11: inout bit;
IRQ_OUT_B: inout bit;
LP_TMP_DETECT_B: in bit;
PORESET_B: in bit;
RESET_REQ_B: inout bit;
RTC: inout bit;
SCAN_MODE_B: in bit;
SD1_PLL1_TPD: out bit;
SD1_PLL2_TPD: out bit;
SD1_REF_CLK1_N: in bit;
SD1_REF_CLK1_P: in bit;
SD1_REF_CLK2_N: in bit;
SD1_REF_CLK2_P: in bit;
SD1_RX0_N: in bit;
SD1_RX0_P: in bit;
SD1_RX1_N: in bit;
SD1_RX1_P: in bit;
SD1_RX2_N: in bit;
SD1_RX2_P: in bit;
SD1_RX3_N: in bit;
SD1_RX3_P: in bit;
SD1_RX4_N: in bit;
SD1_RX4_P: in bit;
SD1_RX5_N: in bit;
SD1_RX5_P: in bit;
SD1_RX6_N: in bit;
SD1_RX6_P: in bit;
SD1_RX7_N: in bit;
SD1_RX7_P: in bit;
SD1_TX0_N: out bit;
SD1_TX0_P: out bit;
SD1_TX1_N: out bit;
SD1_TX1_P: out bit;
SD1_TX2_N: out bit;
SD1_TX2_P: out bit;
SD1_TX3_N: out bit;
SD1_TX3_P: out bit;
SD1_TX4_N: out bit;
SD1_TX4_P: out bit;
SD1_TX5_N: out bit;
SD1_TX5_P: out bit;
SD1_TX6_N: out bit;
SD1_TX6_P: out bit;
SD1_TX7_N: out bit;
SD1_TX7_P: out bit;
SD2_PLL1_TPD: out bit;
SD2_PLL2_TPD: out bit;
SD2_REF_CLK1_N: in bit;
SD2_REF_CLK1_P: in bit;
SD2_REF_CLK2_N: in bit;
SD2_REF_CLK2_P: in bit;
SD2_RX0_N: in bit;
SD2_RX0_P: in bit;
SD2_RX1_N: in bit;
SD2_RX1_P: in bit;
SD2_RX2_N: in bit;
SD2_RX2_P: in bit;
SD2_RX3_N: in bit;
SD2_RX3_P: in bit;
SD2_RX4_N: in bit;
SD2_RX4_P: in bit;
SD2_RX5_N: in bit;
SD2_RX5_P: in bit;
SD2_RX6_N: in bit;
SD2_RX6_P: in bit;
SD2_RX7_N: in bit;
SD2_RX7_P: in bit;
SD2_TX0_N: out bit;
SD2_TX0_P: out bit;
SD2_TX1_N: out bit;
SD2_TX1_P: out bit;
SD2_TX2_N: out bit;
SD2_TX2_P: out bit;
SD2_TX3_N: out bit;
SD2_TX3_P: out bit;
SD2_TX4_N: out bit;
SD2_TX4_P: out bit;
SD2_TX5_N: out bit;
SD2_TX5_P: out bit;
SD2_TX6_N: out bit;
SD2_TX6_P: out bit;
SD2_TX7_N: out bit;
SD2_TX7_P: out bit;
SDHC_CD_B: inout bit;
SDHC_CLK: inout bit;
SDHC_CMD: inout bit;
SDHC_DAT0: inout bit;
SDHC_DAT1: inout bit;
SDHC_DAT2: inout bit;
SDHC_DAT3: inout bit;
SDHC_WP: inout bit;
SPI_CLK: inout bit;
SPI_CS0_B: inout bit;
SPI_CS1_B: inout bit;
SPI_CS2_B: inout bit;
SPI_CS3_B: inout bit;
SPI_MISO: inout bit;
SPI_MOSI: inout bit;
SYSCLK: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TEST_SEL_B: in bit;
TMP_DETECT_B: inout bit;
TMS: in bit;
TRST_B: in bit;
TSEC_1588_ALARM_OUT1: inout bit;
TSEC_1588_ALARM_OUT2: inout bit;
TSEC_1588_CLK_IN: inout bit;
TSEC_1588_CLK_OUT: inout bit;
TSEC_1588_PULSE_OUT1: inout bit;
TSEC_1588_PULSE_OUT2: inout bit;
TSEC_1588_TRIG_IN1: inout bit;
TSEC_1588_TRIG_IN2: inout bit;
UART1_CTS_B: inout bit;
UART1_RTS_B: inout bit;
UART1_SIN: inout bit;
UART1_SOUT: inout bit;
UART2_CTS_B: inout bit;
UART2_RTS_B: inout bit;
UART2_SIN: inout bit;
UART2_SOUT: inout bit;
USB1_DRVVBUS: out bit;
USB1_PWRFAULT: in bit;
USB1_UDM: inout bit;
USB1_UDP: inout bit;
USB1_UID: in bit;
USB1_VBUSCLMP: in bit;
USB2_DRVVBUS: out bit;
USB2_PWRFAULT: in bit;
USB2_UDM: inout bit;
USB2_UDP: inout bit;
USB2_UID: in bit;
USB2_VBUSCLMP: in bit;
USBCLK: inout bit;
AGND_SD1_PLL1: linkage bit;
AGND_SD1_PLL2: linkage bit;
AGND_SD2_PLL1: linkage bit;
AGND_SD2_PLL2: linkage bit;
AVDD_CGA1: linkage bit;
AVDD_CGA2: linkage bit;
AVDD_D1: linkage bit;
AVDD_PLAT: linkage bit;
AVDD_SD1_PLL1: linkage bit;
AVDD_SD1_PLL2: linkage bit;
AVDD_SD2_PLL1: linkage bit;
AVDD_SD2_PLL2: linkage bit;
CVDD: linkage bit_vector(0 to 1);
D1_MDIC0: linkage bit;
D1_MDIC1: linkage bit;
D1_MVREF: linkage bit;
D1_TPA: linkage bit;
DVDD: linkage bit_vector(0 to 1);
FA_ANALOG_G_V: linkage bit;
FA_ANALOG_PIN: linkage bit;
FA_VL: linkage bit;
G1VDD: linkage bit_vector(0 to 24);
GND: linkage bit_vector(0 to 179);
LVDD: linkage bit_vector(0 to 2);
NC: linkage bit_vector(0 to 8);
OVDD: linkage bit_vector(0 to 10);
PROG_MTR: linkage bit;
PROG_SFP: linkage bit;
S1GND: linkage bit_vector(0 to 34);
S1VDD: linkage bit_vector(0 to 5);
S2GND: linkage bit_vector(0 to 43);
S2VDD: linkage bit_vector(0 to 5);
SD1_IMP_CAL_RX: linkage bit;
SD1_IMP_CAL_TX: linkage bit;
SD1_PLL1_TPA: linkage bit;
SD1_PLL2_TPA: linkage bit;
SD2_IMP_CAL_RX: linkage bit;
SD2_IMP_CAL_TX: linkage bit;
SD2_PLL1_TPA: linkage bit;
SD2_PLL2_TPA: linkage bit;
SENSEGND: linkage bit;
SENSEVDD: linkage bit;
TD1_ANODE: linkage bit;
TD1_CATHODE: linkage bit;
TH_TPA: linkage bit;
TH_VDD: linkage bit;
USB_AGND: linkage bit_vector(0 to 9);
USB_HVDD: linkage bit_vector(0 to 1);
USB_IBIAS_REXT: linkage bit;
USB_OVDD: linkage bit_vector(0 to 1);
USB_SVDD: linkage bit_vector(0 to 1);
VDD: linkage bit_vector(0 to 59);
VDD_LP: linkage bit;
X1GND: linkage bit_vector(0 to 21);
X1VDD: linkage bit_vector(0 to 6);
X2GND: linkage bit_vector(0 to 25);
X2VDD: linkage bit_vector(0 to 5));
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
attribute COMPONENT_CONFORMANCE of T2080: entity is "STD_1149_1_2001";
attribute PIN_MAP of T2080: entity is PHYSICAL_PIN_MAP;
constant PBGA :PIN_MAP_STRING :=
"ASLEEP: A11," &
"CKSTP_OUT_B: D20," &
"CLK_OUT: E10," &
"D1_MA00: Y30," &
"D1_MA01: W29," &
"D1_MA02: M30," &
"D1_MA03: L30," &
"D1_MA04: L29," &
"D1_MA05: J30," &
"D1_MA06: J29," &
"D1_MA07: G29," &
"D1_MA08: H30," &
"D1_MA09: F30," &
"D1_MA10: AB30," &
"D1_MA11: G30," &
"D1_MA12: E29," &
"D1_MA13: AG29," &
"D1_MA14: D30," &
"D1_MA15: C29," &
"D1_MAPAR_ERR_B: E30," &
"D1_MAPAR_OUT: AA30," &
"D1_MBA0: AC30," &
"D1_MBA1: AA29," &
"D1_MBA2: D28," &
"D1_MCAS_B: AE29," &
"D1_MCK0: P30," &
"D1_MCK0_B: N30," &
"D1_MCK1: R30," &
"D1_MCK1_B: R29," &
"D1_MCK2: U29," &
"D1_MCK2_B: U30," &
"D1_MCK3: W30," &
"D1_MCK3_B: V30," &
"D1_MCKE0: B29," &
"D1_MCKE1: B28," &
"D1_MCKE2: C30," &
"D1_MCKE3: A28," &
"D1_MCS0_B: AD30," &
"D1_MCS1_B: AH30," &
"D1_MCS2_B: AK28," &
"D1_MCS3_B: AJ28," &
"D1_MDM0: A25," &
"D1_MDM1: E27," &
"D1_MDM2: G26," &
"D1_MDM3: K25," &
"D1_MDM4: T28," &
"D1_MDM5: W25," &
"D1_MDM6: AA26," &
"D1_MDM7: AJ27," &
"D1_MDM8: P25," &
"D1_MDQ00: B24," &
"D1_MDQ01: A24," &
"D1_MDQ02: C25," &
"D1_MDQ03: D24," &
"D1_MDQ04: D25," &
"D1_MDQ05: C26," &
"D1_MDQ06: B27," &
"D1_MDQ07: C27," &
"D1_MDQ08: H23," &
"D1_MDQ09: G23," &
"D1_MDQ10: F24," &
"D1_MDQ11: F25," &
"D1_MDQ12: E25," &
"D1_MDQ13: E26," &
"D1_MDQ14: D27," &
"D1_MDQ15: G25," &
"D1_MDQ16: J23," &
"D1_MDQ17: H24," &
"D1_MDQ18: H25," &
"D1_MDQ19: J26," &
"D1_MDQ20: J25," &
"D1_MDQ21: J27," &
"D1_MDQ22: H28," &
"D1_MDQ23: K28," &
"D1_MDQ24: L23," &
"D1_MDQ25: M25," &
"D1_MDQ26: K24," &
"D1_MDQ27: K27," &
"D1_MDQ28: M24," &
"D1_MDQ29: L27," &
"D1_MDQ30: M27," &
"D1_MDQ31: M28," &
"D1_MDQ32: T27," &
"D1_MDQ33: V27," &
"D1_MDQ34: U25," &
"D1_MDQ35: U26," &
"D1_MDQ36: R25," &
"D1_MDQ37: T25," &
"D1_MDQ38: T24," &
"D1_MDQ39: U23," &
"D1_MDQ40: Y28," &
"D1_MDQ41: Y27," &
"D1_MDQ42: Y25," &
"D1_MDQ43: Y24," &
"D1_MDQ44: V25," &
"D1_MDQ45: Y23," &
"D1_MDQ46: V24," &
"D1_MDQ47: W23," &
"D1_MDQ48: AA27," &
"D1_MDQ49: AB28," &
"D1_MDQ50: AB27," &
"D1_MDQ51: AC27," &
"D1_MDQ52: AB24," &
"D1_MDQ53: AB23," &
"D1_MDQ54: AA23," &
"D1_MDQ55: AA25," &
"D1_MDQ56: AD28," &
"D1_MDQ57: AD27," &
"D1_MDQ58: AE27," &
"D1_MDQ59: AC25," &
"D1_MDQ60: AF28," &
"D1_MDQ61: AF27," &
"D1_MDQ62: AG27," &
"D1_MDQ63: AE26," &
"D1_MDQS0: A26," &
"D1_MDQS0_B: B25," &
"D1_MDQS1: F28," &
"D1_MDQS1_B: F27," &
"D1_MDQS2: G27," &
"D1_MDQS2_B: H27," &
"D1_MDQS3: L26," &
"D1_MDQS3_B: L25," &
"D1_MDQS4: V28," &
"D1_MDQS4_B: U27," &
"D1_MDQS5: W27," &
"D1_MDQS5_B: W26," &
"D1_MDQS6: AB25," &
"D1_MDQS6_B: AC26," &
"D1_MDQS7: AH26," &
"D1_MDQS7_B: AH27," &
"D1_MDQS8: P27," &
"D1_MDQS8_B: P28," &
"D1_MECC0: N25," &
"D1_MECC1: N23," &
"D1_MECC2: N26," &
"D1_MECC3: N27," &
"D1_MECC4: R27," &
"D1_MECC5: R26," &
"D1_MECC6: R23," &
"D1_MECC7: P24," &
"D1_MODT0: AG30," &
"D1_MODT1: AH29," &
"D1_MODT2: AF30," &
"D1_MODT3: AJ29," &
"D1_MRAS_B: AC29," &
"D1_MWE_B: AE30," &
"DDRCLK: E23," &
"DMA1_DACK0_B: E1," &
"DMA1_DDONE0_B: K5," &
"DMA1_DREQ0_B: L5," &
"DMA2_DACK0_B: H1," &
"DMA2_DDONE0_B: G3," &
"DMA2_DREQ0_B: F3," &
"EC1_GTX_CLK: P1," &
"EC1_GTX_CLK125: M2," &
"EC1_RXD0: R5," &
"EC1_RXD1: N5," &
"EC1_RXD2: N6," &
"EC1_RXD3: L1," &
"EC1_RX_CLK: M4," &
"EC1_RX_CTL: L3," &
"EC1_TXD0: T6," &
"EC1_TXD1: N1," &
"EC1_TXD2: N2," &
"EC1_TXD3: R4," &
"EC1_TX_CTL: M3," &
"EC2_GTX_CLK: T1," &
"EC2_GTX_CLK125: V1," &
"EC2_RXD0: R1," &
"EC2_RXD1: T2," &
"EC2_RXD2: U4," &
"EC2_RXD3: R2," &
"EC2_RX_CLK: V6," &
"EC2_RX_CTL: U6," &
"EC2_TXD0: W6," &
"EC2_TXD1: U5," &
"EC2_TXD2: U3," &
"EC2_TXD3: V5," &
"EC2_TX_CTL: R3," &
"EMI1_MDC: T5," &
"EMI1_MDIO: N3," &
"EMI2_MDC: B3," &
"EMI2_MDIO: F5," &
"EVT0_B: A12," &
"EVT1_B: B12," &
"EVT2_B: G12," &
"EVT3_B: C11," &
"EVT4_B: F12," &
"HRESET_B: F11," &
"IFC_A16: G15," &
"IFC_A17: C15," &
"IFC_A18: D15," &
"IFC_A19: G14," &
"IFC_A20: A16," &
"IFC_A21: B14," &
"IFC_A22: J15," &
"IFC_A23: B18," &
"IFC_A24: C16," &
"IFC_A25: E17," &
"IFC_A26: D16," &
"IFC_A27: G17," &
"IFC_A28: F16," &
"IFC_A29: G16," &
"IFC_A30: B21," &
"IFC_A31: E16," &
"IFC_AD00: A13," &
"IFC_AD01: G13," &
"IFC_AD02: C14," &
"IFC_AD03: D13," &
"IFC_AD04: A15," &
"IFC_AD05: F13," &
"IFC_AD06: E14," &
"IFC_AD07: J13," &
"IFC_AD08: E13," &
"IFC_AD09: F14," &
"IFC_AD10: H14," &
"IFC_AD11: A14," &
"IFC_AD12: C13," &
"IFC_AD13: B15," &
"IFC_AD14: F15," &
"IFC_AD15: D14," &
"IFC_AVD: C17," &
"IFC_BCTL: H18," &
"IFC_CLE: H19," &
"IFC_CLK0: A22," &
"IFC_CLK1: B20," &
"IFC_CS0_B: H16," &
"IFC_CS1_B: F17," &
"IFC_CS2_B: D19," &
"IFC_CS3_B: B17," &
"IFC_CS4_B: E19," &
"IFC_CS5_B: C18," &
"IFC_CS6_B: D21," &
"IFC_CS7_B: G19," &
"IFC_NDDDR_CLK: D18," &
"IFC_NDDQS: J19," &
"IFC_OE_B: G18," &
"IFC_PAR0: F18," &
"IFC_PAR1: A17," &
"IFC_PERR_B: F19," &
"IFC_RB0_B: J17," &
"IFC_RB1_B: C19," &
"IFC_TE: A19," &
"IFC_WE0_B: D17," &
"IFC_WP0_B: A18," &
"IIC1_SCL: H3," &
"IIC1_SDA: G2," &
"IIC2_SCL: H4," &
"IIC2_SDA: K2," &
"IIC3_SCL: J6," &
"IIC3_SDA: J2," &
"IIC4_SCL: K1," &
"IIC4_SDA: M1," &
"IRQ00: G11," &
"IRQ01: E11," &
"IRQ02: D10," &
"IRQ03: C10," &
"IRQ04: H12," &
"IRQ05: D11," &
"IRQ06: P5," &
"IRQ07: P3," &
"IRQ08: P6," &
"IRQ09: P4," &
"IRQ10: J5," &
"IRQ11: D1," &
"IRQ_OUT_B: C12," &
"LP_TMP_DETECT_B: R7," &
"PORESET_B: F10," &
"RESET_REQ_B: D12," &
"RTC: A20," &
"SCAN_MODE_B: H11," &
"SD1_PLL1_TPD: AE14," &
"SD1_PLL2_TPD: AG25," &
"SD1_REF_CLK1_N: AK15," &
"SD1_REF_CLK1_P: AJ15," &
"SD1_REF_CLK2_N: AK25," &
"SD1_REF_CLK2_P: AJ25," &
"SD1_RX0_N: AH13," &
"SD1_RX0_P: AH12," &
"SD1_RX1_N: AJ13," &
"SD1_RX1_P: AK13," &
"SD1_RX2_N: AK17," &
"SD1_RX2_P: AJ17," &
"SD1_RX3_N: AH18," &
"SD1_RX3_P: AH17," &
"SD1_RX4_N: AK20," &
"SD1_RX4_P: AJ20," &
"SD1_RX5_N: AH21," &
"SD1_RX5_P: AH20," &
"SD1_RX6_N: AK23," &
"SD1_RX6_P: AJ23," &
"SD1_RX7_N: AH24," &
"SD1_RX7_P: AH23," &
"SD1_TX0_N: AG15," &
"SD1_TX0_P: AG14," &
"SD1_TX1_N: AF16," &
"SD1_TX1_P: AE16," &
"SD1_TX2_N: AD19," &
"SD1_TX2_P: AD18," &
"SD1_TX3_N: AE18," &
"SD1_TX3_P: AF18," &
"SD1_TX4_N: AD21," &
"SD1_TX4_P: AD20," &
"SD1_TX5_N: AE21," &
"SD1_TX5_P: AF21," &
"SD1_TX6_N: AE23," &
"SD1_TX6_P: AF23," &
"SD1_TX7_N: AD24," &
"SD1_TX7_P: AD23," &
"SD2_PLL1_TPD: AC8," &
"SD2_PLL2_TPD: AF11," &
"SD2_REF_CLK1_N: AD5," &
"SD2_REF_CLK1_P: AD6," &
"SD2_REF_CLK2_N: AJ11," &
"SD2_REF_CLK2_P: AK11," &
"SD2_RX0_N: AA4," &
"SD2_RX0_P: AA3," &
"SD2_RX1_N: AC4," &
"SD2_RX1_P: AC3," &
"SD2_RX2_N: AD2," &
"SD2_RX2_P: AD1," &
"SD2_RX3_N: AJ3," &
"SD2_RX3_P: AK3," &
"SD2_RX4_N: AK5," &
"SD2_RX4_P: AJ5," &
"SD2_RX5_N: AJ6," &
"SD2_RX5_P: AK6," &
"SD2_RX6_N: AK8," &
"SD2_RX6_P: AJ8," &
"SD2_RX7_N: AJ9," &
"SD2_RX7_P: AK9," &
"SD2_TX0_N: AB1," &
"SD2_TX0_P: AB2," &
"SD2_TX1_N: AB6," &
"SD2_TX1_P: AB5," &
"SD2_TX2_N: AF2," &
"SD2_TX2_P: AF1," &
"SD2_TX3_N: AH2," &
"SD2_TX3_P: AH1," &
"SD2_TX4_N: AG5," &
"SD2_TX4_P: AF5," &
"SD2_TX5_N: AF6," &
"SD2_TX5_P: AG6," &
"SD2_TX6_N: AG8," &
"SD2_TX6_P: AF8," &
"SD2_TX7_N: AF9," &
"SD2_TX7_P: AG9," &
"SDHC_CD_B: E4," &
"SDHC_CLK: C4," &
"SDHC_CMD: A3," &
"SDHC_DAT0: D2," &
"SDHC_DAT1: D3," &
"SDHC_DAT2: H6," &
"SDHC_DAT3: G5," &
"SDHC_WP: F4," &
"SPI_CLK: B2," &
"SPI_CS0_B: E3," &
"SPI_CS1_B: K6," &
"SPI_CS2_B: H5," &
"SPI_CS3_B: L6," &
"SPI_MISO: C2," &
"SPI_MOSI: C1," &
"SYSCLK: A10," &
"TCK: C20," &
"TDI: D22," &
"TDO: E20," &
"TEST_SEL_B: C9," &
"TMP_DETECT_B: C21," &
"TMS: A21," &
"TRST_B: B22," &
"TSEC_1588_ALARM_OUT1: U1," &
"TSEC_1588_ALARM_OUT2: W5," &
"TSEC_1588_CLK_IN: T3," &
"TSEC_1588_CLK_OUT: V3," &
"TSEC_1588_PULSE_OUT1: W2," &
"TSEC_1588_PULSE_OUT2: W1," &
"TSEC_1588_TRIG_IN1: V4," &
"TSEC_1588_TRIG_IN2: V2," &
"UART1_CTS_B: L4," &
"UART1_RTS_B: G1," &
"UART1_SIN: J3," &
"UART1_SOUT: J1," &
"UART2_CTS_B: F1," &
"UART2_RTS_B: J4," &
"UART2_SIN: F2," &
"UART2_SOUT: K3," &
"USB1_DRVVBUS: A8," &
"USB1_PWRFAULT: B9," &
"USB1_UDM: C7," &
"USB1_UDP: B8," &
"USB1_UID: E5," &
"USB1_VBUSCLMP: E7," &
"USB2_DRVVBUS: B5," &
"USB2_PWRFAULT: A5," &
"USB2_UDM: B6," &
"USB2_UDP: A6," &
"USB2_UID: D7," &
"USB2_VBUSCLMP: C6," &
"USBCLK: B11," &
"AGND_SD1_PLL1: AB16," &
"AGND_SD1_PLL2: AB19," &
"AGND_SD2_PLL1: AB10," &
"AGND_SD2_PLL2: AB13," &
"AVDD_CGA1: H9," &
"AVDD_CGA2: G9," &
"AVDD_D1: F22," &
"AVDD_PLAT: J10," &
"AVDD_SD1_PLL1: AB17," &
"AVDD_SD1_PLL2: AB20," &
"AVDD_SD2_PLL1: AB11," &
"AVDD_SD2_PLL2: AB14," &
"CVDD: (M6, M8)," &
"D1_MDIC0: K30," &
"D1_MDIC1: N29," &
"D1_MVREF: F21," &
"D1_TPA: C23," &
"DVDD: (N8, P8)," &
"FA_ANALOG_G_V: H21," &
"FA_ANALOG_PIN: G20," &
"FA_VL: H20," &
"G1VDD: (A29, B30, D29, F29, H29, K29," &
"L22, M22, M29, N22, P22, P29," &
"R22, T22, T29, T30, U22, V22," &
"V29, Y29, AB29, AD29, AF29, AJ30," &
"AK29)," &
"GND: (A2, A4, A23, A27, B1, B4," &
"B10, B13, B16, B19, B23, B26," &
"C3, C22, C24, C28, D4, D9," &
"D23, D26, E2, E12, E15, E18," &
"E21, E22, E24, E28, F9, F20," &
"F23, F26, G4, G8, G10, G21," &
"G22, G24, G28, H2, H10, H13," &
"H15, H17, H22, H26, J9, J11," &
"J12, J14, J16, J18, J22, J24," &
"J28, K4, K7, K9, K11, K23," &
"K26, L2, L7, L10, L12, L14," &
"L16, L18, L20, L24, L28, M5," &
"M7, M9, M11, M13, M15, M17," &
"M19, M21, M23, M26, N4, N7," &
"N10, N12, N14, N16, N18, N20," &
"N24, N28, P2, P7, P9, P11," &
"P13, P15, P17, P19, P21, P23," &
"P26, R6, R10, R12, R14, R16," &
"R18, R20, R24, R28, T4, T7," &
"T9, T11, T13, T15, T17, T19," &
"T21, T23, T26, U2, U7, U10," &
"U12, U14, U16, U18, U20, U24," &
"U28, V7, V9, V11, V13, V15," &
"V17, V19, V21, V23, V26, W3," &
"W4, W7, W8, W10, W12, W14," &
"W16, W18, W20, W22, W24, W28," &
"Y1, Y2, Y5, Y6, Y7, Y8," &
"Y9, Y22, Y26, AA22, AA24, AA28," &
"AB26, AC24, AC28, AD25, AD26, AE25," &
"AE28, AF26, AG26, AG28, AH28, AK27)," &
"LVDD: (T8, U8, V8)," &
"NC: (AB15, AC15, AD9, AD12, AD13, AD14," &
"AE12, AE13, AF13)," &
"OVDD: (K8, K12, K13, K14, K15, K16," &
"K17, K18, K19, K20, L8)," &
"PROG_MTR: E8," &
"PROG_SFP: E9," &
"S1GND: (AA17, AA18, AA19, AA20, AA21, AB18," &
"AC16, AC17, AC18, AC19, AC20, AH14," &
"AH15, AH16, AH19, AH22, AH25, AJ12," &
"AJ14, AJ16, AJ18, AJ19, AJ21, AJ22," &
"AJ24, AJ26, AK12, AK14, AK16, AK18," &
"AK19, AK21, AK22, AK24, AK26)," &
"S1VDD: (Y16, Y17, Y18, Y19, Y20, Y21)," &
"S2GND: (AA10, AA11, AA12, AA13, AA14, AA16," &
"AB3, AB4, AB7, AB8, AB9, AB12," &
"AC1, AC2, AC5, AC6, AC9, AC10," &
"AC11, AC12, AC13, AC14, AD3, AD4," &
"AD7, AD8, AD15, AE1, AE2, AE5," &
"AE6, AH3, AH5, AH6, AH8, AH9," &
"AH11, AJ4, AJ7, AJ10, AK2, AK4," &
"AK7, AK10)," &
"S2VDD: (Y11, Y12, Y13, Y14, Y15, AA9)," &
"SD1_IMP_CAL_RX: AA15," &
"SD1_IMP_CAL_TX: AC22," &
"SD1_PLL1_TPA: AE15," &
"SD1_PLL2_TPA: AF25," &
"SD2_IMP_CAL_RX: AA8," &
"SD2_IMP_CAL_TX: AE10," &
"SD2_PLL1_TPA: AC7," &
"SD2_PLL2_TPA: AG11," &
"SENSEGND: K21," &
"SENSEVDD: J20," &
"TD1_ANODE: K22," &
"TD1_CATHODE: J21," &
"TH_TPA: F8," &
"TH_VDD: K10," &
"USB_AGND: (A9, B7, C5, D5, D6, D8," &
"E6, G6, H7, H8)," &
"USB_HVDD: (A7, C8)," &
"USB_IBIAS_REXT: F7," &
"USB_OVDD: (J7, J8)," &
"USB_SVDD: (F6, G7)," &
"VDD: (L9, L11, L13, L15, L17, L19," &
"L21, M10, M12, M14, M16, M18," &
"M20, N9, N11, N13, N15, N17," &
"N19, N21, P10, P12, P14, P16," &
"P18, P20, R9, R11, R13, R15," &
"R17, R19, R21, T10, T12, T14," &
"T16, T18, T20, U9, U11, U13," &
"U15, U17, U19, U21, V10, V12," &
"V14, V16, V18, V20, W9, W11," &
"W13, W15, W17, W19, W21, Y10)," &
"VDD_LP: R8," &
"X1GND: (AB21, AC21, AC23, AD17, AD22, AE17," &
"AE19, AE20, AE22, AE24, AF14, AF15," &
"AF17, AF19, AF20, AF22, AF24, AG13," &
"AG16, AG18, AG21, AG23)," &
"X1VDD: (AB22, AD16, AG17, AG19, AG20, AG22," &
"AG24)," &
"X2GND: (Y3, Y4, AA1, AA2, AA5, AA6," &
"AA7, AD10, AD11, AE4, AE7, AE8," &
"AE9, AF3, AF4, AF7, AF10, AF12," &
"AG1, AG2, AG4, AG7, AG10, AG12," &
"AJ1, AJ2)," &
"X2VDD: (AE3, AE11, AG3, AH4, AH7, AH10)" ;
attribute PORT_GROUPING of T2080: entity is
"DIFFERENTIAL_VOLTAGE (" &
"(D1_MCK0, D1_MCK0_B)," &
"(D1_MCK1, D1_MCK1_B)," &
"(D1_MCK2, D1_MCK2_B)," &
"(D1_MCK3, D1_MCK3_B)," &
"(D1_MDQS0, D1_MDQS0_B)," &
"(D1_MDQS1, D1_MDQS1_B)," &
"(D1_MDQS2, D1_MDQS2_B)," &
"(D1_MDQS3, D1_MDQS3_B)," &
"(D1_MDQS4, D1_MDQS4_B)," &
"(D1_MDQS5, D1_MDQS5_B)," &
"(D1_MDQS6, D1_MDQS6_B)," &
"(D1_MDQS7, D1_MDQS7_B)," &
"(D1_MDQS8, D1_MDQS8_B)," &
"(SD1_REF_CLK1_P, SD1_REF_CLK1_N)," &
"(SD1_REF_CLK2_P, SD1_REF_CLK2_N)," &
"(SD1_RX0_P, SD1_RX0_N)," &
"(SD1_RX1_P, SD1_RX1_N)," &
"(SD1_RX2_P, SD1_RX2_N)," &
"(SD1_RX3_P, SD1_RX3_N)," &
"(SD1_RX4_P, SD1_RX4_N)," &
"(SD1_RX5_P, SD1_RX5_N)," &
"(SD1_RX6_P, SD1_RX6_N)," &
"(SD1_RX7_P, SD1_RX7_N)," &
"(SD1_TX0_P, SD1_TX0_N)," &
"(SD1_TX1_P, SD1_TX1_N)," &
"(SD1_TX2_P, SD1_TX2_N)," &
"(SD1_TX3_P, SD1_TX3_N)," &
"(SD1_TX4_P, SD1_TX4_N)," &
"(SD1_TX5_P, SD1_TX5_N)," &
"(SD1_TX6_P, SD1_TX6_N)," &
"(SD1_TX7_P, SD1_TX7_N)," &
"(SD2_REF_CLK1_P, SD2_REF_CLK1_N)," &
"(SD2_REF_CLK2_P, SD2_REF_CLK2_N)," &
"(SD2_RX0_P, SD2_RX0_N)," &
"(SD2_RX1_P, SD2_RX1_N)," &
"(SD2_RX2_P, SD2_RX2_N)," &
"(SD2_RX3_P, SD2_RX3_N)," &
"(SD2_RX4_P, SD2_RX4_N)," &
"(SD2_RX5_P, SD2_RX5_N)," &
"(SD2_RX6_P, SD2_RX6_N)," &
"(SD2_RX7_P, SD2_RX7_N)," &
"(SD2_TX0_P, SD2_TX0_N)," &
"(SD2_TX1_P, SD2_TX1_N)," &
"(SD2_TX2_P, SD2_TX2_N)," &
"(SD2_TX3_P, SD2_TX3_N)," &
"(SD2_TX4_P, SD2_TX4_N)," &
"(SD2_TX5_P, SD2_TX5_N)," &
"(SD2_TX6_P, SD2_TX6_N)," &
"(SD2_TX7_P, SD2_TX7_N)," &
"(USB1_UDP, USB1_UDM)," &
"(USB2_UDP, USB2_UDM))" ;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.00e+07,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute COMPLIANCE_PATTERNS of T2080: entity is
"(SCAN_MODE_B, TEST_SEL_B) (11)";
attribute INSTRUCTION_LENGTH of T2080: entity is 8;
attribute INSTRUCTION_OPCODE of T2080: entity is
"BYPASS (11111111)," &
"CLAMP (11110001)," &
"EXTEST (11111000)," &
"EXTEST_PULSE (11110101)," &
"EXTEST_TRAIN (11110110)," &
"HIGHZ (11110010)," &
"IDCODE (11110011)," &
"IOCONFIG (11110100)," &
"PRELOAD (11110000)," &
"SAMPLE (11110111)," &
"PRIVATE000 (00000011)," &
"PRIVATE001 (00000100)," &
"PRIVATE002 (00000101)," &
"PRIVATE003 (00000110)," &
"PRIVATE004 (00000111)," &
"PRIVATE005 (00001001)," &
"PRIVATE006 (00001010)," &
"PRIVATE007 (00100000)," &
"PRIVATE008 (00100001)," &
"PRIVATE009 (00100010)," &
"PRIVATE010 (00100011)," &
"PRIVATE011 (00100100)," &
"PRIVATE012 (00100101)," &
"PRIVATE013 (00100110)," &
"PRIVATE014 (00100111)," &
"PRIVATE015 (00101110)," &
"PRIVATE016 (00110000)," &
"PRIVATE017 (00110101)," &
"PRIVATE018 (00110110)," &
"PRIVATE019 (00111000)," &
"PRIVATE020 (01000100)," &
"PRIVATE021 (01010000)," &
"PRIVATE022 (01010001)," &
"PRIVATE023 (01010010)," &
"PRIVATE024 (01010100)," &
"PRIVATE025 (01010101)," &
"PRIVATE026 (01010110)," &
"PRIVATE027 (01100000)," &
"PRIVATE028 (01100001)," &
"PRIVATE029 (01100010)," &
"PRIVATE030 (01100011)," &
"PRIVATE031 (01100100)," &
"PRIVATE032 (01100101)," &
"PRIVATE033 (01100110)," &
"PRIVATE034 (01100111)," &
"PRIVATE035 (01101000)," &
"PRIVATE036 (01101001)," &
"PRIVATE037 (01101010)," &
"PRIVATE038 (01101100)," &
"PRIVATE039 (01101101)," &
"PRIVATE040 (01101110)," &
"PRIVATE041 (01101111)," &
"PRIVATE042 (01110001)," &
"PRIVATE043 (01110010)," &
"PRIVATE044 (01110100)," &
"PRIVATE045 (01110110)," &
"PRIVATE046 (01110111)," &
"PRIVATE047 (01111000)," &
"PRIVATE048 (01111001)," &
"PRIVATE049 (01111010)," &
"PRIVATE050 (01111100)," &
"PRIVATE051 (01111110)," &
"PRIVATE052 (01111111)," &
"PRIVATE053 (10000000)," &
"PRIVATE054 (10000001)," &
"PRIVATE055 (10000100)," &
"PRIVATE056 (10000101)," &
"PRIVATE057 (10000110)," &
"PRIVATE058 (10001000)," &
"PRIVATE059 (10001001)," &
"PRIVATE060 (10001010)," &
"PRIVATE061 (10001011)," &
"PRIVATE062 (10010000)," &
"PRIVATE063 (10010001)," &
"PRIVATE064 (10010010)," &
"PRIVATE065 (10010011)," &
"PRIVATE066 (10010100)," &
"PRIVATE067 (10010101)," &
"PRIVATE068 (10100000)," &
"PRIVATE069 (11100000)," &
"PRIVATE070 (11101000)," &
"PRIVATE071 (11111110)";
attribute INSTRUCTION_CAPTURE of T2080: entity is "xxxxxx01";
attribute INSTRUCTION_PRIVATE of T2080: entity is
"PRIVATE000," &
"PRIVATE001," &
"PRIVATE002," &
"PRIVATE003," &
"PRIVATE004," &
"PRIVATE005," &
"PRIVATE006," &
"PRIVATE007," &
"PRIVATE008," &
"PRIVATE009," &
"PRIVATE010," &
"PRIVATE011," &
"PRIVATE012," &
"PRIVATE013," &
"PRIVATE014," &
"PRIVATE015," &
"PRIVATE016," &
"PRIVATE017," &
"PRIVATE018," &
"PRIVATE019," &
"PRIVATE020," &
"PRIVATE021," &
"PRIVATE022," &
"PRIVATE023," &
"PRIVATE024," &
"PRIVATE025," &
"PRIVATE026," &
"PRIVATE027," &
"PRIVATE028," &
"PRIVATE029," &
"PRIVATE030," &
"PRIVATE031," &
"PRIVATE032," &
"PRIVATE033," &
"PRIVATE034," &
"PRIVATE035," &
"PRIVATE036," &
"PRIVATE037," &
"PRIVATE038," &
"PRIVATE039," &
"PRIVATE040," &
"PRIVATE041," &
"PRIVATE042," &
"PRIVATE043," &
"PRIVATE044," &
"PRIVATE045," &
"PRIVATE046," &
"PRIVATE047," &
"PRIVATE048," &
"PRIVATE049," &
"PRIVATE050," &
"PRIVATE051," &
"PRIVATE052," &
"PRIVATE053," &
"PRIVATE054," &
"PRIVATE055," &
"PRIVATE056," &
"PRIVATE057," &
"PRIVATE058," &
"PRIVATE059," &
"PRIVATE060," &
"PRIVATE061," &
"PRIVATE062," &
"PRIVATE063," &
"PRIVATE064," &
"PRIVATE065," &
"PRIVATE066," &
"PRIVATE067," &
"PRIVATE068," &
"PRIVATE069," &
"PRIVATE070," &
"PRIVATE071";
attribute IDCODE_REGISTER of T2080: entity is
"0001" & -- Version
"0001100011100111" & -- Part Number
"00000001110" & -- Manufacturer Identity
"1"; -- IEEE 1149.1 Requirement
attribute REGISTER_ACCESS of T2080: entity is
"BOUNDARY (EXTEST, EXTEST_PULSE, EXTEST_TRAIN, SAMPLE, PRELOAD)," &
"BYPASS (BYPASS, CLAMP, HIGHZ)," &
"DEVICE_ID (IDCODE)," &
"TDR[120] (IOCONFIG)";
attribute BOUNDARY_LENGTH of T2080: entity is 721;
attribute BOUNDARY_REGISTER of T2080: entity is
-- BSR DESCRIPTION TERMS
-- cell type = BC_0 - BC_99
-- port = port name
-- function
-- input = input only
-- bidir = bidirectional
-- output2 = two state ouput
-- output3 = three state ouput
-- control = control cell
-- controlr = control cell
-- internal = placeholder cell
-- safe = value that turns off drivers in control cells
-- ccell = controlling cell number for I/O direction
-- dsval = disabling (input) value
-- rslt = result if disabled (input = Z)
--
-- num cell port/* function safe [ccell dis rslt]
" 0 (BC_8, IRQ02, bidir, X, 1, 0, Z) ," &
" 1 (BC_2, *, control, 0) ," &
" 2 (BC_8, CLK_OUT, bidir, X, 3, 0, Z) ," &
" 3 (BC_2, *, control, 0) ," &
" 4 (BC_8, HRESET_B, bidir, X, 5, 0, Z) ," &
" 5 (BC_2, *, control, 0) ," &
" 6 (BC_8, IRQ03, bidir, X, 7, 0, Z) ," &
" 7 (BC_2, *, control, 0) ," &
" 8 (BC_8, IRQ01, bidir, X, 9, 0, Z) ," &
" 9 (BC_2, *, control, 0) ," &
" 10 (BC_8, IRQ04, bidir, X, 11, 0, Z) ," &
" 11 (BC_2, *, control, 0) ," &
" 12 (BC_8, USBCLK, bidir, X, 13, 0, Z) ," &
" 13 (BC_2, *, control, 0) ," &
" 14 (BC_8, IRQ05, bidir, X, 15, 0, Z) ," &
" 15 (BC_2, *, control, 0) ," &
" 16 (BC_8, EVT2_B, bidir, X, 17, 0, Z) ," &
" 17 (BC_2, *, control, 0) ," &
" 18 (BC_8, EVT3_B, bidir, X, 19, 0, Z) ," &
" 19 (BC_2, *, control, 0) ," &
" 20 (BC_8, EVT4_B, bidir, X, 21, 0, Z) ," &
" 21 (BC_2, *, control, 0) ," &
" 22 (BC_8, ASLEEP, bidir, X, 23, 0, Z) ," &
" 23 (BC_2, *, control, 0) ," &
" 24 (BC_8, RESET_REQ_B, bidir, X, 25, 0, Z) ," &
" 25 (BC_2, *, control, 0) ," &
" 26 (BC_8, IRQ_OUT_B, bidir, X, 27, 0, Z) ," &
" 27 (BC_2, *, control, 0) ," &
" 28 (BC_8, EVT1_B, bidir, X, 29, 0, Z) ," &
" 29 (BC_2, *, control, 0) ," &
" 30 (BC_8, EVT0_B, bidir, X, 31, 0, Z) ," &
" 31 (BC_2, *, control, 0) ," &
" 32 (BC_8, IFC_AD07, bidir, X, 33, 0, Z) ," &
" 33 (BC_2, *, control, 0) ," &
" 34 (BC_8, IFC_AD01, bidir, X, 35, 0, Z) ," &
" 35 (BC_2, *, control, 0) ," &
" 36 (BC_8, IFC_AD05, bidir, X, 37, 0, Z) ," &
" 37 (BC_2, *, control, 0) ," &
" 38 (BC_8, IFC_AD08, bidir, X, 39, 0, Z) ," &
" 39 (BC_2, *, control, 0) ," &
" 40 (BC_8, IFC_AD03, bidir, X, 41, 0, Z) ," &
" 41 (BC_2, *, control, 0) ," &
" 42 (BC_8, IFC_AD12, bidir, X, 43, 0, Z) ," &
" 43 (BC_2, *, control, 0) ," &
" 44 (BC_8, IFC_AD00, bidir, X, 45, 0, Z) ," &
" 45 (BC_2, *, control, 0) ," &
" 46 (BC_8, IFC_AD11, bidir, X, 47, 0, Z) ," &
" 47 (BC_2, *, control, 0) ," &
" 48 (BC_8, IFC_A21, bidir, X, 49, 0, Z) ," &
" 49 (BC_2, *, control, 0) ," &
" 50 (BC_8, IFC_AD02, bidir, X, 51, 0, Z) ," &
" 51 (BC_2, *, control, 0) ," &
" 52 (BC_8, IFC_AD15, bidir, X, 53, 0, Z) ," &
" 53 (BC_2, *, control, 0) ," &
" 54 (BC_8, IFC_AD06, bidir, X, 55, 0, Z) ," &
" 55 (BC_2, *, control, 0) ," &
" 56 (BC_8, IFC_AD09, bidir, X, 57, 0, Z) ," &
" 57 (BC_2, *, control, 0) ," &
" 58 (BC_8, IFC_A19, bidir, X, 59, 0, Z) ," &
" 59 (BC_2, *, control, 0) ," &
" 60 (BC_8, IFC_AD10, bidir, X, 61, 0, Z) ," &
" 61 (BC_2, *, control, 0) ," &
" 62 (BC_8, IFC_AD04, bidir, X, 63, 0, Z) ," &
" 63 (BC_2, *, control, 0) ," &
" 64 (BC_8, IFC_AD13, bidir, X, 65, 0, Z) ," &
" 65 (BC_2, *, control, 0) ," &
" 66 (BC_8, IFC_A17, bidir, X, 67, 0, Z) ," &
" 67 (BC_2, *, control, 0) ," &
" 68 (BC_8, IFC_A18, bidir, X, 69, 0, Z) ," &
" 69 (BC_2, *, control, 0) ," &
" 70 (BC_8, IFC_A20, bidir, X, 71, 0, Z) ," &
" 71 (BC_2, *, control, 0) ," &
" 72 (BC_8, IFC_AD14, bidir, X, 73, 0, Z) ," &
" 73 (BC_2, *, control, 0) ," &
" 74 (BC_8, IFC_A16, bidir, X, 75, 0, Z) ," &
" 75 (BC_2, *, control, 0) ," &
" 76 (BC_8, IFC_A24, bidir, X, 77, 0, Z) ," &
" 77 (BC_2, *, control, 0) ," &
" 78 (BC_8, IFC_A22, bidir, X, 79, 0, Z) ," &
" 79 (BC_2, *, control, 0) ," &
" 80 (BC_8, IFC_A26, bidir, X, 81, 0, Z) ," &
" 81 (BC_2, *, control, 0) ," &
" 82 (BC_8, IFC_A31, bidir, X, 83, 0, Z) ," &
" 83 (BC_2, *, control, 0) ," &
" 84 (BC_8, IFC_A28, bidir, X, 85, 0, Z) ," &
" 85 (BC_2, *, control, 0) ," &
" 86 (BC_8, IFC_PAR1, bidir, X, 87, 0, Z) ," &
" 87 (BC_2, *, control, 0) ," &
" 88 (BC_8, IFC_A29, bidir, X, 89, 0, Z) ," &
" 89 (BC_2, *, control, 0) ," &
" 90 (BC_8, IFC_CS0_B, bidir, X, 91, 0, Z) ," &
" 91 (BC_2, *, control, 0) ," &
" 92 (BC_8, IFC_CS3_B, bidir, X, 93, 0, Z) ," &
" 93 (BC_2, *, control, 0) ," &
" 94 (BC_8, IFC_AVD, bidir, X, 95, 0, Z) ," &
" 95 (BC_2, *, control, 0) ," &
" 96 (BC_8, IFC_WE0_B, bidir, X, 97, 0, Z) ," &
" 97 (BC_2, *, control, 0) ," &
" 98 (BC_8, IFC_A25, bidir, X, 99, 0, Z) ," &
" 99 (BC_2, *, control, 0) ," &
" 100 (BC_8, IFC_CS1_B, bidir, X, 101, 0, Z) ," &
" 101 (BC_2, *, control, 0) ," &
" 102 (BC_8, IFC_NDDDR_CLK, bidir, X, 103, 0, Z) ," &
" 103 (BC_2, *, control, 0) ," &
" 104 (BC_8, IFC_A27, bidir, X, 105, 0, Z) ," &
" 105 (BC_2, *, control, 0) ," &
" 106 (BC_8, IFC_RB0_B, bidir, X, 107, 0, Z) ," &
" 107 (BC_2, *, control, 0) ," &
" 108 (BC_8, IFC_WP0_B, bidir, X, 109, 0, Z) ," &
" 109 (BC_2, *, control, 0) ," &
" 110 (BC_8, IFC_A23, bidir, X, 111, 0, Z) ," &
" 111 (BC_2, *, control, 0) ," &
" 112 (BC_8, IFC_CS5_B, bidir, X, 113, 0, Z) ," &
" 113 (BC_2, *, control, 0) ," &
" 114 (BC_8, IFC_PAR0, bidir, X, 115, 0, Z) ," &
" 115 (BC_2, *, control, 0) ," &
" 116 (BC_8, IFC_OE_B, bidir, X, 117, 0, Z) ," &
" 117 (BC_2, *, control, 0) ," &
" 118 (BC_8, IFC_BCTL, bidir, X, 119, 0, Z) ," &
" 119 (BC_2, *, control, 0) ," &
" 120 (BC_8, IFC_TE, bidir, X, 121, 0, Z) ," &
" 121 (BC_2, *, control, 0) ," &
" 122 (BC_8, IFC_RB1_B, bidir, X, 123, 0, Z) ," &
" 123 (BC_2, *, control, 0) ," &
" 124 (BC_8, IFC_CS2_B, bidir, X, 125, 0, Z) ," &
" 125 (BC_2, *, control, 0) ," &
" 126 (BC_8, IFC_CS4_B, bidir, X, 127, 0, Z) ," &
" 127 (BC_2, *, control, 0) ," &
" 128 (BC_8, IFC_PERR_B, bidir, X, 129, 0, Z) ," &
" 129 (BC_2, *, control, 0) ," &
" 130 (BC_8, IFC_CS7_B, bidir, X, 131, 0, Z) ," &
" 131 (BC_2, *, control, 0) ," &
" 132 (BC_8, IFC_CLE, bidir, X, 133, 0, Z) ," &
" 133 (BC_2, *, control, 0) ," &
" 134 (BC_8, IFC_NDDQS, bidir, X, 135, 0, Z) ," &
" 135 (BC_2, *, control, 0) ," &
" 136 (BC_8, RTC, bidir, X, 137, 0, Z) ," &
" 137 (BC_2, *, control, 0) ," &
" 138 (BC_8, IFC_CLK1, bidir, X, 139, 0, Z) ," &
" 139 (BC_2, *, control, 0) ," &
" 140 (BC_8, CKSTP_OUT_B, bidir, X, 141, 0, Z) ," &
" 141 (BC_2, *, control, 0) ," &
" 142 (BC_8, TMP_DETECT_B, bidir, X, 143, 0, Z) ," &
" 143 (BC_2, *, control, 0) ," &
" 144 (BC_8, IFC_CS6_B, bidir, X, 145, 0, Z) ," &
" 145 (BC_2, *, control, 0) ," &
" 146 (BC_8, IFC_CLK0, bidir, X, 147, 0, Z) ," &
" 147 (BC_2, *, control, 0) ," &
" 148 (BC_8, IFC_A30, bidir, X, 149, 0, Z) ," &
" 149 (BC_2, *, control, 0) ," &
" 150 (BC_2, D1_MCKE1, output3, X, 151, 0, Z) ," &
" 151 (BC_2, *, control, 0) ," &
" 152 (BC_2, D1_MCKE2, output3, X, 153, 0, Z) ," &
" 153 (BC_2, *, control, 0) ," &
" 154 (BC_2, D1_MCKE3, output3, X, 155, 0, Z) ," &
" 155 (BC_2, *, control, 0) ," &
" 156 (BC_2, D1_MCKE0, output3, X, 157, 0, Z) ," &
" 157 (BC_2, *, control, 0) ," &
" 158 (BC_2, D1_MA15, output3, X, 159, 0, Z) ," &
" 159 (BC_2, *, control, 0) ," &
" 160 (BC_2, D1_MBA2, output3, X, 161, 0, Z) ," &
" 161 (BC_2, *, control, 0) ," &
" 162 (BC_2, D1_MA14, output3, X, 163, 0, Z) ," &
" 163 (BC_2, *, control, 0) ," &
" 164 (BC_7, D1_MDQ00, bidir, X, 165, 0, Z) ," &
" 165 (BC_2, *, control, 0) ," &
" 166 (BC_7, D1_MDQ01, bidir, X, 167, 0, Z) ," &
" 167 (BC_2, *, control, 0) ," &
" 168 (BC_2, *, internal, X) ," &
" 169 (BC_7, D1_MDQS0, bidir, X, 170, 0, Z) ," &
" 170 (BC_2, *, control, 0) ," &
" 171 (BC_7, D1_MDQ02, bidir, X, 172, 0, Z) ," &
" 172 (BC_2, *, control, 0) ," &
" 173 (BC_7, D1_MDQ03, bidir, X, 174, 0, Z) ," &
" 174 (BC_2, *, control, 0) ," &
" 175 (BC_7, D1_MDQ04, bidir, X, 176, 0, Z) ," &
" 176 (BC_2, *, control, 0) ," &
" 177 (BC_7, D1_MDQ05, bidir, X, 178, 0, Z) ," &
" 178 (BC_2, *, control, 0) ," &
" 179 (BC_2, *, internal, X) ," &
" 180 (BC_0, D1_MDM0, output3, X, 181, 0, Z) ," &
" 181 (BC_2, *, control, 0) ," &
" 182 (BC_7, D1_MDQ06, bidir, X, 183, 0, Z) ," &
" 183 (BC_2, *, control, 0) ," &
" 184 (BC_7, D1_MDQ07, bidir, X, 185, 0, Z) ," &
" 185 (BC_2, *, control, 0) ," &
" 186 (BC_7, D1_MDQ08, bidir, X, 187, 0, Z) ," &
" 187 (BC_2, *, control, 0) ," &
" 188 (BC_7, D1_MDQ09, bidir, X, 189, 0, Z) ," &
" 189 (BC_2, *, control, 0) ," &
" 190 (BC_2, *, internal, X) ," &
" 191 (BC_7, D1_MDQS1, bidir, X, 192, 0, Z) ," &
" 192 (BC_2, *, control, 0) ," &
" 193 (BC_7, D1_MDQ10, bidir, X, 194, 0, Z) ," &
" 194 (BC_2, *, control, 0) ," &
" 195 (BC_7, D1_MDQ11, bidir, X, 196, 0, Z) ," &
" 196 (BC_2, *, control, 0) ," &
" 197 (BC_7, D1_MDQ12, bidir, X, 198, 0, Z) ," &
" 198 (BC_2, *, control, 0) ," &
" 199 (BC_7, D1_MDQ13, bidir, X, 200, 0, Z) ," &
" 200 (BC_2, *, control, 0) ," &
" 201 (BC_2, *, internal, X) ," &
" 202 (BC_0, D1_MDM1, output3, X, 203, 0, Z) ," &
" 203 (BC_2, *, control, 0) ," &
" 204 (BC_7, D1_MDQ14, bidir, X, 205, 0, Z) ," &
" 205 (BC_2, *, control, 0) ," &
" 206 (BC_7, D1_MDQ15, bidir, X, 207, 0, Z) ," &
" 207 (BC_2, *, control, 0) ," &
" 208 (BC_7, D1_MDQ16, bidir, X, 209, 0, Z) ," &
" 209 (BC_2, *, control, 0) ," &
" 210 (BC_7, D1_MDQ17, bidir, X, 211, 0, Z) ," &
" 211 (BC_2, *, control, 0) ," &
" 212 (BC_2, *, internal, X) ," &
" 213 (BC_7, D1_MDQS2, bidir, X, 214, 0, Z) ," &
" 214 (BC_2, *, control, 0) ," &
" 215 (BC_7, D1_MDQ18, bidir, X, 216, 0, Z) ," &
" 216 (BC_2, *, control, 0) ," &
" 217 (BC_7, D1_MDQ19, bidir, X, 218, 0, Z) ," &
" 218 (BC_2, *, control, 0) ," &
" 219 (BC_7, D1_MDQ20, bidir, X, 220, 0, Z) ," &
" 220 (BC_2, *, control, 0) ," &
" 221 (BC_7, D1_MDQ21, bidir, X, 222, 0, Z) ," &
" 222 (BC_2, *, control, 0) ," &
" 223 (BC_2, *, internal, X) ," &
" 224 (BC_0, D1_MDM2, output3, X, 225, 0, Z) ," &
" 225 (BC_2, *, control, 0) ," &
" 226 (BC_7, D1_MDQ22, bidir, X, 227, 0, Z) ," &
" 227 (BC_2, *, control, 0) ," &
" 228 (BC_7, D1_MDQ23, bidir, X, 229, 0, Z) ," &
" 229 (BC_2, *, control, 0) ," &
" 230 (BC_7, D1_MDQ24, bidir, X, 231, 0, Z) ," &
" 231 (BC_2, *, control, 0) ," &
" 232 (BC_7, D1_MDQ25, bidir, X, 233, 0, Z) ," &
" 233 (BC_2, *, control, 0) ," &
" 234 (BC_2, *, internal, X) ," &
" 235 (BC_7, D1_MDQS3, bidir, X, 236, 0, Z) ," &
" 236 (BC_2, *, control, 0) ," &
" 237 (BC_7, D1_MDQ26, bidir, X, 238, 0, Z) ," &
" 238 (BC_2, *, control, 0) ," &
" 239 (BC_7, D1_MDQ27, bidir, X, 240, 0, Z) ," &
" 240 (BC_2, *, control, 0) ," &
" 241 (BC_7, D1_MDQ28, bidir, X, 242, 0, Z) ," &
" 242 (BC_2, *, control, 0) ," &
" 243 (BC_7, D1_MDQ29, bidir, X, 244, 0, Z) ," &
" 244 (BC_2, *, control, 0) ," &
" 245 (BC_2, *, internal, X) ," &
" 246 (BC_0, D1_MDM3, output3, X, 247, 0, Z) ," &
" 247 (BC_2, *, control, 0) ," &
" 248 (BC_7, D1_MDQ30, bidir, X, 249, 0, Z) ," &
" 249 (BC_2, *, control, 0) ," &
" 250 (BC_7, D1_MDQ31, bidir, X, 251, 0, Z) ," &
" 251 (BC_2, *, control, 0) ," &
" 252 (BC_7, D1_MECC0, bidir, X, 253, 0, Z) ," &
" 253 (BC_2, *, control, 0) ," &
" 254 (BC_7, D1_MECC1, bidir, X, 255, 0, Z) ," &
" 255 (BC_2, *, control, 0) ," &
" 256 (BC_2, *, internal, X) ," &
" 257 (BC_7, D1_MDQS8, bidir, X, 258, 0, Z) ," &
" 258 (BC_2, *, control, 0) ," &
" 259 (BC_7, D1_MECC2, bidir, X, 260, 0, Z) ," &
" 260 (BC_2, *, control, 0) ," &
" 261 (BC_7, D1_MECC3, bidir, X, 262, 0, Z) ," &
" 262 (BC_2, *, control, 0) ," &
" 263 (BC_7, D1_MECC4, bidir, X, 264, 0, Z) ," &
" 264 (BC_2, *, control, 0) ," &
" 265 (BC_7, D1_MECC5, bidir, X, 266, 0, Z) ," &
" 266 (BC_2, *, control, 0) ," &
" 267 (BC_2, *, internal, X) ," &
" 268 (BC_0, D1_MDM8, output3, X, 269, 0, Z) ," &
" 269 (BC_2, *, control, 0) ," &
" 270 (BC_7, D1_MECC6, bidir, X, 271, 0, Z) ," &
" 271 (BC_2, *, control, 0) ," &
" 272 (BC_7, D1_MECC7, bidir, X, 273, 0, Z) ," &
" 273 (BC_2, *, control, 0) ," &
" 274 (BC_2, D1_MA12, output3, X, 275, 0, Z) ," &
" 275 (BC_2, *, control, 0) ," &
" 276 (BC_2, D1_MA11, output3, X, 277, 0, Z) ," &
" 277 (BC_2, *, control, 0) ," &
" 278 (BC_2, *, internal, X) ," &
" 279 (BC_2, D1_MCK0, output3, X, 280, 0, Z) ," &
" 280 (BC_2, *, control, 0) ," &
" 281 (BC_2, D1_MA09, output3, X, 282, 0, Z) ," &
" 282 (BC_2, *, control, 0) ," &
" 283 (BC_2, D1_MA07, output3, X, 284, 0, Z) ," &
" 284 (BC_2, *, control, 0) ," &
" 285 (BC_2, D1_MA08, output3, X, 286, 0, Z) ," &
" 286 (BC_2, *, control, 0) ," &
" 287 (BC_2, D1_MA05, output3, X, 288, 0, Z) ," &
" 288 (BC_2, *, control, 0) ," &
" 289 (BC_2, *, internal, X) ," &
" 290 (BC_2, D1_MCK1, output3, X, 291, 0, Z) ," &
" 291 (BC_2, *, control, 0) ," &
" 292 (BC_2, D1_MA06, output3, X, 293, 0, Z) ," &
" 293 (BC_2, *, control, 0) ," &
" 294 (BC_4, DDRCLK, clock, X) ," &
" 295 (BC_7, D1_MAPAR_ERR_B, bidir, X, 296, 0, Z) ," &
" 296 (BC_2, *, control, 0) ," &
" 297 (BC_2, D1_MA04, output3, X, 298, 0, Z) ," &
" 298 (BC_2, *, control, 0) ," &
" 299 (BC_2, D1_MA03, output3, X, 300, 0, Z) ," &
" 300 (BC_2, *, control, 0) ," &
" 301 (BC_2, *, internal, X) ," &
" 302 (BC_2, D1_MCK2, output3, X, 303, 0, Z) ," &
" 303 (BC_2, *, control, 0) ," &
" 304 (BC_2, D1_MA02, output3, X, 305, 0, Z) ," &
" 305 (BC_2, *, control, 0) ," &
" 306 (BC_2, D1_MA01, output3, X, 307, 0, Z) ," &
" 307 (BC_2, *, control, 0) ," &
" 308 (BC_2, D1_MA00, output3, X, 309, 0, Z) ," &
" 309 (BC_2, *, control, 0) ," &
" 310 (BC_2, D1_MAPAR_OUT, output3, X, 311, 0, Z) ," &
" 311 (BC_2, *, control, 0) ," &
" 312 (BC_2, D1_MA10, output3, X, 313, 0, Z) ," &
" 313 (BC_2, *, control, 0) ," &
" 314 (BC_2, D1_MBA1, output3, X, 315, 0, Z) ," &
" 315 (BC_2, *, control, 0) ," &
" 316 (BC_2, *, internal, X) ," &
" 317 (BC_2, D1_MCK3, output3, X, 318, 0, Z) ," &
" 318 (BC_2, *, control, 0) ," &
" 319 (BC_2, D1_MBA0, output3, X, 320, 0, Z) ," &
" 320 (BC_2, *, control, 0) ," &
" 321 (BC_7, D1_MDQ32, bidir, X, 322, 0, Z) ," &
" 322 (BC_2, *, control, 0) ," &
" 323 (BC_7, D1_MDQ33, bidir, X, 324, 0, Z) ," &
" 324 (BC_2, *, control, 0) ," &
" 325 (BC_2, *, internal, X) ," &
" 326 (BC_7, D1_MDQS4, bidir, X, 327, 0, Z) ," &
" 327 (BC_2, *, control, 0) ," &
" 328 (BC_7, D1_MDQ34, bidir, X, 329, 0, Z) ," &
" 329 (BC_2, *, control, 0) ," &
" 330 (BC_7, D1_MDQ35, bidir, X, 331, 0, Z) ," &
" 331 (BC_2, *, control, 0) ," &
" 332 (BC_7, D1_MDQ36, bidir, X, 333, 0, Z) ," &
" 333 (BC_2, *, control, 0) ," &
" 334 (BC_7, D1_MDQ37, bidir, X, 335, 0, Z) ," &
" 335 (BC_2, *, control, 0) ," &
" 336 (BC_2, *, internal, X) ," &
" 337 (BC_0, D1_MDM4, output3, X, 338, 0, Z) ," &
" 338 (BC_2, *, control, 0) ," &
" 339 (BC_7, D1_MDQ38, bidir, X, 340, 0, Z) ," &
" 340 (BC_2, *, control, 0) ," &
" 341 (BC_7, D1_MDQ39, bidir, X, 342, 0, Z) ," &
" 342 (BC_2, *, control, 0) ," &
" 343 (BC_7, D1_MDQ40, bidir, X, 344, 0, Z) ," &
" 344 (BC_2, *, control, 0) ," &
" 345 (BC_7, D1_MDQ41, bidir, X, 346, 0, Z) ," &
" 346 (BC_2, *, control, 0) ," &
" 347 (BC_2, *, internal, X) ," &
" 348 (BC_7, D1_MDQS5, bidir, X, 349, 0, Z) ," &
" 349 (BC_2, *, control, 0) ," &
" 350 (BC_7, D1_MDQ42, bidir, X, 351, 0, Z) ," &
" 351 (BC_2, *, control, 0) ," &
" 352 (BC_7, D1_MDQ43, bidir, X, 353, 0, Z) ," &
" 353 (BC_2, *, control, 0) ," &
" 354 (BC_7, D1_MDQ44, bidir, X, 355, 0, Z) ," &
" 355 (BC_2, *, control, 0) ," &
" 356 (BC_7, D1_MDQ45, bidir, X, 357, 0, Z) ," &
" 357 (BC_2, *, control, 0) ," &
" 358 (BC_2, *, internal, X) ," &
" 359 (BC_0, D1_MDM5, output3, X, 360, 0, Z) ," &
" 360 (BC_2, *, control, 0) ," &
" 361 (BC_7, D1_MDQ46, bidir, X, 362, 0, Z) ," &
" 362 (BC_2, *, control, 0) ," &
" 363 (BC_7, D1_MDQ47, bidir, X, 364, 0, Z) ," &
" 364 (BC_2, *, control, 0) ," &
" 365 (BC_7, D1_MDQ48, bidir, X, 366, 0, Z) ," &
" 366 (BC_2, *, control, 0) ," &
" 367 (BC_7, D1_MDQ49, bidir, X, 368, 0, Z) ," &
" 368 (BC_2, *, control, 0) ," &
" 369 (BC_2, *, internal, X) ," &
" 370 (BC_7, D1_MDQS6, bidir, X, 371, 0, Z) ," &
" 371 (BC_2, *, control, 0) ," &
" 372 (BC_7, D1_MDQ50, bidir, X, 373, 0, Z) ," &
" 373 (BC_2, *, control, 0) ," &
" 374 (BC_7, D1_MDQ51, bidir, X, 375, 0, Z) ," &
" 375 (BC_2, *, control, 0) ," &
" 376 (BC_7, D1_MDQ52, bidir, X, 377, 0, Z) ," &
" 377 (BC_2, *, control, 0) ," &
" 378 (BC_7, D1_MDQ53, bidir, X, 379, 0, Z) ," &
" 379 (BC_2, *, control, 0) ," &
" 380 (BC_2, *, internal, X) ," &
" 381 (BC_0, D1_MDM6, output3, X, 382, 0, Z) ," &
" 382 (BC_2, *, control, 0) ," &
" 383 (BC_7, D1_MDQ54, bidir, X, 384, 0, Z) ," &
" 384 (BC_2, *, control, 0) ," &
" 385 (BC_7, D1_MDQ55, bidir, X, 386, 0, Z) ," &
" 386 (BC_2, *, control, 0) ," &
" 387 (BC_7, D1_MDQ56, bidir, X, 388, 0, Z) ," &
" 388 (BC_2, *, control, 0) ," &
" 389 (BC_7, D1_MDQ57, bidir, X, 390, 0, Z) ," &
" 390 (BC_2, *, control, 0) ," &
" 391 (BC_2, *, internal, X) ," &
" 392 (BC_7, D1_MDQS7, bidir, X, 393, 0, Z) ," &
" 393 (BC_2, *, control, 0) ," &
" 394 (BC_7, D1_MDQ58, bidir, X, 395, 0, Z) ," &
" 395 (BC_2, *, control, 0) ," &
" 396 (BC_7, D1_MDQ59, bidir, X, 397, 0, Z) ," &
" 397 (BC_2, *, control, 0) ," &
" 398 (BC_7, D1_MDQ60, bidir, X, 399, 0, Z) ," &
" 399 (BC_2, *, control, 0) ," &
" 400 (BC_7, D1_MDQ61, bidir, X, 401, 0, Z) ," &
" 401 (BC_2, *, control, 0) ," &
" 402 (BC_2, *, internal, X) ," &
" 403 (BC_0, D1_MDM7, output3, X, 404, 0, Z) ," &
" 404 (BC_2, *, control, 0) ," &
" 405 (BC_7, D1_MDQ62, bidir, X, 406, 0, Z) ," &
" 406 (BC_2, *, control, 0) ," &
" 407 (BC_7, D1_MDQ63, bidir, X, 408, 0, Z) ," &
" 408 (BC_2, *, control, 0) ," &
" 409 (BC_2, D1_MCS0_B, output3, X, 410, 0, Z) ," &
" 410 (BC_2, *, control, 0) ," &
" 411 (BC_2, D1_MCS2_B, output3, X, 412, 0, Z) ," &
" 412 (BC_2, *, control, 0) ," &
" 413 (BC_2, D1_MWE_B, output3, X, 414, 0, Z) ," &
" 414 (BC_2, *, control, 0) ," &
" 415 (BC_2, D1_MRAS_B, output3, X, 416, 0, Z) ," &
" 416 (BC_2, *, control, 0) ," &
" 417 (BC_2, D1_MCAS_B, output3, X, 418, 0, Z) ," &
" 418 (BC_2, *, control, 0) ," &
" 419 (BC_2, D1_MODT0, output3, X, 420, 0, Z) ," &
" 420 (BC_2, *, control, 0) ," &
" 421 (BC_2, D1_MODT2, output3, X, 422, 0, Z) ," &
" 422 (BC_2, *, control, 0) ," &
" 423 (BC_2, D1_MA13, output3, X, 424, 0, Z) ," &
" 424 (BC_2, *, control, 0) ," &
" 425 (BC_2, D1_MCS3_B, output3, X, 426, 0, Z) ," &
" 426 (BC_2, *, control, 0) ," &
" 427 (BC_2, D1_MCS1_B, output3, X, 428, 0, Z) ," &
" 428 (BC_2, *, control, 0) ," &
" 429 (BC_2, D1_MODT1, output3, X, 430, 0, Z) ," &
" 430 (BC_2, *, control, 0) ," &
" 431 (BC_2, D1_MODT3, output3, X, 432, 0, Z) ," &
" 432 (BC_2, *, control, 0) ," &
" 433 (BC_4, SD1_RX0_P, observe_only, X) ," &
" 434 (BC_4, SD1_RX0_N, observe_only, X) ," &
" 435 (AC_SELU, *, internal, 0) ," &
" 436 (AC_2, SD1_TX0_P, output3, 0, 437, 1, Z) ," &
" 437 (BC_2, *, control, 1) ," &
" 438 (BC_2, *, control, 1) ," &
" 439 (AC_2, SD1_TX1_P, output3, 0, 438, 1, Z) ," &
" 440 (AC_SELU, *, internal, 0) ," &
" 441 (BC_4, SD1_RX1_N, observe_only, X) ," &
" 442 (BC_4, SD1_RX1_P, observe_only, X) ," &
" 443 (BC_2, *, control, 1) ," &
" 444 (BC_2, SD1_PLL1_TPD, output3, 0, 443, 1, Z) ," &
" 445 (BC_4, SD1_REF_CLK1_P, observe_only, X) ," &
" 446 (BC_4, SD1_REF_CLK1_N, observe_only, X) ," &
" 447 (BC_4, SD1_RX2_P, observe_only, X) ," &
" 448 (BC_4, SD1_RX2_N, observe_only, X) ," &
" 449 (AC_SELU, *, internal, 0) ," &
" 450 (AC_2, SD1_TX2_P, output3, 0, 451, 1, Z) ," &
" 451 (BC_2, *, control, 1) ," &
" 452 (BC_2, *, control, 1) ," &
" 453 (AC_2, SD1_TX3_P, output3, 0, 452, 1, Z) ," &
" 454 (AC_SELU, *, internal, 0) ," &
" 455 (BC_4, SD1_RX3_N, observe_only, X) ," &
" 456 (BC_4, SD1_RX3_P, observe_only, X) ," &
" 457 (BC_4, SD1_RX4_P, observe_only, X) ," &
" 458 (BC_4, SD1_RX4_N, observe_only, X) ," &
" 459 (AC_SELU, *, internal, 0) ," &
" 460 (AC_2, SD1_TX4_P, output3, 0, 461, 1, Z) ," &
" 461 (BC_2, *, control, 1) ," &
" 462 (BC_2, *, control, 1) ," &
" 463 (AC_2, SD1_TX5_P, output3, 0, 462, 1, Z) ," &
" 464 (AC_SELU, *, internal, 0) ," &
" 465 (BC_4, SD1_RX5_N, observe_only, X) ," &
" 466 (BC_4, SD1_RX5_P, observe_only, X) ," &
" 467 (BC_4, SD1_RX6_P, observe_only, X) ," &
" 468 (BC_4, SD1_RX6_N, observe_only, X) ," &
" 469 (AC_SELU, *, internal, 0) ," &
" 470 (AC_2, SD1_TX6_P, output3, 0, 471, 1, Z) ," &
" 471 (BC_2, *, control, 1) ," &
" 472 (BC_2, *, control, 1) ," &
" 473 (AC_2, SD1_TX7_P, output3, 0, 472, 1, Z) ," &
" 474 (AC_SELU, *, internal, 0) ," &
" 475 (BC_4, SD1_RX7_N, observe_only, X) ," &
" 476 (BC_4, SD1_RX7_P, observe_only, X) ," &
" 477 (BC_2, *, control, 1) ," &
" 478 (BC_2, SD1_PLL2_TPD, output3, 0, 477, 1, Z) ," &
" 479 (BC_4, SD1_REF_CLK2_P, observe_only, X) ," &
" 480 (BC_4, SD1_REF_CLK2_N, observe_only, X) ," &
" 481 (BC_4, SD2_RX0_P, observe_only, X) ," &
" 482 (BC_4, SD2_RX0_N, observe_only, X) ," &
" 483 (AC_SELU, *, internal, 0) ," &
" 484 (AC_2, SD2_TX0_P, output3, 0, 485, 1, Z) ," &
" 485 (BC_2, *, control, 1) ," &
" 486 (BC_2, *, control, 1) ," &
" 487 (AC_2, SD2_TX1_P, output3, 0, 486, 1, Z) ," &
" 488 (AC_SELU, *, internal, 0) ," &
" 489 (BC_4, SD2_RX1_N, observe_only, X) ," &
" 490 (BC_4, SD2_RX1_P, observe_only, X) ," &
" 491 (BC_2, *, control, 1) ," &
" 492 (BC_2, SD2_PLL1_TPD, output3, 0, 491, 1, Z) ," &
" 493 (BC_4, SD2_REF_CLK1_P, observe_only, X) ," &
" 494 (BC_4, SD2_REF_CLK1_N, observe_only, X) ," &
" 495 (BC_4, SD2_RX2_P, observe_only, X) ," &
" 496 (BC_4, SD2_RX2_N, observe_only, X) ," &
" 497 (AC_SELU, *, internal, 0) ," &
" 498 (AC_2, SD2_TX2_P, output3, 0, 499, 1, Z) ," &
" 499 (BC_2, *, control, 1) ," &
" 500 (BC_2, *, control, 1) ," &
" 501 (AC_2, SD2_TX3_P, output3, 0, 500, 1, Z) ," &
" 502 (AC_SELU, *, internal, 0) ," &
" 503 (BC_4, SD2_RX3_N, observe_only, X) ," &
" 504 (BC_4, SD2_RX3_P, observe_only, X) ," &
" 505 (BC_4, SD2_RX4_P, observe_only, X) ," &
" 506 (BC_4, SD2_RX4_N, observe_only, X) ," &
" 507 (AC_SELU, *, internal, 0) ," &
" 508 (AC_2, SD2_TX4_P, output3, 0, 509, 1, Z) ," &
" 509 (BC_2, *, control, 1) ," &
" 510 (BC_2, *, control, 1) ," &
" 511 (AC_2, SD2_TX5_P, output3, 0, 510, 1, Z) ," &
" 512 (AC_SELU, *, internal, 0) ," &
" 513 (BC_4, SD2_RX5_N, observe_only, X) ," &
" 514 (BC_4, SD2_RX5_P, observe_only, X) ," &
" 515 (BC_4, SD2_RX6_P, observe_only, X) ," &
" 516 (BC_4, SD2_RX6_N, observe_only, X) ," &
" 517 (AC_SELU, *, internal, 0) ," &
" 518 (AC_2, SD2_TX6_P, output3, 0, 519, 1, Z) ," &
" 519 (BC_2, *, control, 1) ," &
" 520 (BC_2, *, control, 1) ," &
" 521 (AC_2, SD2_TX7_P, output3, 0, 520, 1, Z) ," &
" 522 (AC_SELU, *, internal, 0) ," &
" 523 (BC_4, SD2_RX7_N, observe_only, X) ," &
" 524 (BC_4, SD2_RX7_P, observe_only, X) ," &
" 525 (BC_2, *, control, 1) ," &
" 526 (BC_2, SD2_PLL2_TPD, output3, 0, 525, 1, Z) ," &
" 527 (BC_4, SD2_REF_CLK2_P, observe_only, X) ," &
" 528 (BC_4, SD2_REF_CLK2_N, observe_only, X) ," &
" 529 (BC_8, TSEC_1588_PULSE_OUT2, bidir, X, 530, 0, Z) ," &
" 530 (BC_2, *, control, 0) ," &
" 531 (BC_8, TSEC_1588_PULSE_OUT1, bidir, X, 532, 0, Z) ," &
" 532 (BC_2, *, control, 0) ," &
" 533 (BC_8, TSEC_1588_TRIG_IN1, bidir, X, 534, 0, Z) ," &
" 534 (BC_2, *, control, 0) ," &
" 535 (BC_8, TSEC_1588_ALARM_OUT2, bidir, X, 536, 0, Z) ," &
" 536 (BC_2, *, control, 0) ," &
" 537 (BC_8, TSEC_1588_CLK_OUT, bidir, X, 538, 0, Z) ," &
" 538 (BC_2, *, control, 0) ," &
" 539 (BC_8, EC2_TXD0, bidir, X, 540, 0, Z) ," &
" 540 (BC_2, *, control, 0) ," &
" 541 (BC_8, EC2_TXD3, bidir, X, 542, 0, Z) ," &
" 542 (BC_2, *, control, 0) ," &
" 543 (BC_8, TSEC_1588_TRIG_IN2, bidir, X, 544, 0, Z) ," &
" 544 (BC_2, *, control, 0) ," &
" 545 (BC_8, TSEC_1588_ALARM_OUT1, bidir, X, 546, 0, Z) ," &
" 546 (BC_2, *, control, 0) ," &
" 547 (BC_8, EC2_TXD2, bidir, X, 548, 0, Z) ," &
" 548 (BC_2, *, control, 0) ," &
" 549 (BC_8, TSEC_1588_CLK_IN, bidir, X, 550, 0, Z) ," &
" 550 (BC_2, *, control, 0) ," &
" 551 (BC_8, EC2_TXD1, bidir, X, 552, 0, Z) ," &
" 552 (BC_2, *, control, 0) ," &
" 553 (BC_8, EC2_GTX_CLK125, bidir, X, 554, 0, Z) ," &
" 554 (BC_2, *, control, 0) ," &
" 555 (BC_8, EC2_RXD1, bidir, X, 556, 0, Z) ," &
" 556 (BC_2, *, control, 0) ," &
" 557 (BC_8, EC2_RX_CLK, bidir, X, 558, 0, Z) ," &
" 558 (BC_2, *, control, 0) ," &
" 559 (BC_8, EC2_TX_CTL, bidir, X, 560, 0, Z) ," &
" 560 (BC_2, *, control, 0) ," &
" 561 (BC_8, EC2_RXD2, bidir, X, 562, 0, Z) ," &
" 562 (BC_2, *, control, 0) ," &
" 563 (BC_8, EC2_RX_CTL, bidir, X, 564, 0, Z) ," &
" 564 (BC_2, *, control, 0) ," &
" 565 (BC_8, EC2_GTX_CLK, bidir, X, 566, 0, Z) ," &
" 566 (BC_2, *, control, 0) ," &
" 567 (BC_8, EC2_RXD0, bidir, X, 568, 0, Z) ," &
" 568 (BC_2, *, control, 0) ," &
" 569 (BC_8, EC2_RXD3, bidir, X, 570, 0, Z) ," &
" 570 (BC_2, *, control, 0) ," &
" 571 (BC_8, IRQ07, bidir, X, 572, 0, Z) ," &
" 572 (BC_2, *, control, 0) ," &
" 573 (BC_8, EMI1_MDC, bidir, X, 574, 0, Z) ," &
" 574 (BC_2, *, control, 0) ," &
" 575 (BC_8, EC1_TXD0, bidir, X, 576, 0, Z) ," &
" 576 (BC_2, *, control, 0) ," &
" 577 (BC_8, EMI1_MDIO, bidir, X, 578, 0, Z) ," &
" 578 (BC_2, *, control, 0) ," &
" 579 (BC_8, EC1_GTX_CLK, bidir, X, 580, 0, Z) ," &
" 580 (BC_2, *, control, 0) ," &
" 581 (BC_8, EC1_TXD1, bidir, X, 582, 0, Z) ," &
" 582 (BC_2, *, control, 0) ," &
" 583 (BC_8, IRQ09, bidir, X, 584, 0, Z) ," &
" 584 (BC_2, *, control, 0) ," &
" 585 (BC_8, EC1_TXD3, bidir, X, 586, 0, Z) ," &
" 586 (BC_2, *, control, 0) ," &
" 587 (BC_8, EC1_TXD2, bidir, X, 588, 0, Z) ," &
" 588 (BC_2, *, control, 0) ," &
" 589 (BC_8, EC1_GTX_CLK125, bidir, X, 590, 0, Z) ," &
" 590 (BC_2, *, control, 0) ," &
" 591 (BC_8, EC1_TX_CTL, bidir, X, 592, 0, Z) ," &
" 592 (BC_2, *, control, 0) ," &
" 593 (BC_8, EC1_RX_CTL, bidir, X, 594, 0, Z) ," &
" 594 (BC_2, *, control, 0) ," &
" 595 (BC_8, EC1_RXD3, bidir, X, 596, 0, Z) ," &
" 596 (BC_2, *, control, 0) ," &
" 597 (BC_8, EC1_RXD0, bidir, X, 598, 0, Z) ," &
" 598 (BC_2, *, control, 0) ," &
" 599 (BC_8, IRQ06, bidir, X, 600, 0, Z) ," &
" 600 (BC_2, *, control, 0) ," &
" 601 (BC_8, EC1_RX_CLK, bidir, X, 602, 0, Z) ," &
" 602 (BC_2, *, control, 0) ," &
" 603 (BC_8, EC1_RXD1, bidir, X, 604, 0, Z) ," &
" 604 (BC_2, *, control, 0) ," &
" 605 (BC_8, EC1_RXD2, bidir, X, 606, 0, Z) ," &
" 606 (BC_2, *, control, 0) ," &
" 607 (BC_8, IRQ08, bidir, X, 608, 0, Z) ," &
" 608 (BC_2, *, control, 0) ," &
" 609 (BC_2, LP_TMP_DETECT_B, input, X) ," &
" 610 (BC_2, *, internal, X) ," &
" 611 (BC_8, IIC4_SDA, bidir, X, 612, 0, Z) ," &
" 612 (BC_2, *, control, 0) ," &
" 613 (BC_8, IIC4_SCL, bidir, X, 614, 0, Z) ," &
" 614 (BC_2, *, control, 0) ," &
" 615 (BC_8, UART1_SOUT, bidir, X, 616, 0, Z) ," &
" 616 (BC_2, *, control, 0) ," &
" 617 (BC_8, DMA2_DACK0_B, bidir, X, 618, 0, Z) ," &
" 618 (BC_2, *, control, 0) ," &
" 619 (BC_8, UART2_SOUT, bidir, X, 620, 0, Z) ," &
" 620 (BC_2, *, control, 0) ," &
" 621 (BC_8, IIC2_SDA, bidir, X, 622, 0, Z) ," &
" 622 (BC_2, *, control, 0) ," &
" 623 (BC_8, UART1_SIN, bidir, X, 624, 0, Z) ," &
" 624 (BC_2, *, control, 0) ," &
" 625 (BC_8, IIC3_SDA, bidir, X, 626, 0, Z) ," &
" 626 (BC_2, *, control, 0) ," &
" 627 (BC_8, UART1_RTS_B, bidir, X, 628, 0, Z) ," &
" 628 (BC_2, *, control, 0) ," &
" 629 (BC_8, IIC1_SCL, bidir, X, 630, 0, Z) ," &
" 630 (BC_2, *, control, 0) ," &
" 631 (BC_8, UART1_CTS_B, bidir, X, 632, 0, Z) ," &
" 632 (BC_2, *, control, 0) ," &
" 633 (BC_8, UART2_CTS_B, bidir, X, 634, 0, Z) ," &
" 634 (BC_2, *, control, 0) ," &
" 635 (BC_8, IIC1_SDA, bidir, X, 636, 0, Z) ," &
" 636 (BC_2, *, control, 0) ," &
" 637 (BC_8, DMA2_DDONE0_B, bidir, X, 638, 0, Z) ," &
" 638 (BC_2, *, control, 0) ," &
" 639 (BC_8, DMA1_DACK0_B, bidir, X, 640, 0, Z) ," &
" 640 (BC_2, *, control, 0) ," &
" 641 (BC_8, UART2_SIN, bidir, X, 642, 0, Z) ," &
" 642 (BC_2, *, control, 0) ," &
" 643 (BC_8, IIC2_SCL, bidir, X, 644, 0, Z) ," &
" 644 (BC_2, *, control, 0) ," &
" 645 (BC_8, UART2_RTS_B, bidir, X, 646, 0, Z) ," &
" 646 (BC_2, *, control, 0) ," &
" 647 (BC_8, DMA2_DREQ0_B, bidir, X, 648, 0, Z) ," &
" 648 (BC_2, *, control, 0) ," &
" 649 (BC_8, DMA1_DDONE0_B, bidir, X, 650, 0, Z) ," &
" 650 (BC_2, *, control, 0) ," &
" 651 (BC_8, DMA1_DREQ0_B, bidir, X, 652, 0, Z) ," &
" 652 (BC_2, *, control, 0) ," &
" 653 (BC_8, IRQ11, bidir, X, 654, 0, Z) ," &
" 654 (BC_2, *, control, 0) ," &
" 655 (BC_8, IIC3_SCL, bidir, X, 656, 0, Z) ," &
" 656 (BC_2, *, control, 0) ," &
" 657 (BC_8, SPI_CS3_B, bidir, X, 658, 0, Z) ," &
" 658 (BC_2, *, control, 0) ," &
" 659 (BC_8, SPI_MOSI, bidir, X, 660, 0, Z) ," &
" 660 (BC_2, *, control, 0) ," &
" 661 (BC_8, SPI_MISO, bidir, X, 662, 0, Z) ," &
" 662 (BC_2, *, control, 0) ," &
" 663 (BC_8, SPI_CS2_B, bidir, X, 664, 0, Z) ," &
" 664 (BC_2, *, control, 0) ," &
" 665 (BC_8, SPI_CS1_B, bidir, X, 666, 0, Z) ," &
" 666 (BC_2, *, control, 0) ," &
" 667 (BC_8, SPI_CLK, bidir, X, 668, 0, Z) ," &
" 668 (BC_2, *, control, 0) ," &
" 669 (BC_8, IRQ10, bidir, X, 670, 0, Z) ," &
" 670 (BC_2, *, control, 0) ," &
" 671 (BC_8, SPI_CS0_B, bidir, X, 672, 0, Z) ," &
" 672 (BC_2, *, control, 0) ," &
" 673 (BC_8, SDHC_CD_B, bidir, X, 674, 0, Z) ," &
" 674 (BC_2, *, control, 0) ," &
" 675 (BC_8, SDHC_WP, bidir, X, 676, 0, Z) ," &
" 676 (BC_2, *, control, 0) ," &
" 677 (BC_8, SDHC_DAT3, bidir, X, 678, 0, Z) ," &
" 678 (BC_2, *, control, 0) ," &
" 679 (BC_8, SDHC_DAT2, bidir, X, 680, 0, Z) ," &
" 680 (BC_2, *, control, 0) ," &
" 681 (BC_0, EMI2_MDIO, output2, 1, 681, 1, WEAK1)," &
" 682 (BC_2, *, internal, 0) ," &
" 683 (BC_8, SDHC_DAT0, bidir, X, 684, 0, Z) ," &
" 684 (BC_2, *, control, 0) ," &
" 685 (BC_8, SDHC_DAT1, bidir, X, 686, 0, Z) ," &
" 686 (BC_2, *, control, 0) ," &
" 687 (BC_0, EMI2_MDC, output2, 1, 687, 1, WEAK1)," &
" 688 (BC_2, *, internal, X) ," &
" 689 (BC_8, SDHC_CMD, bidir, X, 690, 0, Z) ," &
" 690 (BC_2, *, control, 0) ," &
" 691 (BC_8, SDHC_CLK, bidir, X, 692, 0, Z) ," &
" 692 (BC_2, *, control, 0) ," &
" 693 (BC_2, *, control, 0) ," &
" 694 (BC_1, USB2_DRVVBUS, output3, X, 693, 0, Z) ," &
" 695 (BC_2, *, internal, X) ," &
" 696 (BC_2, USB2_VBUSCLMP, input, X) ," &
" 697 (BC_2, *, internal, X) ," &
" 698 (BC_2, USB2_PWRFAULT, input, X) ," &
" 699 (BC_2, *, internal, X) ," &
" 700 (BC_2, USB2_UID, input, X) ," &
" 701 (BC_2, *, internal, 0) ," &
" 702 (BC_7, USB2_UDP, bidir, X, 703, 0, Z) ," &
" 703 (BC_2, *, control, 0) ," &
" 704 (BC_2, *, control, 0) ," &
" 705 (BC_1, USB1_DRVVBUS, output3, X, 704, 0, Z) ," &
" 706 (BC_2, *, internal, X) ," &
" 707 (BC_2, USB1_VBUSCLMP, input, X) ," &
" 708 (BC_2, *, internal, X) ," &
" 709 (BC_2, USB1_PWRFAULT, input, X) ," &
" 710 (BC_2, *, internal, X) ," &
" 711 (BC_2, USB1_UID, input, X) ," &
" 712 (BC_2, *, internal, 0) ," &
" 713 (BC_7, USB1_UDP, bidir, X, 714, 0, Z) ," &
" 714 (BC_2, *, control, 0) ," &
" 715 (BC_2, PORESET_B, input, X) ," &
" 716 (BC_2, *, internal, X) ," &
" 717 (BC_2, SYSCLK, input, X) ," &
" 718 (BC_2, *, internal, X) ," &
" 719 (BC_8, IRQ00, bidir, X, 720, 0, Z) ," &
" 720 (BC_2, *, control, 0) ";
attribute AIO_COMPONENT_CONFORMANCE of T2080: entity is "STD_1149_6_2003";
attribute AIO_PIN_BEHAVIOR of T2080: entity is
"SD1_TX0_P : AC_SELECT=435;"&
"SD1_TX1_P : AC_SELECT=440;"&
"SD1_TX2_P : AC_SELECT=449;"&
"SD1_TX3_P : AC_SELECT=454;"&
"SD1_TX4_P : AC_SELECT=459;"&
"SD1_TX5_P : AC_SELECT=464;"&
"SD1_TX6_P : AC_SELECT=469;"&
"SD1_TX7_P : AC_SELECT=474;"&
"SD2_TX0_P : AC_SELECT=483;"&
"SD2_TX1_P : AC_SELECT=488;"&
"SD2_TX2_P : AC_SELECT=497;"&
"SD2_TX3_P : AC_SELECT=502;"&
"SD2_TX4_P : AC_SELECT=507;"&
"SD2_TX5_P : AC_SELECT=512;"&
"SD2_TX6_P : AC_SELECT=517;"&
"SD2_TX7_P : AC_SELECT=522;"&
"SD1_REF_CLK1_P [445] : HP_TIME=1.0e-07;"&
"SD1_REF_CLK2_P [479] : HP_TIME=1.0e-07;"&
"SD1_RX0_P [433] : HP_TIME=1.0e-07;"&
"SD1_RX1_P [442] : HP_TIME=1.0e-07;"&
"SD1_RX2_P [447] : HP_TIME=1.0e-07;"&
"SD1_RX3_P [456] : HP_TIME=1.0e-07;"&
"SD1_RX4_P [457] : HP_TIME=1.0e-07;"&
"SD1_RX5_P [466] : HP_TIME=1.0e-07;"&
"SD1_RX6_P [467] : HP_TIME=1.0e-07;"&
"SD1_RX7_P [476] : HP_TIME=1.0e-07;"&
"SD2_REF_CLK1_P [493] : HP_TIME=1.0e-07;"&
"SD2_REF_CLK2_P [527] : HP_TIME=1.0e-07;"&
"SD2_RX0_P [481] : HP_TIME=1.0e-07;"&
"SD2_RX1_P [490] : HP_TIME=1.0e-07;"&
"SD2_RX2_P [495] : HP_TIME=1.0e-07;"&
"SD2_RX3_P [504] : HP_TIME=1.0e-07;"&
"SD2_RX4_P [505] : HP_TIME=1.0e-07;"&
"SD2_RX5_P [514] : HP_TIME=1.0e-07;"&
"SD2_RX6_P [515] : HP_TIME=1.0e-07;"&
"SD2_RX7_P [524] : HP_TIME=1.0e-07";
attribute DESIGN_WARNING of T2080: entity is
"WARNING: The advanced I/O pins are compliant with IEEE 1149.6. "&
"except there are limitations placed on SAMPLE due to the inherent "&
"issues with capturing the value of gigabit signaling with the slow "&
"asynchronous TCK at the 1149.6 Test Receivers across externally "&
"ac-coupled interfaces. "&
" "&
"When TDR[sd_sample_overide] (bit 15) is set, then the SDm_RXn and "&
"SDm_RX_Bn will capture values on the pins during SAMPLE. Unless the "&
"value driven is slow or static, the value cannot be predicted. If "&
"the lane are running at a selected protocol frequency, use of "&
"SAMPLE may create an effect on the signal integrity of the "&
"functional data transmissions. "&
" "&
"If TDR[sd_sample_override] bit is set, the Serdes receive and "&
"transmit signals use an internal DC-coupled sample configuration "&
"based on electrical settings from the IOCONFIG TDR register. When "&
"the TDR[sd_sample_override] bit is not set, then the SerDes receive "&
"and transmit signals use an internal AC-coupled sample "&
"configuration based on their normal electrical settings from the "&
"functional mission logic during SAMPLE. "&
" "&
"After Update-IR or Update-DR states while in the EXTEST, "&
"EXTEST_TRAIN, EXTEST_PULSE, or CLAMP instructions, usage of a "&
"transition through the optional Run-Test-Idle state to allow for "&
"the timing for input setup or output hold on non-TAP pins to be "&
"satisfied is recommended. ";
end T2080;