-- CYD36S72V18.bsdl
----------------------------------------------------------------------
entity CYD36S72V18 is
-- This section identifies the default device package.
generic (PHYSICAL_PIN_MAP: string:= "BGA_484");
-- This section declares all the ports in the design.
port (
ADSnL : in bit;
CE0nL : in bit;
CE1L : in bit;
CNTENnL : in bit;
CNTMSKnL : in bit;
CNTRSTnL : in bit;
FTSELnL : in bit;
LOWSPDnL : in bit;
RETnL : in bit;
RWnL : in bit;
WRPnL : in bit;
MRSTn : in bit;
ADSnR : in bit;
CE0nR : in bit;
CE1R : in bit;
CNTENnR : in bit;
CNTMSKnR : in bit;
CNTRSTnR : in bit;
FTSELnR : in bit;
LOWSPDnR : in bit;
RETnR : in bit;
RWnR : in bit;
WRPnR : in bit;
TCK : in bit;
TDI : in bit;
TMS : in bit;
TRSTn : in bit;
BEn6L : in bit;
BEn4L : in bit;
BEn2L : in bit;
BEn0L : in bit;
OEnL : in bit;
PORTSTD1L : linkage bit;
PORTSTD0L : linkage bit;
BEn6R : in bit;
BEn4R : in bit;
BEn2R : in bit;
BEn0R : in bit;
OEnR : in bit;
PORTSTD1R : linkage bit;
PORTSTD0R : linkage bit;
A18L : inout bit;
A17L : inout bit;
A16L : inout bit;
A15L : inout bit;
A14L : inout bit;
A13L : inout bit;
A12L : inout bit;
A11L : inout bit;
A10L : inout bit;
A9L : inout bit;
A8L : inout bit;
A7L : inout bit;
A6L : inout bit;
A5L : inout bit;
A4L : inout bit;
A3L : inout bit;
A2L : inout bit;
A1L : inout bit;
A0L : inout bit;
DQ62L : inout bit;
DQ61L : inout bit;
DQ60L : inout bit;
DQ59L : inout bit;
DQ58L : inout bit;
DQ57L : inout bit;
DQ56L : inout bit;
DQ55L : inout bit;
DQ54L : inout bit;
DQ44L : inout bit;
DQ43L : inout bit;
DQ42L : inout bit;
DQ41L : inout bit;
DQ40L : inout bit;
DQ39L : inout bit;
DQ38L : inout bit;
DQ37L : inout bit;
DQ36L : inout bit;
DQ26L : inout bit;
DQ25L : inout bit;
DQ24L : inout bit;
DQ23L : inout bit;
DQ22L : inout bit;
DQ21L : inout bit;
DQ20L : inout bit;
DQ19L : inout bit;
DQ18L : inout bit;
DQ8L : inout bit;
DQ7L : inout bit;
DQ6L : inout bit;
DQ5L : inout bit;
DQ4L : inout bit;
DQ3L : inout bit;
DQ2L : inout bit;
DQ1L : inout bit;
DQ0L : inout bit;
A18R : inout bit;
A17R : inout bit;
A16R : inout bit;
A15R : inout bit;
A14R : inout bit;
A13R : inout bit;
A12R : inout bit;
A11R : inout bit;
A10R : inout bit;
A9R : inout bit;
A8R : inout bit;
A7R : inout bit;
A6R : inout bit;
A5R : inout bit;
A4R : inout bit;
A3R : inout bit;
A2R : inout bit;
A1R : inout bit;
A0R : inout bit;
DQ62R : inout bit;
DQ61R : inout bit;
DQ60R : inout bit;
DQ59R : inout bit;
DQ58R : inout bit;
DQ57R : inout bit;
DQ56R : inout bit;
DQ55R : inout bit;
DQ54R : inout bit;
DQ44R : inout bit;
DQ43R : inout bit;
DQ42R : inout bit;
DQ41R : inout bit;
DQ40R : inout bit;
DQ39R : inout bit;
DQ38R : inout bit;
DQ37R : inout bit;
DQ36R : inout bit;
DQ26R : inout bit;
DQ25R : inout bit;
DQ24R : inout bit;
DQ23R : inout bit;
DQ22R : inout bit;
DQ21R : inout bit;
DQ20R : inout bit;
DQ19R : inout bit;
DQ18R : inout bit;
DQ8R : inout bit;
DQ7R : inout bit;
DQ6R : inout bit;
DQ5R : inout bit;
DQ4R : inout bit;
DQ3R : inout bit;
DQ2R : inout bit;
DQ1R : inout bit;
DQ0R : inout bit;
TDO : out bit;
READYnL : buffer bit;
READYnR : buffer bit;
CL : linkage bit;
ZQ0L : linkage bit;
CR : linkage bit;
ZQ0R : linkage bit;
VREFL : linkage bit_vector (0 to 1);
VREFR : linkage bit_vector (0 to 1);
VDDIOL : linkage bit_vector (0 to 33);
VDDIOR : linkage bit_vector (0 to 33);
VTTL : linkage bit_vector (0 to 11);
VCORE : linkage bit_vector (0 to 15);
VSS : linkage bit_vector (0 to 117);
NC : linkage bit_vector (0 to 107)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of CYD36S72V18: entity is
"STD_1149_1_2001";
attribute PIN_MAP of CYD36S72V18: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port.
constant BGA_484: PIN_MAP_STRING :=
"ADSnL : N3," &
"CE0nL : F4," &
"CE1L : F3," &
"CNTENnL : R3," &
"CNTMSKnL : P3," &
"CNTRSTnL : T3," &
"FTSELnL : V3," &
"LOWSPDnL : D9," &
"RETnL : G3," &
"RWnL : U3," &
"WRPnL : H3," &
"MRSTn : W4," &
"ADSnR : N20," &
"CE0nR : F19," &
"CE1R : F20," &
"CNTENnR : R20," &
"CNTMSKnR : P20," &
"CNTRSTnR : T20," &
"FTSELnR : V20," &
"LOWSPDnR : W14," &
"RETnR : G20," &
"RWnR : U20," &
"WRPnR : H20," &
"TCK : Y20," &
"TDI : W19," &
"TMS : Y19," &
"TRSTn : V18," &
"BEn6L : J4," &
"BEn4L : G4," &
"BEn2L : N4," &
"BEn0L : R4," &
"OEnL : L4," &
"PORTSTD1L : D14," &
"PORTSTD0L : D10," &
"BEn6R : J19," &
"BEn4R : G19," &
"BEn2R : N19," &
"BEn0R : R19," &
"OEnR : L19," &
"PORTSTD1R : W9," &
"PORTSTD0R : W13," &
"A18L : T1," &
"A17L : R2," &
"A16L : R1," &
"A15L : P2," &
"A14L : P1," &
"A13L : N2," &
"A12L : N1," &
"A11L : M2," &
"A10L : M1," &
"A9L : L2," &
"A8L : L1," &
"A7L : K2," &
"A6L : K1," &
"A5L : J2," &
"A4L : J1," &
"A3L : H2," &
"A2L : H1," &
"A1L : G2," &
"A0L : G1," &
"DQ62L : B2," &
"DQ61L : A2," &
"DQ60L : B3," &
"DQ59L : A3," &
"DQ58L : B4," &
"DQ57L : A4," &
"DQ56L : C5," &
"DQ55L : B5," &
"DQ54L : A5," &
"DQ44L : C9," &
"DQ43L : B9," &
"DQ42L : A9," &
"DQ41L : C10," &
"DQ40L : B10," &
"DQ39L : A10," &
"DQ38L : C11," &
"DQ37L : B11," &
"DQ36L : A11," &
"DQ26L : AA2," &
"DQ25L : AB2," &
"DQ24L : AA3," &
"DQ23L : AB3," &
"DQ22L : AA4," &
"DQ21L : AB4," &
"DQ20L : Y5," &
"DQ19L : AA5," &
"DQ18L : AB5," &
"DQ8L : Y9," &
"DQ7L : AA9," &
"DQ6L : AB9," &
"DQ5L : Y10," &
"DQ4L : AA10," &
"DQ3L : AB10," &
"DQ2L : Y11," &
"DQ1L : AA11," &
"DQ0L : AB11," &
"A18R : T22," &
"A17R : R21," &
"A16R : R22," &
"A15R : P21," &
"A14R : P22," &
"A13R : N21," &
"A12R : N22," &
"A11R : M21," &
"A10R : M22," &
"A9R : L21," &
"A8R : L22," &
"A7R : K21," &
"A6R : K22," &
"A5R : J21," &
"A4R : J22," &
"A3R : H21," &
"A2R : H22," &
"A1R : G21," &
"A0R : G22," &
"DQ62R : B21," &
"DQ61R : A21," &
"DQ60R : B20," &
"DQ59R : A20," &
"DQ58R : B19," &
"DQ57R : A19," &
"DQ56R : C18," &
"DQ55R : B18," &
"DQ54R : A18," &
"DQ44R : C14," &
"DQ43R : B14," &
"DQ42R : A14," &
"DQ41R : C13," &
"DQ40R : B13," &
"DQ39R : A13," &
"DQ38R : C12," &
"DQ37R : B12," &
"DQ36R : A12," &
"DQ26R : AA21," &
"DQ25R : AB21," &
"DQ24R : AA20," &
"DQ23R : AB20," &
"DQ22R : AA19," &
"DQ21R : AB19," &
"DQ20R : Y18," &
"DQ19R : AA18," &
"DQ18R : AB18," &
"DQ8R : Y14," &
"DQ7R : AA14," &
"DQ6R : AB14," &
"DQ5R : Y13," &
"DQ4R : AA13," &
"DQ3R : AB13," &
"DQ2R : Y12," &
"DQ1R : AA12," &
"DQ0R : AB12," &
"TDO : W20," &
"READYnL : J3," &
"READYnR : J20," &
"CL : L3," &
"ZQ0L : D11," &
"CR : L20," &
"ZQ0R : W12," &
"VREFL : (G7, T7)," &
"VREFR : (G16, T16)," &
"VDDIOL : (E10, E3, E6, E7, E8, E9, F5, F6, F7," &
"F8, F9, G5, G6, H5, H6, J5, J6, N5," &
"P5, P6, R5, R6, T5, T6, U5, U6, U7," &
"U8, U9, V4, V6, V7, V8, V9)," &
"VDDIOR : (E14, E15, E16, E17, E20, F14, F15, F16, F17," &
"F18, G17, G18, H17, H18, J17, J18, K18, P17," &
"P18, R17, R18, T17, T18, U14, U15, U16, U17," &
"U18, V13, V14, V15, V16, V17, V19)," &
"VTTL : (E11, E12, E13, K5, L18, L5, M18, M5, N18," &
"V10, V11, V12)," &
"VCORE : (F10, F11, F12, F13, K17, K6, L17, L6, M17," &
"M6, N17, N6, U10, U11, U12, U13)," &
"VSS : (C19, C3, D18, D19, D20, D3, D4, D5, E19," &
"E4, E5, G10, G11, G12, G13, G14, G15, G8," &
"G9, H10, H11, H12, H13, H14, H15, H16, H7," &
"H8, H9, J10, J11, J12, J13, J14, J15, J16," &
"J7, J8, J9, K10, K11, K12, K13, K14, K15," &
"K16, K7, K8, K9, L10, L11, L12, L13, L14," &
"L15, L16, L7, L8, L9, M10, M11, M12, M13," &
"M14, M15, M16, M7, M8, M9, N10, N11, N12," &
"N13, N14, N15, N16, N7, N8, N9, P10, P11," &
"P12, P13, P14, P15, P16, P7, P8, P9, R10," &
"R11, R12, R13, R14, R15, R16, R7, R8, R9," &
"T10, T11, T12, T13, T14, T15, T8, T9, W18," &
"W3, W5, Y3, Y4, C4, C20, D8, M3, M20," &
"W15)," &
"NC : (A1, A22, AB1, AB22, D15, E18, T2, T21, V5, " &
"W8," &
"P4, P19, M4, M19, H4, H19, K4, K19, D12," &
"W11, D13, W10, W6, W17, D6, D17, W7, W16," &
"D7, D16, U4, U19, AA8, AA15, Y8, Y15, AB7," &
"AB16, AA7, AA16, Y7, Y16, AB6, AB17, AA6, AA17," &
"Y6, Y17, AA1, AA22, Y2, Y21, Y1, Y22, W2," &
"W21, W1, W22, V2, V21, V1, V22, U2, U21," &
"U1, U22, A8, A15, B8, B15, C8, C15, A7," &
"A16, B7, B16, C7, C16, A6, A17, B6, B17," &
"C6, C17, B1, B22, C2, C21, C1, C22, D2," &
"D21, D1, D22, E2, E21, E1, E22, F2, F21," &
"F1, F22, AB8, AB15, T4, T19, K3, K20)";
-- This section specifies the TAP ports. For the TAP TCK
-- port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (2.000000e+07, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTn : signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of CYD36S72V18: entity is 4;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of CYD36S72V18: entity is
"BYPASS (1111)," &
"EXTEST (0000)," &
"SAMPLE (1000)," &
"PRELOAD (1000)," &
"CLAMP (0100)," &
"HIGHZ (0111)," &
"NBSRST (1100)," &
"IDCODE (1011)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of CYD36S72V18: entity is "0001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of CYD36S72V18: entity is
"0000" & -- 4-bit version number
"1100000000100110" & -- 16-bit part number
"00000110100" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of CYD36S72V18: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ, NBSRST)," &
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of CYD36S72V18: entity is 476;
-- The following list specifies the characteristics of each cell in
-- the boundary scan register from TDI to TDO. The following is a
-- description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not have
-- a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the control
-- cell to disable the output enable for the
-- corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of CYD36S72V18: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"475 (BC_4, *, internal, X), " &
"474 (BC_4, LOWSPDnR, observe_only, X), " &
"473 (BC_4, FTSELnR, observe_only, X), " &
"472 (BC_4, *, internal, X), " &
"471 (BC_2, *, internal, X), " &
"470 (BC_4, *, internal, X), " &
"469 (BC_2, DQ8R, output3, X, 451, 0, Z), " &
"468 (BC_4, DQ8R, observe_only, X), " &
"467 (BC_2, *, internal, X), " &
"466 (BC_4, *, internal, X), " &
"465 (BC_2, DQ7R, output3, X, 451, 0, Z), " &
"464 (BC_4, DQ7R, observe_only, X), " &
"463 (BC_2, *, internal, X), " &
"462 (BC_4, *, internal, X), " &
"461 (BC_2, DQ6R, output3, X, 451, 0, Z), " &
"460 (BC_4, DQ6R, observe_only, X), " &
"459 (BC_2, *, internal, X), " &
"458 (BC_4, *, internal, X), " &
"457 (BC_2, DQ5R, output3, X, 451, 0, Z), " &
"456 (BC_4, DQ5R, observe_only, X), " &
"455 (BC_2, *, internal, X), " &
"454 (BC_4, *, internal, X), " &
"453 (BC_2, DQ4R, output3, X, 451, 0, Z), " &
"452 (BC_4, DQ4R, observe_only, X), " &
"451 (BC_2, *, control, 0), " &
"450 (BC_4, BEn0R, observe_only, X), " &
"449 (BC_2, *, internal, 0), " &
"448 (BC_4, *, internal, X), " &
"447 (BC_2, *, internal, X), " &
"446 (BC_4, *, internal, X), " &
"445 (BC_2, DQ3R, output3, X, 451, 0, Z), " &
"444 (BC_4, DQ3R, observe_only, X), " &
"443 (BC_2, *, internal, X), " &
"442 (BC_4, *, internal, X), " &
"441 (BC_2, DQ2R, output3, X, 451, 0, Z), " &
"440 (BC_4, DQ2R, observe_only, X), " &
"439 (BC_2, *, internal, X), " &
"438 (BC_4, *, internal, X), " &
"437 (BC_2, DQ1R, output3, X, 451, 0, Z), " &
"436 (BC_4, DQ1R, observe_only, X), " &
"435 (BC_2, *, internal, X), " &
"434 (BC_4, *, internal, X), " &
"433 (BC_2, DQ0R, output3, X, 451, 0, Z), " &
"432 (BC_4, DQ0R, observe_only, X), " &
"431 (BC_2, *, internal, X), " &
"430 (BC_2, *, internal, X), " &
"429 (BC_2, *, internal, X), " &
"428 (BC_2, DQ0L, output3, X, 412, 0, Z), " &
"427 (BC_4, DQ0L, observe_only, X), " &
"426 (BC_2, *, internal, X), " &
"425 (BC_4, *, internal, X), " &
"424 (BC_2, DQ1L, output3, X, 412, 0, Z), " &
"423 (BC_4, DQ1L, observe_only, X), " &
"422 (BC_2, *, internal, X), " &
"421 (BC_4, *, internal, X), " &
"420 (BC_2, DQ2L, output3, X, 412, 0, Z), " &
"419 (BC_4, DQ2L, observe_only, X), " &
"418 (BC_2, *, internal, X), " &
"417 (BC_4, *, internal, X), " &
"416 (BC_2, DQ3L, output3, X, 412, 0, Z), " &
"415 (BC_4, DQ3L, observe_only, X), " &
"414 (BC_2, *, internal, X), " &
"413 (BC_4, *, internal, X), " &
"412 (BC_2, *, control, 0), " &
"411 (BC_4, BEn0L, observe_only, X), " &
"410 (BC_2, *, internal, 0), " &
"409 (BC_4, *, internal, X), " &
"408 (BC_2, DQ4L, output3, X, 412, 0, Z), " &
"407 (BC_4, DQ4L, observe_only, X), " &
"406 (BC_2, *, internal, X), " &
"405 (BC_4, *, internal, X), " &
"404 (BC_2, DQ5L, output3, X, 412, 0, Z), " &
"403 (BC_4, DQ5L, observe_only, X), " &
"402 (BC_2, *, internal, X), " &
"401 (BC_4, *, internal, X), " &
"400 (BC_2, DQ6L, output3, X, 412, 0, Z), " &
"399 (BC_4, DQ6L, observe_only, X), " &
"398 (BC_2, *, internal, X), " &
"397 (BC_4, *, internal, X), " &
"396 (BC_2, DQ7L, output3, X, 412, 0, Z), " &
"395 (BC_4, DQ7L, observe_only, X), " &
"394 (BC_2, *, internal, X), " &
"393 (BC_4, *, internal, X), " &
"392 (BC_2, DQ8L, output3, X, 412, 0, Z), " &
"391 (BC_4, DQ8L, observe_only, X), " &
"390 (BC_2, *, internal, X), " &
"389 (BC_4, *, internal, X), " &
"388 (BC_2, A11R, output3, X, 376, 0, Z), " &
"387 (BC_4, A11R, observe_only, X), " &
"386 (BC_2, A12R, output3, X, 376, 0, Z), " &
"385 (BC_4, A12R, observe_only, X), " &
"384 (BC_2, A13R, output3, X, 376, 0, Z), " &
"383 (BC_4, A13R, observe_only, X), " &
"382 (BC_2, A14R, output3, X, 376, 0, Z), " &
"381 (BC_4, A14R, observe_only, X), " &
"380 (BC_2, *, internal, X), " &
"379 (BC_4, *, internal, X), " &
"378 (BC_2, A15R, output3, X, 376, 0, Z), " &
"377 (BC_4, A15R, observe_only, X), " &
"376 (BC_2, *, control, 0), " &
"375 (BC_4, OEnR, observe_only, X), " &
"374 (BC_2, A16R, output3, X, 376, 0, Z), " &
"373 (BC_4, A16R, observe_only, X), " &
"372 (BC_2, A17R, output3, X, 376, 0, Z), " &
"371 (BC_4, A17R, observe_only, X), " &
"370 (BC_2, A18R, output3, X, 376, 0, Z), " &
"369 (BC_4, A18R, observe_only, X), " &
"368 (BC_2, *, internal, X), " &
"367 (BC_4, *, internal, X), " &
"366 (BC_4, CE1R, observe_only, X), " &
"365 (BC_4, CE0nR, observe_only, X), " &
"364 (BC_4, RWnR, observe_only, X), " &
"363 (BC_4, CNTMSKnR, observe_only, X), " &
"362 (BC_4, CNTENnR, observe_only, X), " &
"361 (BC_4, CNTRSTnR, observe_only, X), " &
"360 (BC_4, ADSnR, observe_only, X), " &
"359 (BC_4, RETnR, observe_only, X), " &
"358 (BC_4, WRPnR, observe_only, X), " &
"357 (BC_2, *, internal, X), " &
"356 (BC_2, *, internal, X), " &
"355 (BC_2, *, internal, X), " &
"354 (BC_1, READYnR, output2, X), " &
"353 (BC_2, *, internal, X), " &
"352 (BC_4, *, internal, X), " &
"351 (BC_2, *, internal, X), " &
"350 (BC_4, *, internal, X), " &
"349 (BC_2, A18L, output3, X, 338, 0, Z), " &
"348 (BC_4, A18L, observe_only, X), " &
"347 (BC_2, A17L, output3, X, 338, 0, Z), " &
"346 (BC_4, A17L, observe_only, X), " &
"345 (BC_2, A16L, output3, X, 338, 0, Z), " &
"344 (BC_4, A16L, observe_only, X), " &
"343 (BC_4, OEnL, observe_only, X), " &
"342 (BC_2, A15L, output3, X, 338, 0, Z), " &
"341 (BC_4, A15L, observe_only, X), " &
"340 (BC_2, A10L, output3, X, 338, 0, Z), " &
"339 (BC_4, A10L, observe_only, X), " &
"338 (BC_2, *, control, 0), " &
"337 (BC_2, A14L, output3, X, 338, 0, Z), " &
"336 (BC_4, A14L, observe_only, X), " &
"335 (BC_2, A13L, output3, X, 338, 0, Z), " &
"334 (BC_4, A13L, observe_only, X), " &
"333 (BC_2, A12L, output3, X, 338, 0, Z), " &
"332 (BC_4, A12L, observe_only, X), " &
"331 (BC_2, A11L, output3, X, 338, 0, Z), " &
"330 (BC_4, A11L, observe_only, X), " &
"329 (BC_2, *, internal, X), " &
"328 (BC_4, *, internal, X), " &
"327 (BC_2, DQ26R, output3, X, 307, 0, Z), " &
"326 (BC_4, DQ26R, observe_only, X), " &
"325 (BC_2, *, internal, X), " &
"324 (BC_4, *, internal, X), " &
"323 (BC_2, DQ25R, output3, X, 307, 0, Z), " &
"322 (BC_4, DQ25R, observe_only, X), " &
"321 (BC_2, *, internal, X), " &
"320 (BC_4, *, internal, X), " &
"319 (BC_2, DQ24R, output3, X, 307, 0, Z), " &
"318 (BC_4, DQ24R, observe_only, X), " &
"317 (BC_2, *, internal, X), " &
"316 (BC_4, *, internal, X), " &
"315 (BC_2, DQ23R, output3, X, 307, 0, Z), " &
"314 (BC_4, DQ23R, observe_only, X), " &
"313 (BC_2, *, internal, X), " &
"312 (BC_4, *, internal, X), " &
"311 (BC_2, DQ22R, output3, X, 307, 0, Z), " &
"310 (BC_4, DQ22R, observe_only, X), " &
"309 (BC_2, *, internal, 0), " &
"308 (BC_4, *, internal, X), " &
"307 (BC_2, *, control, 0), " &
"306 (BC_4, BEn2R, observe_only, X), " &
"305 (BC_2, *, internal, X), " &
"304 (BC_4, *, internal, X), " &
"303 (BC_2, DQ21R, output3, X, 307, 0, Z), " &
"302 (BC_4, DQ21R, observe_only, X), " &
"301 (BC_2, *, internal, X), " &
"300 (BC_4, *, internal, X), " &
"299 (BC_2, DQ20R, output3, X, 307, 0, Z), " &
"298 (BC_4, DQ20R, observe_only, X), " &
"297 (BC_2, *, internal, X), " &
"296 (BC_4, *, internal, X), " &
"295 (BC_2, DQ19R, output3, X, 307, 0, Z), " &
"294 (BC_4, DQ19R, observe_only, X), " &
"293 (BC_2, *, internal, X), " &
"292 (BC_4, *, internal, X), " &
"291 (BC_2, DQ18R, output3, X, 307, 0, Z), " &
"290 (BC_4, DQ18R, observe_only, X), " &
"289 (BC_2, *, internal, X), " &
"288 (BC_2, *, internal, X), " &
"287 (BC_2, *, internal, X), " &
"286 (BC_2, DQ18L, output3, X, 268, 0, Z), " &
"285 (BC_4, DQ18L, observe_only, X), " &
"284 (BC_2, *, internal, X), " &
"283 (BC_4, *, internal, X), " &
"282 (BC_2, DQ19L, output3, X, 268, 0, Z), " &
"281 (BC_4, DQ19L, observe_only, X), " &
"280 (BC_2, *, internal, X), " &
"279 (BC_4, *, internal, X), " &
"278 (BC_2, DQ20L, output3, X, 268, 0, Z), " &
"277 (BC_4, DQ20L, observe_only, X), " &
"276 (BC_2, *, internal, X), " &
"275 (BC_4, *, internal, X), " &
"274 (BC_2, DQ21L, output3, X, 268, 0, Z), " &
"273 (BC_4, DQ21L, observe_only, X), " &
"272 (BC_2, *, internal, X), " &
"271 (BC_4, *, internal, X), " &
"270 (BC_2, *, internal, 0), " &
"269 (BC_4, *, internal, X), " &
"268 (BC_2, *, control, 0), " &
"267 (BC_4, BEn2L, observe_only, X), " &
"266 (BC_2, DQ22L, output3, X, 268, 0, Z), " &
"265 (BC_4, DQ22L, observe_only, X), " &
"264 (BC_2, *, internal, X), " &
"263 (BC_4, *, internal, X), " &
"262 (BC_2, DQ23L, output3, X, 268, 0, Z), " &
"261 (BC_4, DQ23L, observe_only, X), " &
"260 (BC_2, *, internal, X), " &
"259 (BC_4, *, internal, X), " &
"258 (BC_2, DQ24L, output3, X, 268, 0, Z), " &
"257 (BC_4, DQ24L, observe_only, X), " &
"256 (BC_2, *, internal, X), " &
"255 (BC_4, *, internal, X), " &
"254 (BC_2, DQ25L, output3, X, 268, 0, Z), " &
"253 (BC_4, DQ25L, observe_only, X), " &
"252 (BC_2, *, internal, X), " &
"251 (BC_4, *, internal, X), " &
"250 (BC_2, DQ26L, output3, X, 268, 0, Z), " &
"249 (BC_4, DQ26L, observe_only, X), " &
"248 (BC_2, *, internal, X), " &
"247 (BC_4, *, internal, X), " &
"246 (BC_4, *, internal, X), " &
"245 (BC_4, *, internal, X), " &
"244 (BC_4, *, internal, X), " &
"243 (BC_4, *, internal, X), " &
"242 (BC_4, *, internal, X), " &
"241 (BC_4, *, internal, X), " &
"240 (BC_4, *, internal, X), " &
"239 (BC_4, FTSELnL, observe_only, X), " &
"238 (BC_4, MRSTn, observe_only, X), " &
"237 (BC_4, *, internal, X), " &
"236 (BC_4, *, internal, X), " &
"235 (BC_4, *, internal, X), " &
"234 (BC_4, *, internal, X), " &
"233 (BC_4, LOWSPDnL, observe_only, X), " &
"232 (BC_2, *, internal, X), " &
"231 (BC_4, *, internal, X), " &
"230 (BC_2, DQ62L, output3, X, 212, 0, Z), " &
"229 (BC_4, DQ62L, observe_only, X), " &
"228 (BC_2, *, internal, X), " &
"227 (BC_4, *, internal, X), " &
"226 (BC_2, DQ61L, output3, X, 212, 0, Z), " &
"225 (BC_4, DQ61L, observe_only, X), " &
"224 (BC_2, *, internal, X), " &
"223 (BC_4, *, internal, X), " &
"222 (BC_2, DQ60L, output3, X, 212, 0, Z), " &
"221 (BC_4, DQ60L, observe_only, X), " &
"220 (BC_2, *, internal, X), " &
"219 (BC_4, *, internal, X), " &
"218 (BC_2, DQ59L, output3, X, 212, 0, Z), " &
"217 (BC_4, DQ59L, observe_only, X), " &
"216 (BC_2, *, internal, X), " &
"215 (BC_4, *, internal, X), " &
"214 (BC_2, DQ58L, output3, X, 212, 0, Z), " &
"213 (BC_4, DQ58L, observe_only, X), " &
"212 (BC_2, *, control, 0), " &
"211 (BC_4, BEn6L, observe_only, X), " &
"210 (BC_2, *, internal, 0), " &
"209 (BC_4, *, internal, X), " &
"208 (BC_2, *, internal, X), " &
"207 (BC_4, *, internal, X), " &
"206 (BC_2, DQ57L, output3, X, 212, 0, Z), " &
"205 (BC_4, DQ57L, observe_only, X), " &
"204 (BC_2, *, internal, X), " &
"203 (BC_4, *, internal, X), " &
"202 (BC_2, DQ56L, output3, X, 212, 0, Z), " &
"201 (BC_4, DQ56L, observe_only, X), " &
"200 (BC_2, *, internal, X), " &
"199 (BC_4, *, internal, X), " &
"198 (BC_2, DQ55L, output3, X, 212, 0, Z), " &
"197 (BC_4, DQ55L, observe_only, X), " &
"196 (BC_2, *, internal, X), " &
"195 (BC_4, *, internal, X), " &
"194 (BC_2, DQ54L, output3, X, 212, 0, Z), " &
"193 (BC_4, DQ54L, observe_only, X), " &
"192 (BC_2, *, internal, X), " &
"191 (BC_2, *, internal, X), " &
"190 (BC_2, *, internal, X), " &
"189 (BC_2, DQ54R, output3, X, 173, 0, Z), " &
"188 (BC_4, DQ54R, observe_only, X), " &
"187 (BC_2, *, internal, X), " &
"186 (BC_4, *, internal, X), " &
"185 (BC_2, DQ55R, output3, X, 173, 0, Z), " &
"184 (BC_4, DQ55R, observe_only, X), " &
"183 (BC_2, *, internal, X), " &
"182 (BC_4, *, internal, X), " &
"181 (BC_2, DQ56R, output3, X, 173, 0, Z), " &
"180 (BC_4, DQ56R, observe_only, X), " &
"179 (BC_2, *, internal, X), " &
"178 (BC_4, *, internal, X), " &
"177 (BC_2, DQ57R, output3, X, 173, 0, Z), " &
"176 (BC_4, DQ57R, observe_only, X), " &
"175 (BC_2, *, internal, X), " &
"174 (BC_4, *, internal, X), " &
"173 (BC_2, *, control, 0), " &
"172 (BC_4, BEn6R, observe_only, X), " &
"171 (BC_2, *, internal, 0), " &
"170 (BC_4, *, internal, X), " &
"169 (BC_2, DQ58R, output3, X, 173, 0, Z), " &
"168 (BC_4, DQ58R, observe_only, X), " &
"167 (BC_2, *, internal, X), " &
"166 (BC_4, *, internal, X), " &
"165 (BC_2, DQ59R, output3, X, 173, 0, Z), " &
"164 (BC_4, DQ59R, observe_only, X), " &
"163 (BC_2, *, internal, X), " &
"162 (BC_4, *, internal, X), " &
"161 (BC_2, DQ60R, output3, X, 173, 0, Z), " &
"160 (BC_4, DQ60R, observe_only, X), " &
"159 (BC_2, *, internal, X), " &
"158 (BC_4, *, internal, X), " &
"157 (BC_2, DQ61R, output3, X, 173, 0, Z), " &
"156 (BC_4, DQ61R, observe_only, X), " &
"155 (BC_2, *, internal, X), " &
"154 (BC_4, *, internal, X), " &
"153 (BC_2, DQ62R, output3, X, 173, 0, Z), " &
"152 (BC_4, DQ62R, observe_only, X), " &
"151 (BC_2, *, internal, X), " &
"150 (BC_4, *, internal, X), " &
"149 (BC_2, A9L, output3, X, 139, 0, Z), " &
"148 (BC_4, A9L, observe_only, X), " &
"147 (BC_2, A8L, output3, X, 139, 0, Z), " &
"146 (BC_4, A8L, observe_only, X), " &
"145 (BC_2, A7L, output3, X, 139, 0, Z), " &
"144 (BC_4, A7L, observe_only, X), " &
"143 (BC_2, A6L, output3, X, 139, 0, Z), " &
"142 (BC_4, A6L, observe_only, X), " &
"141 (BC_2, A5L, output3, X, 139, 0, Z), " &
"140 (BC_4, A5L, observe_only, X), " &
"139 (BC_2, *, control, 0), " &
"138 (BC_2, A4L, output3, X, 139, 0, Z), " &
"137 (BC_4, A4L, observe_only, X), " &
"136 (BC_2, A3L, output3, X, 139, 0, Z), " &
"135 (BC_4, A3L, observe_only, X), " &
"134 (BC_2, A2L, output3, X, 139, 0, Z), " &
"133 (BC_4, A2L, observe_only, X), " &
"132 (BC_2, A1L, output3, X, 139, 0, Z), " &
"131 (BC_4, A1L, observe_only, X), " &
"130 (BC_2, A0L, output3, X, 139, 0, Z), " &
"129 (BC_4, A0L, observe_only, X), " &
"128 (BC_4, OEnL, observe_only, X), " &
"127 (BC_1, READYnL, output2, X), " &
"126 (BC_2, *, internal, X), " &
"125 (BC_2, *, internal, X), " &
"124 (BC_2, *, internal, X), " &
"123 (BC_4, RWnL, observe_only, X), " &
"122 (BC_4, CNTMSKnL, observe_only, X), " &
"121 (BC_4, CNTENnL, observe_only, X), " &
"120 (BC_4, CNTRSTnL, observe_only, X), " &
"119 (BC_4, ADSnL, observe_only, X), " &
"118 (BC_4, RETnL, observe_only, X), " &
"117 (BC_4, WRPnL, observe_only, X), " &
"116 (BC_4, CE0nL, observe_only, X), " &
"115 (BC_4, CE1L, observe_only, X), " &
"114 (BC_4, OEnR, observe_only, X), " &
"113 (BC_2, A0R, output3, X, 101, 0, Z), " &
"112 (BC_4, A0R, observe_only, X), " &
"111 (BC_2, A1R, output3, X, 101, 0, Z), " &
"110 (BC_4, A1R, observe_only, X), " &
"109 (BC_2, A2R, output3, X, 101, 0, Z), " &
"108 (BC_4, A2R, observe_only, X), " &
"107 (BC_2, A3R, output3, X, 101, 0, Z), " &
"106 (BC_4, A3R, observe_only, X), " &
"105 (BC_2, A4R, output3, X, 101, 0, Z), " &
"104 (BC_4, A4R, observe_only, X), " &
"103 (BC_2, A5R, output3, X, 101, 0, Z), " &
"102 (BC_4, A5R, observe_only, X), " &
"101 (BC_2, *, control, 0), " &
"100 (BC_2, A6R, output3, X, 101, 0, Z), " &
"99 (BC_4, A6R, observe_only, X), " &
"98 (BC_2, A7R, output3, X, 101, 0, Z), " &
"97 (BC_4, A7R, observe_only, X), " &
"96 (BC_2, A8R, output3, X, 101, 0, Z), " &
"95 (BC_4, A8R, observe_only, X), " &
"94 (BC_2, A9R, output3, X, 101, 0, Z), " &
"93 (BC_4, A9R, observe_only, X), " &
"92 (BC_2, A10R, output3, X, 101, 0, Z), " &
"91 (BC_4, A10R, observe_only, X), " &
"90 (BC_2, *, internal, X), " &
"89 (BC_4, *, internal, X), " &
"88 (BC_2, DQ44L, output3, X, 68, 0, Z), " &
"87 (BC_4, DQ44L, observe_only, X), " &
"86 (BC_2, *, internal, X), " &
"85 (BC_4, *, internal, X), " &
"84 (BC_2, DQ43L, output3, X, 68, 0, Z), " &
"83 (BC_4, DQ43L, observe_only, X), " &
"82 (BC_2, *, internal, X), " &
"81 (BC_4, *, internal, X), " &
"80 (BC_2, DQ42L, output3, X, 68, 0, Z), " &
"79 (BC_4, DQ42L, observe_only, X), " &
"78 (BC_2, *, internal, X), " &
"77 (BC_4, *, internal, X), " &
"76 (BC_2, DQ41L, output3, X, 68, 0, Z), " &
"75 (BC_4, DQ41L, observe_only, X), " &
"74 (BC_2, *, internal, X), " &
"73 (BC_4, *, internal, X), " &
"72 (BC_2, DQ40L, output3, X, 68, 0, Z), " &
"71 (BC_4, DQ40L, observe_only, X), " &
"70 (BC_2, *, internal, 0), " &
"69 (BC_4, *, internal, X), " &
"68 (BC_2, *, control, 0), " &
"67 (BC_4, BEn4L, observe_only, X), " &
"66 (BC_2, *, internal, X), " &
"65 (BC_4, *, internal, X), " &
"64 (BC_2, DQ39L, output3, X, 68, 0, Z), " &
"63 (BC_4, DQ39L, observe_only, X), " &
"62 (BC_2, *, internal, X), " &
"61 (BC_4, *, internal, X), " &
"60 (BC_2, DQ38L, output3, X, 68, 0, Z), " &
"59 (BC_4, DQ38L, observe_only, X), " &
"58 (BC_2, *, internal, X), " &
"57 (BC_4, *, internal, X), " &
"56 (BC_2, DQ37L, output3, X, 68, 0, Z), " &
"55 (BC_4, DQ37L, observe_only, X), " &
"54 (BC_2, *, internal, X), " &
"53 (BC_4, *, internal, X), " &
"52 (BC_2, DQ36L, output3, X, 68, 0, Z), " &
"51 (BC_4, DQ36L, observe_only, X), " &
"50 (BC_2, *, internal, X), " &
"49 (BC_2, *, internal, X), " &
"48 (BC_2, *, internal, X), " &
"47 (BC_2, DQ36R, output3, X, 29, 0, Z), " &
"46 (BC_4, DQ36R, observe_only, X), " &
"45 (BC_2, *, internal, X), " &
"44 (BC_4, *, internal, X), " &
"43 (BC_2, DQ37R, output3, X, 29, 0, Z), " &
"42 (BC_4, DQ37R, observe_only, X), " &
"41 (BC_2, *, internal, X), " &
"40 (BC_4, *, internal, X), " &
"39 (BC_2, DQ38R, output3, X, 29, 0, Z), " &
"38 (BC_4, DQ38R, observe_only, X), " &
"37 (BC_2, *, internal, X), " &
"36 (BC_4, *, internal, X), " &
"35 (BC_2, DQ39R, output3, X, 29, 0, Z), " &
"34 (BC_4, DQ39R, observe_only, X), " &
"33 (BC_2, *, internal, X), " &
"32 (BC_4, *, internal, X), " &
"31 (BC_2, *, internal, 0), " &
"30 (BC_4, *, internal, X), " &
"29 (BC_2, *, control, 0), " &
"28 (BC_4, BEn4R, observe_only, X), " &
"27 (BC_2, DQ40R, output3, X, 29, 0, Z), " &
"26 (BC_4, DQ40R, observe_only, X), " &
"25 (BC_2, *, internal, X), " &
"24 (BC_4, *, internal, X), " &
"23 (BC_2, DQ41R, output3, X, 29, 0, Z), " &
"22 (BC_4, DQ41R, observe_only, X), " &
"21 (BC_2, *, internal, X), " &
"20 (BC_4, *, internal, X), " &
"19 (BC_2, DQ42R, output3, X, 29, 0, Z), " &
"18 (BC_4, DQ42R, observe_only, X), " &
"17 (BC_2, *, internal, X), " &
"16 (BC_4, *, internal, X), " &
"15 (BC_2, DQ43R, output3, X, 29, 0, Z), " &
"14 (BC_4, DQ43R, observe_only, X), " &
"13 (BC_2, *, internal, X), " &
"12 (BC_4, *, internal, X), " &
"11 (BC_2, DQ44R, output3, X, 29, 0, Z), " &
"10 (BC_4, DQ44R, observe_only, X), " &
"9 (BC_2, *, internal, X), " &
"8 (BC_4, *, internal, X), " &
"7 (BC_4, *, internal, X), " &
"6 (BC_4, *, internal, X), " &
"5 (BC_4, *, internal, X), " &
"4 (BC_4, *, internal, X), " &
"3 (BC_4, *, internal, X), " &
"2 (BC_4, *, internal, X), " &
"1 (BC_4, *, internal, X), " &
"0 (BC_4, *, internal, X) ";
end CYD36S72V18;