---------------------------------------------------------------------------
-- This model was created at IDT's ATLANTA DESIGN CENTER
-- Part: IDT72T55248 (Demultiplexer 1M)
-- Ver: 0.1 Created by: SSB Date: 4/14/03
-- Customization created on: Mon Apr 14 15:01:07 2003
-- Application Note:
-- In HSTL mode (IOSEL=1), PDB=0 blocks the HSTL mode inputs
-- internally. Consequently, for correct JTAG operation,
-- PDB must be set to 1. Since the same vectors are used
-- for HSTL and LVTTL modes, this means that PDB must be
-- set to 1 when using JTAG in LVTTL mode as well.
---------------------------------------------------------------------------
entity IDT72T55248 is
-- Generic parameter
generic (PHYSICAL_PIN_MAP: string := "BB324");
-- Logical port description
port (
CEFBCORB : out bit;
CFFBCIRB : out bit;
D : in bit_vector(0 to 39);
EFBORB : out bit_vector(0 to 3);
ERCLK0 : out bit;
ERCLK1 : out bit;
ERCLK2 : out bit;
ERCLK3 : out bit;
ERENB0 : out bit;
ERENB1 : out bit;
ERENB2 : out bit;
ERENB3 : out bit;
FFBIRB : out bit_vector(0 to 3);
FSEL : in bit_vector(0 to 1);
FWFTSI : in bit;
GND : linkage bit_vector(0 to 77);
IOSEL : linkage bit;
IS0 : in bit;
IS1 : in bit;
IW : in bit_vector(0 to 1);
MD0 : linkage bit;
MD1 : linkage bit;
MRSB : in bit;
OEB0 : in bit;
OEB1 : in bit;
OEB2 : in bit;
OEB3 : in bit;
OS0 : in bit;
OS1 : in bit;
OW : in bit_vector(0 to 1);
PAEB : out bit_vector(0 to 3);
PAFB : out bit_vector(0 to 3);
PDB : linkage bit;
PFM : in bit;
PRSB : in bit_vector(0 to 3);
Q : out bit_vector(0 to 39);
RCLK0 : in bit;
RCLK1 : in bit;
RCLK2 : in bit;
RCLK3 : in bit;
RCSB0 : in bit;
RCSB1 : in bit;
RCSB2 : in bit;
RCSB3 : in bit;
RDDR : in bit;
RENB0 : in bit;
RENB1 : in bit;
RENB2 : in bit;
RENB3 : in bit;
SCLK : in bit;
SDO : out bit;
SRENB : in bit;
SWENB : in bit;
TCK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
TRSTB : in bit;
VCC : linkage bit_vector(0 to 39);
VDDQ : linkage bit_vector(0 to 38);
VREF : linkage bit;
WCLK0 : in bit;
WCLK1 : in bit;
WCLK2 : in bit;
WCLK3 : in bit;
WCSB0 : in bit;
WCSB1 : in bit;
WCSB2 : in bit;
WCSB3 : in bit;
WDDR : in bit;
WENB0 : in bit;
WENB1 : in bit;
WENB2 : in bit;
WENB3 : in bit
);
-- Standard
use STD_1149_1_1994.all;
-- Component conformance
attribute COMPONENT_CONFORMANCE of IDT72T55248: entity is "STD_1149_1_1993";
-- Device package pin mappings
attribute PIN_MAP of IDT72T55248: entity is PHYSICAL_PIN_MAP;
-- Pin-port map for package BB324
constant BB324: PIN_MAP_STRING :=
"CEFBCORB: U6, " &
"CFFBCIRB: T6, " &
"D : (A1, A2, A3, B1, B2, B3, C1, C2, C3, " &
"C4, D1, D2, D3, E1, E2, E3, F2, F3, " &
"G2, G3, H2, H3, J2, J3, K3, K2, K1, " &
"L3, L2, L1, M3, M2, M1, N3, N2, N1, " &
"P3, P2, P1, R3), " &
"EFBORB : (V4, U5, U7, V10), " &
"ERCLK0 : R18, " &
"ERCLK1 : T18, " &
"ERCLK2 : U18, " &
"ERCLK3 : V18, " &
"ERENB0 : J17, " &
"ERENB1 : J16, " &
"ERENB2 : K16, " &
"ERENB3 : K17, " &
"FFBIRB : (T4, V6, T10, U11), " &
"FSEL : (B6, C5), " &
"FWFTSI : B16, " &
"GND : (A10, B10, C10, D10, E10, F6, F7, F8, F9, " &
"F10, F11, F12, F13, G6, G7, G8, G9, G10, " &
"G11, G12, G13, H6, H7, H8, H9, H10, H11, " &
"H12, H13, J6, J7, J8, J9, J10, J11, J12, " &
"J13, K6, K7, K8, K9, K10, K11, K12, K13, " &
"L6, L7, L8, L9, L10, L11, L12, L13, M6, " &
"M7, M8, M9, M10, M11, M12, M13, N6, N7, " &
"N8, N9, N10, N11, N12, N13, P9, P10, R9, " &
"R10, T9, U9, V9, D7, D8" &
"), " &
"IOSEL : D5, " &
"IS0 : V2, " &
"IS1 : V1, " &
"IW : (C8, C12), " &
"MD0 : B4, " &
"MD1 : B5, " &
"MRSB : A5, " &
"OEB0 : A13, " &
"OEB1 : A14, " &
"OEB2 : A15, " &
"OEB3 : A16, " &
"OS0 : T12, " &
"OS1 : V11, " &
"OW : (C6, B8), " &
"PAEB : (V3, V5, V7, U10), " &
"PAFB : (U4, T5, T7, T11), " &
"PDB : B12, " &
"PFM : D4, " &
"PRSB : (A6, A7, A8, A12), " &
"Q : (A17, A18, B18, C18, D18, D17, D16, E18, E17, E16, " &
"F18, F17, F16, G18, G17, G16, H18, H17, H16, J18, " &
"K18, L16, L17, L18, M16, M17, M18, N16, N17, N18, " &
"P16, P17, P18, R16, R17, T15, T16, T17, U16, U17), " &
"RCLK0 : V17, " &
"RCLK1 : V16, " &
"RCLK2 : V15, " &
"RCLK3 : V14, " &
"RCSB0 : U13, " &
"RCSB1 : T13, " &
"RCSB2 : V12, " &
"RCSB3 : U12, " &
"RDDR : B7, " &
"RENB0 : U15, " &
"RENB1 : U14, " &
"RENB2 : T14, " &
"RENB3 : V13, " &
"SCLK : B14, " &
"SDO : C17, " &
"SRENB : B15, " &
"SWENB : C16, " &
"TCK : C13, " &
"TDI : B13, " &
"TDO : B17, " &
"TMS : C14, " &
"TRSTB : C15, " &
"VCC : (C9, D9, E5, E6, E7, E8, E9, F4, F5, G4, " &
"G5, H4, H5, J4, J5, K4, K5, L4, L5, M4, " &
"M5, N4, N5, P4, P5, P6, P7, P8, R4, R5, " &
"R6, R7, R8, T8, U8, V8, A9, D6, B9" &
", E4), " &
"VDDQ : (A11, B11, C11, D11, D12, D13, D14, D15, E11, E12, " &
"E13, E14, E15, F14, F15, G14, G15, H14, H15, J14, " &
"J15, K14, K15, L14, L15, M14, M15, N14, N15, P11, " &
"P12, P13, P14, P15, R11, R12, R13, R14, R15), " &
"VREF : A4, " &
"WCLK0 : F1, " &
"WCLK1 : G1, " &
"WCLK2 : H1, " &
"WCLK3 : J1, " &
"WCSB0 : U1, " &
"WCSB1 : U2, " &
"WCSB2 : U3, " &
"WCSB3 : T1, " &
"WDDR : C7, " &
"WENB0 : T2, " &
"WENB1 : T3, " &
"WENB2 : R1, " &
"WENB3 : R2";
-- Scan port identification
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTB : signal is true;
-- Instruction register description
attribute INSTRUCTION_LENGTH of IDT72T55248: entity is 4;
attribute INSTRUCTION_OPCODE of IDT72T55248: entity is
"SAMPLE (0001)," &
"EXTEST (0000)," &
"IDCODE (0010)," &
"HIGHZ (0100)," &
"CLAMP (0011)," &
"BYPASS (1111)," &
"PRIVATE (0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110)";
attribute INSTRUCTION_CAPTURE of IDT72T55248: entity is "0101";
attribute INSTRUCTION_PRIVATE of IDT72T55248: entity is "PRIVATE";
-- Optional register description
attribute IDCODE_REGISTER of IDT72T55248: entity is
"0000" & -- version
"0000010011001001" & -- part number
"00000110011" & -- manufacturer's identity
"1"; -- required by 1149.1
-- Register access description
attribute REGISTER_ACCESS of IDT72T55248: entity is
"BYPASS (BYPASS, HIGHZ, CLAMP), " &
"BOUNDARY (SAMPLE, EXTEST), " &
"DEVICE_ID (IDCODE)";
-- Boundary-Scan register description
attribute BOUNDARY_LENGTH of IDT72T55248: entity is 182;
attribute BOUNDARY_REGISTER of IDT72T55248: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"0 (BC_1, Q(0), output3, X, 6, 0, Z), " &
"1 (BC_1, Q(1), output3, X, 6, 0, Z), " &
"2 (BC_1, Q(2), output3, X, 6, 0, Z), " &
"3 (BC_1, Q(3), output3, X, 6, 0, Z), " &
"4 (BC_1, Q(4), output3, X, 6, 0, Z), " &
"5 (BC_1, Q(5), output3, X, 6, 0, Z), " &
"6 (BC_1, *, control, 0 ), " &
"7 (BC_1, Q(6), output3, X, 6, 0, Z), " &
"8 (BC_1, Q(7), output3, X, 6, 0, Z), " &
"9 (BC_1, Q(8), output3, X, 6, 0, Z), " &
"10 (BC_1, Q(9), output3, X, 6, 0, Z), " &
"11 (BC_1, Q(10), output3, X, 17, 0, Z), " &
"12 (BC_1, Q(11), output3, X, 17, 0, Z), " &
"13 (BC_1, Q(12), output3, X, 17, 0, Z), " &
"14 (BC_1, Q(13), output3, X, 17, 0, Z), " &
"15 (BC_1, Q(14), output3, X, 17, 0, Z), " &
"16 (BC_1, Q(15), output3, X, 17, 0, Z), " &
"17 (BC_1, *, control, 0 ), " &
"18 (BC_1, Q(16), output3, X, 17, 0, Z), " &
"19 (BC_1, Q(17), output3, X, 17, 0, Z), " &
"20 (BC_1, Q(18), output3, X, 17, 0, Z), " &
"21 (BC_1, Q(19), output3, X, 17, 0, Z), " &
"22 (BC_1, *, control, 0 ), " &
"23 (BC_1, ERENB0, output3, X, 22, 0, Z), " &
"24 (BC_1, ERENB1, output3, X, 22, 0, Z), " &
"25 (BC_1, ERENB2, output3, X, 22, 0, Z), " &
"26 (BC_1, ERENB3, output3, X, 22, 0, Z), " &
"27 (BC_1, Q(20), output3, X, 33, 0, Z), " &
"28 (BC_1, Q(21), output3, X, 33, 0, Z), " &
"29 (BC_1, Q(22), output3, X, 33, 0, Z), " &
"30 (BC_1, Q(23), output3, X, 33, 0, Z), " &
"31 (BC_1, Q(24), output3, X, 33, 0, Z), " &
"32 (BC_1, Q(25), output3, X, 33, 0, Z), " &
"33 (BC_1, *, control, 0 ), " &
"34 (BC_1, Q(26), output3, X, 33, 0, Z), " &
"35 (BC_1, Q(27), output3, X, 33, 0, Z), " &
"36 (BC_1, Q(28), output3, X, 33, 0, Z), " &
"37 (BC_1, Q(29), output3, X, 33, 0, Z), " &
"38 (BC_1, Q(30), output3, X, 44, 0, Z), " &
"39 (BC_1, Q(31), output3, X, 44, 0, Z), " &
"40 (BC_1, Q(32), output3, X, 44, 0, Z), " &
"41 (BC_1, Q(33), output3, X, 44, 0, Z), " &
"42 (BC_1, Q(34), output3, X, 44, 0, Z), " &
"43 (BC_1, Q(35), output3, X, 44, 0, Z), " &
"44 (BC_1, *, control, 0 ), " &
"45 (BC_1, Q(36), output3, X, 44, 0, Z), " &
"46 (BC_1, Q(37), output3, X, 44, 0, Z), " &
"47 (BC_1, Q(38), output3, X, 44, 0, Z), " &
"48 (BC_1, Q(39), output3, X, 44, 0, Z), " &
"49 (BC_1, *, control, 0 ), " &
"50 (BC_1, ERCLK0, output3, X, 49, 0, Z), " &
"51 (BC_1, ERCLK1, output3, X, 49, 0, Z), " &
"52 (BC_1, ERCLK2, output3, X, 49, 0, Z), " &
"53 (BC_1, ERCLK3, output3, X, 49, 0, Z), " &
"54 (BC_4, OS1, input, X ), " &
"55 (BC_4, OS0, input, X ), " &
"56 (BC_4, RCSB3, input, X ), " &
"57 (BC_4, RCSB2, input, X ), " &
"58 (BC_4, RCSB1, input, X ), " &
"59 (BC_4, RCSB0, input, X ), " &
"60 (BC_4, RCLK3, clock, X ), " &
"61 (BC_4, RCLK2, clock, X ), " &
"62 (BC_4, RCLK1, clock, X ), " &
"63 (BC_4, RCLK0, clock, X ), " &
"64 (BC_4, RENB3, input, X ), " &
"65 (BC_4, RENB2, input, X ), " &
"66 (BC_4, RENB1, input, X ), " &
"67 (BC_4, RENB0, input, X ), " &
"68 (BC_1, *, control, 0 ), " &
"69 (BC_1, CFFBCIRB, output3, X, 68, 0, Z), " &
"70 (BC_1, *, control, 0 ), " &
"71 (BC_1, FFBIRB(3), output3, X, 70, 0, Z), " &
"72 (BC_1, PAFB(3), output3, X, 70, 0, Z), " &
"73 (BC_1, PAEB(3), output3, X, 70, 0, Z), " &
"74 (BC_1, EFBORB(3), output3, X, 70, 0, Z), " &
"75 (BC_1, *, control, 0 ), " &
"76 (BC_1, FFBIRB(2), output3, X, 75, 0, Z), " &
"77 (BC_1, PAFB(2), output3, X, 75, 0, Z), " &
"78 (BC_1, PAEB(2), output3, X, 75, 0, Z), " &
"79 (BC_1, EFBORB(2), output3, X, 75, 0, Z), " &
"80 (BC_1, *, control, 0 ), " &
"81 (BC_1, CEFBCORB, output3, X, 80, 0, Z), " &
"82 (BC_1, *, control, 0 ), " &
"83 (BC_1, FFBIRB(1), output3, X, 82, 0, Z), " &
"84 (BC_1, PAFB(1), output3, X, 82, 0, Z), " &
"85 (BC_1, PAEB(1), output3, X, 82, 0, Z), " &
"86 (BC_1, EFBORB(1), output3, X, 82, 0, Z), " &
"87 (BC_1, *, control, 0 ), " &
"88 (BC_1, FFBIRB(0), output3, X, 87, 0, Z), " &
"89 (BC_1, PAFB(0), output3, X, 87, 0, Z), " &
"90 (BC_1, PAEB(0), output3, X, 87, 0, Z), " &
"91 (BC_1, EFBORB(0), output3, X, 87, 0, Z), " &
"92 (BC_4, IS1, input, X ), " &
"93 (BC_4, IS0, input, X ), " &
"94 (BC_4, WCSB3, input, X ), " &
"95 (BC_4, WCSB2, input, X ), " &
"96 (BC_4, WCSB1, input, X ), " &
"97 (BC_4, WCSB0, input, X ), " &
"98 (BC_4, WCLK3, clock, X ), " &
"99 (BC_4, WCLK2, clock, X ), " &
"100 (BC_4, WCLK1, clock, X ), " &
"101 (BC_4, WCLK0, clock, X ), " &
"102 (BC_4, WENB3, input, X ), " &
"103 (BC_4, WENB2, input, X ), " &
"104 (BC_4, WENB1, input, X ), " &
"105 (BC_4, WENB0, input, X ), " &
"106 (BC_4, D(39), input, X ), " &
"107 (BC_4, D(38), input, X ), " &
"108 (BC_4, D(37), input, X ), " &
"109 (BC_4, D(36), input, X ), " &
"110 (BC_4, D(35), input, X ), " &
"111 (BC_4, D(34), input, X ), " &
"112 (BC_4, D(33), input, X ), " &
"113 (BC_4, D(32), input, X ), " &
"114 (BC_4, D(31), input, X ), " &
"115 (BC_4, D(30), input, X ), " &
"116 (BC_4, D(29), input, X ), " &
"117 (BC_4, D(28), input, X ), " &
"118 (BC_4, D(27), input, X ), " &
"119 (BC_4, D(26), input, X ), " &
"120 (BC_4, D(25), input, X ), " &
"121 (BC_4, D(24), input, X ), " &
"122 (BC_4, D(23), input, X ), " &
"123 (BC_4, D(22), input, X ), " &
"124 (BC_4, D(21), input, X ), " &
"125 (BC_4, D(20), input, X ), " &
"126 (BC_4, D(19), input, X ), " &
"127 (BC_4, D(18), input, X ), " &
"128 (BC_4, D(17), input, X ), " &
"129 (BC_4, D(16), input, X ), " &
"130 (BC_4, D(15), input, X ), " &
"131 (BC_4, D(14), input, X ), " &
"132 (BC_4, D(13), input, X ), " &
"133 (BC_4, D(12), input, X ), " &
"134 (BC_4, D(11), input, X ), " &
"135 (BC_4, D(10), input, X ), " &
"136 (BC_4, D(9), input, X ), " &
"137 (BC_4, D(8), input, X ), " &
"138 (BC_4, D(7), input, X ), " &
"139 (BC_4, D(6), input, X ), " &
"140 (BC_4, D(5), input, X ), " &
"141 (BC_4, D(4), input, X ), " &
"142 (BC_4, D(3), input, X ), " &
"143 (BC_4, D(2), input, X ), " &
"144 (BC_4, D(1), input, X ), " &
"145 (BC_4, D(0), input, X ), " &
"146 (BC_4, *, internal, X ), " &
"147 (BC_4, *, internal, X ), " &
"148 (BC_4, *, internal, X ), " &
-- Bit 149 of the scan chain monitors IOSEL, pin D5
"149 (BC_4, *, internal, X ), " &
-- Bit 150 of the scan chain monitors MD0, pin B4
"150 (BC_4, *, internal, X ), " &
-- Bit 151 of the scan chain monitors MD1, pin B5
"151 (BC_4, *, internal, X ), " &
"152 (BC_4, PFM, input, X ), " &
"153 (BC_4, FSEL(0), input, X ), " &
"154 (BC_4, FSEL(1), input, X ), " &
"155 (BC_4, RDDR, input, X ), " &
"156 (BC_4, OW(0), input, X ), " &
"157 (BC_4, OW(1), input, X ), " &
"158 (BC_4, WDDR, input, X ), " &
"159 (BC_4, IW(0), input, X ), " &
"160 (BC_4, IW(1), input, X ), " &
"161 (BC_4, *, internal, X ), " &
"162 (BC_4, *, internal, X ), " &
"163 (BC_4, *, internal, X ), " &
"164 (BC_4, *, internal, X ), " &
"165 (BC_4, *, internal, X ), " &
"166 (BC_4, FWFTSI, input, X ), " &
"167 (BC_4, MRSB, input, X ), " &
"168 (BC_4, PRSB(0), input, X ), " &
"169 (BC_4, PRSB(1), input, X ), " &
"170 (BC_4, PRSB(2), input, X ), " &
"171 (BC_4, PRSB(3), input, X ), " &
-- Bit 172 of the scan chain monitors PDB, pin B12
"172 (BC_4, *, internal, X ), " &
"173 (BC_1, *, control, 0 ), " &
"174 (BC_1, SDO, output3, X, 173, 0, Z), " &
"175 (BC_4, SCLK, input, X ), " &
"176 (BC_4, SRENB, input, X ), " &
"177 (BC_4, SWENB, input, X ), " &
"178 (BC_4, OEB0, input, X ), " &
"179 (BC_4, OEB1, input, X ), " &
"180 (BC_4, OEB2, input, X ), " &
"181 (BC_4, OEB3, input, X )";
end IDT72T55248;