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BSDL File: CS61583 Download View details  


						 
---------------------------------------------------------------------
-- CS61583-IQ (64 pin tqfp) BSDL File IEEE STD 1149.1 Sept 1990
---------------------------------------------------------------------
entity CS61583 is
        generic (PHYSICAL_PIN_MAP: string := "TQFP_64");

        -- Port Declarations
	-- Note that the "bidirectional" pins in the CS61583
	-- are not all truly bidirectional and must be configured as 
	-- either inputs or outputs - see datasheet
		-- PORT DESCRIPTION TERMS
		-- in      = input only
		-- out     = three-state output 
		-- inout   = bidirectional
		-- linkage = power, ground, analog)
		-- bit     = single pin
		-- bit_vector = group of pins 0 to n

        port(rloop2 :in bit;
               ami2 :in bit;
               los2 :out bit;
          tneg2_ais2:inout bit;
        tpos2_tdata2:in bit;
               tclk2:in bit;
          rneg2_bpv2:out bit;
          rpos2_rdata2:out bit;
               rclk2:out bit;
                ami1:in bit;
               con22:in bit;
               con21:in bit;
               con12:in bit;
               con11:in bit;
               con02:in bit;
               con01:in bit;
               taos2:in bit;
               taos1:in bit;
              lloop2:in bit;
              lloop1:in bit;
              rloop1:in bit;
              atten1:in bit;
               rclk1:out bit;
        rpos1_rdata1:out bit;
          rneg1_bpv1:out bit;
               tclk1:in bit;
        tpos1_tdata1:in bit;
          tneg1_ais1:inout bit;
                los1:out bit;
       	      coder1:in bit;
	      coder2:in bit;
                 tck:in bit;
                 tms:in bit;
                 tdi:in bit;
                 tdo:out bit;
                 vcc:linkage bit_vector(1 to 6);
                 gnd:linkage bit_vector(1 to 9);
              analog:linkage bit_vector(1 to 12);
		 clke:linkage bit;
	      atten0:linkage bit);
        use STD_1149_1_1990.all;
        attribute PIN_MAP of CS61583 : entity is PHYSICAL_PIN_MAP;

        -- Physical Pin Mapping

        constant TQFP_64 : PIN_MAP_STRING :=
                "rloop2:27,ami2:41,los2:42,tneg2_ais2:43,"&
                "tpos2_tdata2:44,tclk2:45,rneg2_bpv2:46,rpos2_rdata2:47,"&
                "rclk2:48,ami1:49,con22:50,con21:51,"&
                "con12:52,con11:53,con02:54,con01:58,"&
                "taos2:59,taos1:60,lloop2:61,lloop1:62,"&
                "rloop1:63,atten1:64,rclk1:1,rpos1_rdata1:2,"&
                "rneg1_bpv1:3,tclk1:4,tpos1_tdata1:5,tneg1_ais1:6,"&
                "los1:7,coder1:15,coder2:34,tck:40,tms:39,tdi:10,tdo:8,"&
                "vcc:(12,19,24,30,37,56),"&
                "gnd:(9,13,20,21,23,29,36,55,57),"&
                "analog:(11,14,17,18,22,25,26,28,31,32,35,38)"&
		"clke:33,atten0:16;

        -- Compulsory signal Attribute Declarations

        attribute TAP_SCAN_IN    of tdi  : signal is true;
        attribute TAP_SCAN_OUT   of tdo  : signal is true;
        attribute TAP_SCAN_MODE  of tms  : signal is true;
        attribute TAP_SCAN_CLOCK of tck  : signal is (4.0e6,LOW);

        attribute INSTRUCTION_LENGTH of CS61583: entity is 2;
        attribute INSTRUCTION_OPCODE of CS61583: entity is
                "BYPASS (11),"&
                "EXTEST (00),"&
                "SAMPLE (01)";

-- IDCODE_REGISTER & IDCODE instruction commented out.
-- ID register in CS61583 does not comply with IEEE 1149.1. When IDCODE
instruction is
-- active, the ID register is connected to TDO, but not TDI. This will allow
-- the device to output its own ID code but it will not pass data from
-- upstream devices in this mode.  A workaround is possible by issuing a
BYPASS
-- instruction to the CS61583 before reading the ID codes of the other
devices.
-- The IDCODE instruction may then be used to read the CS61583 information
while
-- the other devices are in BYPASS mode
 
--              "SAMPLE (01),"&
--              "IDCODE (10)";


        attribute INSTRUCTION_CAPTURE of CS61583: entity is
                "01";

--      attribute IDCODE_REGISTER of CS61583: entity is
--              "0000" &
--              "0000000000000011" &
--              "00001100100" &
--              "1";
--
        attribute REGISTER_ACCESS of CS61583:entity is
                "BOUNDARY (SAMPLE, EXTEST), " &
                "BYPASS   (BYPASS)";

--              "BYPASS   (BYPASS), " &
--              "IDCODE   (IDCODE) ";


        attribute BOUNDARY_CELLS of CS61583: entity is "BC_1";
        attribute BOUNDARY_LENGTH of CS61583: entity is 67;
        attribute BOUNDARY_REGISTER of CS61583: entity is



-- PORT DESCRIPTION TERMS
-- cell type: BC_1
-- port: port name 
-- input    = input only
-- bidir    = bidirectional
-- control = control cell
-- output3  = three state output
-- safe = value in control cell to make input = 0 for bidir and control
-- ccell = controlling cell number for I/O direction
-- dsval = disabling (input) value
-- rslt  = result if disabled (input = Z)

--num  cell    port     function  safe  ccell dsval rslt
"66    (BC_1,  coder1,  input,    X),"&
"65    (BC_1,  rloop2,  input,    X),"&
"64    (BC_1,  coder2,  input,    X),"&
"63    (BC_1,  ami2,    input,    X),"&
"62    (BC_1,  *,       internal, 0),"&
"61    (BC_1,  los2,    output3,  0,   60,    0,    Z),"&
"60    (BC_1,  *,       control,  0),"&
"59    (BC_1,  tneg2_ais2, bidir, 0,	58,	0,	Z),"&
"58    (BC_1,  *,       control, 0),"&
"57    (BC_1,  *,       internal, 0),"&
"56    (BC_1,  tpos2_tdata2,   input,    X),"&
"55    (BC_1,  tclk2,   input,    X),"&
"54    (BC_1,  rneg2_bpv2,   output3,  X,   53,    0,    Z),"&
"53    (BC_1,  *,       control,  0),"&
"52    (BC_1,  rpos2_rdata2,   output3,  X,   51,    0,    Z),"&
"51    (BC_1,  *,       control,  0),"&
"50    (BC_1,  rclk2,   output3,  X,   49,    0,    Z),"&
"49    (BC_1,  *,       control,  0),"&
"48    (BC_1,  *,       internal, 0),"&
"47    (BC_1,  ami1,    input,  X),"&
"46    (BC_1,  *,       internal,  0),"&
"45    (BC_1,  con22,   input,    X),"&
"44    (BC_1,  con21,   input,    X),"&
"43    (BC_1,  *,       internal, 0),"&
"42    (BC_1,  *,       internal, 0),"&
"41    (BC_1,  con12,   input,    X),"&
"40    (BC_1,  *,       internal, 0),"&
"39    (BC_1,  *,       internal, 0),"&
"38    (BC_1,  con11,   input,    X),"&
"37    (BC_1,  *,       internal, 0),"&
"36    (BC_1,  *,       internal, 0),"&
"35    (BC_1,  con02,   input,    X),"&
"34    (BC_1,  *,       internal, 0),"&
"33    (BC_1,  *,       internal, 0),"&
"32    (BC_1,  con01,   input,    X),"&
"31    (BC_1,  *,       internal, 0),"&
"30    (BC_1,  *,       internal, 0),"&
"29    (BC_1,  taos2,   input,    X),"&
"28    (BC_1,  *,       internal, 0),"&
"27    (BC_1,  *,       internal, 0),"&
"26    (BC_1,  taos1,   input,    X),"&
"25    (BC_1,  *,       internal, 0),"&
"24    (BC_1,  *,       internal, 0),"&
"23    (BC_1,  lloop2,  input,    X),"&
"22    (BC_1,  *,       internal, 0),"&
"21    (BC_1,  *,       internal, 0),"&
"20    (BC_1,  lloop1,  input,    X),"&
"19    (BC_1,  rloop1,  input,    X),"&
"18    (BC_1,  *,       internal, 0),"&
"17    (BC_1,  *,       internal, 0),"&
"16    (BC_1,  *,       internal, 0),"&
"15    (BC_1,  atten1,  input,  X),"&
"14    (BC_1,  *,       internal,  0),"&
"13    (BC_1,  rclk1,   output3,  X,   12,    0,    Z),"&
"12    (BC_1,  *,       control,  0),"&
"11    (BC_1,  rpos1_rdata1,   output3,  X,   10,    0,    Z),"&
"10    (BC_1,  *,       control,  0),"&
"9     (BC_1,  rneg1_bpv1,   output3,  X,    8,    0,    Z),"&
"8     (BC_1,  *,       control,  0),"&
"7     (BC_1,  tclk1,   input,    X),"&
"6     (BC_1,  tpos1_tdata1,   input,    X),"&
"5     (BC_1,  tneg1_ais1,   bidir,    0,	4,	0,	Z),"&
"4     (BC_1,  *,       control, 0),"&
"3     (BC_1,  *,       internal, 0),"&
"2     (BC_1,  *,       internal, 0),"&
"1     (BC_1,  los1,    output3,  X,    0,    0,    Z),"&
"0     (BC_1,  *,       control,  0)";
end CS61583;

--
-- End of Definition File
--

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Last BSDL model (chip) was added on Oct 17, 2017 16:06
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