-- royalty by users of the AMD Elan (Am386sc300) processor.
-- Advanced Micro Devices makes no warranty for the use of its
-- products and assumes no responsibility for any errors which may
-- appear in this file nor does it make a commitment to update the
-- information contained herein.
--
-- Note: all of the following is the BSDL entity description for Elan.
-- Do not change the order in which the elements of this file appear.
-- This file pertains to the rev B Elan, 208-pin PQFP.
--
-- Written by AMD MCD/EPD, Austin, Texas, USA.
--
-- Revision 1.0, 07/10/95
---wej-------------------------------------------------------------------------
--Revised 01/18/99 by Brian Henning
-- Changed order of vectors so that they followed standard order of
-- LSB -> MSB
-- Vectors that were changed are D, MA, and SA
-------------------------------------------------------------------------------
entity am386sc300 is
generic (PHYSICAL_PIN_MAP : string := "PQFP_208");
port (D:inout bit_vector (0 to 15); MA:out bit_vector (0 to 10);
DSMA0:out bit; DSMA1:inout bit; DSMA:out bit_vector (2 to 14);
DSMD:inout bit_vector (0 to 7);
PMC:out bit_vector (0 to 4); PGP:inout bit_vector (0 to 3);
SA:out bit_vector (0 to 12); RC:in bit; A20GATE:in bit;
AFDT:out bit; PE:in bit; STRB:out bit; SLCTIN:out bit;
BUSY:in bit; ERROR:in bit; SLCT:in bit; ACK:in bit;
INIT:out bit; PPDWE:inout bit; PPOEN:inout bit; DTR:inout bit;
RTS:inout bit; SOUT:inout bit; CTS:in bit; DSR:in bit;
DCD:in bit; SIN:in bit; RIN:in bit; ACIN:in bit;
EXTSMI:in bit; SUSRES:in bit; BL1:in bit; BL2:in bit;
BL3:in bit; BL4:in bit; CD_A:in bit; RDY_A:in bit;
WP_A:in bit; BVD2_A:in bit; BVD1_A:in bit;
WAIT_AB:in bit; CD_B:in bit; RDY_B:in bit; WP_B:in bit;
BVD2_B:in bit; BVD1_B:in bit; ICDIR:out bit;
MCEL_B:out bit; MCEH_B:out bit; VPP_B:out bit; REG_B:out bit;
RST_B:out bit; MCEL_A:out bit; MCEH_A:out bit; VPP_A:out bit;
REG_A:out bit; RST_A:out bit; CA24:out bit; CA25:out bit;
SPKR:out bit; IORESET:in bit; RESIN:in bit; SBHE:out bit;
DI_R:out bit; LVDD:out bit; DSCE:out bit; DSOE:out bit;
M:inout bit; DO_I:inout bit; D2_G:inout bit; D3_B:inout bit;
CP1_HDRV:inout bit; CP2_VDO:inout bit; FRMVDRV:inout bit;
LVEE:inout bit; DSWE:inout bit; LPH:out bit; IOCHRDY:in bit;
PIRQ_1:in bit; PIRQ_0:in bit; IRQ1:in bit;
IOCS16:inout bit; MCS16:inout bit; IRQ14:inout bit; CLK14_O:out bit;
RAS0:out bit; RAS1:out bit; CAS1L:out bit; CAS1H:out bit;
CAS0L:out bit; CAS0H:out bit; MWE:out bit; DOSCS:out bit;
DROMCS:out bit; SYSCLK:inout bit; ENDIRL:out bit; ENDIRH:out bit;
IOR:out bit; IOW:out bit; MEMR:out bit; MEMW:out bit;
RSTDRV:out bit;
DBUFOE:out bit; CS8042:inout bit;
GND:linkage bit_vector(0 to 12);
VCC:linkage bit_vector(0 to 3);
TDO:out bit; TMS, TDI, TCK:in bit);
use STD_1149_1_1990.all; -- Get Std 1149.1-1990 attributes and definitions
attribute PIN_MAP of am386sc300 : entity is PHYSICAL_PIN_MAP;
constant PQFP_208: PIN_MAP_STRING:="RC:78, A20GATE:79, AFDT:80," &
"DSMD:(148,166,167,168,169,170,171,172)," &
"D:(42,41,40,39,38,37,36,34,32,31,30,29,28,27,26,25)," &
"MA:(24,21,19,18,17,16,15,14,13,11,10)," &
"DSMA0:165, DSMA1:164," &
"DSMA:(163,162,161,160,159,158,155,154,153,152,151,150,149)," &
"PMC:(137,138,77,185,184), PGP:(189,188,187,186)," &
"SA:(74,73,72,71,70,69,67,66,64,63,62,61,60)," &
"PE:82, STRB:83, SLCTIN:84," &
"BUSY:85, ERROR:86, SLCT:87, ACK:88, INIT:89, PPDWE:90," &
"PPOEN:91, DTR:92, RTS:93, SOUT:94, CTS:96, DSR:97," &
"DCD:98, SIN:99, RIN:100, ACIN:101, EXTSMI:102, SUSRES:103," &
"BL1:106, BL2:107, BL3:108, BL4:109, CD_A:110, RDY_A:111," &
"WP_A:112, BVD2_A:113, BVD1_A:114, WAIT_AB:115, CD_B:116," &
"RDY_B:117, WP_B:118, BVD2_B:119, BVD1_B:120, ICDIR:122," &
"MCEL_B:123, MCEH_B:124, VPP_B:125, REG_B:126, RST_B:127," &
"MCEL_A:129, MCEH_A:130, VPP_A:131, REG_A:132, RST_A:133," &
"CA24:134, CA25:136, SPKR:139, IORESET:140, RESIN:141, SBHE:143," &
"DI_R:144, LVDD:145, DSCE:146, DSOE:147, M:173, DO_I:174, D2_G:175," &
"D3_B:177, CP1_HDRV:178, CP2_VDO:179, FRMVDRV:181, LVEE:182, DSWE:183," &
"LPH:190, IOCHRDY:192, PIRQ_1:193, PIRQ_0:194, IRQ1:195, IOCS16:196," &
"MCS16:197, IRQ14:198, CLK14_O:200, RAS0:2, RAS1:3, CAS1L:4," &
"CAS1H:5, CAS0L:6, CAS0H:7, MWE:8, DOSCS:43, DROMCS:44," &
"SYSCLK:45, ENDIRL:50, ENDIRH:51, IOR:54, IOW:55, MEMR:56," &
"MEMW:57, RSTDRV:58, DBUFOE:59, CS8042:75, VCC:(23,81,135,180)," &
"GND:(1,12,33,52,53,68,104,105,121,156,157,191,208)," &
"TDO:76, TMS:49, TCK:46, TDI:47";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of am386sc300 : entity is 4;
attribute INSTRUCTION_OPCODE of am386sc300 : entity is
"BYPASS (1111)," &
"EXTEST (0000)," &
"SAMPLE (0001)," &
"IDCODE (0010)";
attribute INSTRUCTION_CAPTURE of am386sc300 : entity is "0001";
attribute IDCODE_REGISTER of am386sc300 : entity is
"0001" & -- Version
"1001010111111010" & -- Part number
"00000000001" & -- Manufacturer Identity
"1"; -- Mandatory LSB
-- i.d. = 195FA003
attribute BOUNDARY_CELLS of am386sc300 : entity is "BC_1, BC_6";
attribute BOUNDARY_LENGTH of am386sc300 : entity is 173;
attribute BOUNDARY_REGISTER of am386sc300 : entity is
-- num cell port function safe [ccell disval rslt]
"172 (BC_1, PMC(2), output3, X, 20, 1, Z)," &
"171 (BC_1, RC, input, X)," &
"170 (BC_1, A20GATE, input, X)," &
"169 (BC_1, AFDT, output3, X, 20, 1, Z)," &
"168 (BC_1, PE, input, X)," &
"167 (BC_1, STRB, output3, X, 20, 1, Z)," &
"166 (BC_1, SLCTIN, output3, X, 20, 1, Z)," &
"165 (BC_1, BUSY, input, X)," &
"164 (BC_1, ERROR, input, X)," &
"163 (BC_1, SLCT, input, X)," &
"162 (BC_1, ACK, input, X)," &
"161 (BC_1, INIT, output3, X, 20, 1, Z)," &
"160 (BC_6, PPDWE, bidir, X, 20, 1, Z)," &
"159 (BC_6, PPOEN, bidir, X, 20, 1, Z)," &
"158 (BC_6, DTR, bidir, X, 20, 1, Z)," &
"157 (BC_6, RTS, bidir, X, 20, 1, Z)," &
"156 (BC_6, SOUT, bidir, X, 20, 1, Z)," &
"155 (BC_1, CTS, input, X)," &
"154 (BC_1, DSR, input, X)," &
"153 (BC_1, DCD, input, X)," &
"152 (BC_1, SIN, input, X)," &
"151 (BC_1, RIN, input, X)," &
"150 (BC_1, ACIN, input, X)," &
"149 (BC_1, EXTSMI, input, X)," &
"148 (BC_1, SUSRES, input, X)," &
"147 (BC_1, *, control, 1)," &
"146 (BC_1, BL1, input, X)," &
"145 (BC_1, BL2, input, X)," &
"144 (BC_1, BL3, input, X)," &
"143 (BC_1, BL4, input, X)," &
"142 (BC_1, CD_A, input, X)," &
"141 (BC_1, RDY_A, input, X)," &
"140 (BC_1, WP_A, input, X)," &
"139 (BC_1, BVD2_A, input, X)," &
"138 (BC_1, BVD1_A, input, X)," &
"137 (BC_1, WAIT_AB, input, X)," &
"136 (BC_1, CD_B, input, X)," &
"135 (BC_1, RDY_B, input, X)," &
"134 (BC_1, WP_B, input, X)," &
"133 (BC_1, BVD2_B, input, X)," &
"132 (BC_1, BVD1_B, input, X)," &
"131 (BC_1, ICDIR, output3, X, 147, 1, Z)," &
"130 (BC_1, MCEL_B, output3, X, 147, 1, Z)," &
"129 (BC_1, MCEH_B, output3, X, 147, 1, Z)," &
"128 (BC_1, VPP_B, output3, X, 147, 1, Z)," &
"127 (BC_1, REG_B, output3, X, 147, 1, Z)," &
"126 (BC_1, RST_B, output3, X, 147, 1, Z)," &
"125 (BC_1, MCEL_A, output3, X, 147, 1, Z)," &
"124 (BC_1, MCEH_A, output3, X, 147, 1, Z)," &
"123 (BC_1, VPP_A, output3, X, 147, 1, Z)," &
"122 (BC_1, REG_A, output3, X, 147, 1, Z)," &
"121 (BC_1, RST_A, output3, X, 147, 1, Z)," &
"120 (BC_1, CA24, output3, X, 147, 1, Z)," &
"119 (BC_1, CA25, output3, X, 147, 1, Z)," &
"118 (BC_1, PMC(0), output3, X, 147, 1, Z)," &
"117 (BC_1, PMC(1), output3, X, 147, 1, Z)," &
"116 (BC_1, SPKR, output3, X, 147, 1, Z)," &
"115 (BC_1, IORESET, input, X)," &
"114 (BC_1, RESIN, input, X)," &
"113 (BC_1, SBHE, output3, X, 147, 1, Z)," &
"112 (BC_1, DI_R, output3, X, 147, 1, Z)," &
"111 (BC_1, LVDD, output3, X, 147, 1, Z)," &
"110 (BC_1, DSCE, output3, X, 147, 1, Z)," &
"109 (BC_1, DSOE, output3, X, 147, 1, Z)," &
"108 (BC_6, DSMD(0), bidir, X, 147, 1, Z)," &
"107 (BC_1, DSMA(14), output3, X, 147, 1, Z)," &
"106 (BC_1, DSMA(13), output3, X, 147, 1, Z)," &
"105 (BC_1, DSMA(12), output3, X, 147, 1, Z)," &
"104 (BC_1, DSMA(11), output3, X, 147, 1, Z)," &
"103 (BC_1, DSMA(10), output3, X, 147, 1, Z)," &
"102 (BC_1, DSMA(9), output3, X, 147, 1, Z)," &
"101 (BC_1, DSMA(8), output3, X, 147, 1, Z)," &
"100 (BC_1, *, control, 1)," &
"99 (BC_1, DSMA(7), output3, X, 100, 1, Z)," &
"98 (BC_1, DSMA(6), output3, X, 100, 1, Z)," &
"97 (BC_1, DSMA(5), output3, X, 100, 1, Z)," &
"96 (BC_1, DSMA(4), output3, X, 100, 1, Z)," &
"95 (BC_1, DSMA(3), output3, X, 100, 1, Z)," &
"94 (BC_1, DSMA(2), output3, X, 100, 1, Z)," &
"93 (BC_6, DSMA1, bidir, X, 100, 1, Z)," &
"92 (BC_1, DSMA0, output3, X, 100, 1, Z)," &
"91 (BC_6, DSMD(1), bidir, X, 100, 1, Z)," &
"90 (BC_6, DSMD(2), bidir, X, 100, 1, Z)," &
"89 (BC_6, DSMD(3), bidir, X, 100, 1, Z)," &
"88 (BC_6, DSMD(4), bidir, X, 100, 1, Z)," &
"87 (BC_6, DSMD(5), bidir, X, 100, 1, Z)," &
"86 (BC_6, DSMD(6), bidir, X, 100, 1, Z)," &
"85 (BC_6, DSMD(7), bidir, X, 100, 1, Z)," &
"84 (BC_6, M, bidir, X, 100, 1, Z)," &
"83 (BC_6, DO_I, bidir, X, 100, 1, Z)," &
"82 (BC_6, D2_G, bidir, X, 100, 1, Z)," &
"81 (BC_6, D3_B, bidir, X, 100, 1, Z)," &
"80 (BC_6, CP1_HDRV, bidir, X, 100, 1, Z)," &
"79 (BC_6, CP2_VDO, bidir, X, 100, 1, Z)," &
"78 (BC_6, FRMVDRV, bidir, X, 100, 1, Z)," &
"77 (BC_6, LVEE, bidir, X, 100, 1, Z)," &
"76 (BC_6, DSWE, bidir, X, 100, 1, Z)," &
"75 (BC_1, PMC(4), output3, X, 100, 1, Z)," &
"74 (BC_1, PMC(3), output3, X, 100, 1, Z)," &
"73 (BC_6, PGP(3), bidir, X, 100, 1, Z)," &
"72 (BC_6, PGP(2), bidir, X, 100, 1, Z)," &
"71 (BC_6, PGP(1), bidir, X, 100, 1, Z)," &
"70 (BC_6, PGP(0), bidir, X, 100, 1, Z)," &
"69 (BC_1, LPH, output3, X, 100, 1, Z)," &
"68 (BC_1, IOCHRDY, input, X)," &
"67 (BC_1, PIRQ_1, input, X)," &
"66 (BC_1, PIRQ_0, input, X)," &
"65 (BC_1, IRQ1, input, X)," &
"64 (BC_6, IOCS16, bidir, X, 100, 1, Z)," &
"63 (BC_6, MCS16, bidir, X, 100, 1, Z)," &
"62 (BC_6, IRQ14, bidir, X, 100, 1, Z)," &
"61 (BC_1, CLK14_O, output3, X, 100, 1, Z)," &
"60 (BC_1, *, control, 1)," &
"59 (BC_1, RAS0, output3, X, 60, 1, Z)," &
"58 (BC_1, RAS1, output3, X, 60, 1, Z)," &
"57 (BC_1, CAS1L, output3, X, 60, 1, Z)," &
"56 (BC_1, CAS1H, output3, X, 60, 1, Z)," &
"55 (BC_1, CAS0L, output3, X, 60, 1, Z)," &
"54 (BC_1, CAS0H, output3, X, 60, 1, Z)," &
"53 (BC_1, MWE, output3, X, 60, 1, Z)," &
"52 (BC_1, MA(10), output3, X, 60, 1, Z)," &
"51 (BC_1, MA(9), output3, X, 60, 1, Z)," &
"50 (BC_1, MA(8), output3, X, 60, 1, Z)," &
"49 (BC_1, MA(7), output3, X, 60, 1, Z)," &
"48 (BC_1, MA(6), output3, X, 60, 1, Z)," &
"47 (BC_1, MA(5), output3, X, 60, 1, Z)," &
"46 (BC_1, MA(4), output3, X, 60, 1, Z)," &
"45 (BC_1, MA(3), output3, X, 60, 1, Z)," &
"44 (BC_1, MA(2), output3, X, 60, 1, Z)," &
"43 (BC_1, MA(1), output3, X, 60, 1, Z)," &
"42 (BC_1, MA(0), output3, X, 60, 1, Z)," &
"41 (BC_6, D(15), bidir, X, 60, 1, Z)," &
"40 (BC_6, D(14), bidir, X, 60, 1, Z)," &
"39 (BC_6, D(13), bidir, X, 60, 1, Z)," &
"38 (BC_6, D(12), bidir, X, 60, 1, Z)," &
"37 (BC_6, D(11), bidir, X, 60, 1, Z)," &
"36 (BC_6, D(10), bidir, X, 60, 1, Z)," &
"35 (BC_6, D(9), bidir, X, 60, 1, Z)," &
"34 (BC_6, D(8), bidir, X, 60, 1, Z)," &
"33 (BC_6, D(7), bidir, X, 60, 1, Z)," &
"32 (BC_6, D(6), bidir, X, 60, 1, Z)," &
"31 (BC_6, D(5), bidir, X, 60, 1, Z)," &
"30 (BC_6, D(4), bidir, X, 60, 1, Z)," &
"29 (BC_6, D(3), bidir, X, 60, 1, Z)," &
"28 (BC_6, D(2), bidir, X, 60, 1, Z)," &
"27 (BC_6, D(1), bidir, X, 60, 1, Z)," &
"26 (BC_6, D(0), bidir, X, 60, 1, Z)," &
"25 (BC_1, DOSCS, output3, X, 60, 1, Z)," &
"24 (BC_1, DROMCS, output3, X, 60, 1, Z)," &
"23 (BC_6, SYSCLK, bidir, X, 60, 1, Z)," &
"22 (BC_1, ENDIRL, output3, X, 60, 1, Z)," &
"21 (BC_1, ENDIRH, output3, X, 60, 1, Z)," &
"20 (BC_1, *, control, 1)," &
"19 (BC_1, IOR, output3, X, 20, 1, Z)," &
"18 (BC_1, IOW, output3, X, 20, 1, Z)," &
"17 (BC_1, MEMR, output3, X, 20, 1, Z)," &
"16 (BC_1, MEMW, output3, X, 20, 1, Z)," &
"15 (BC_1, RSTDRV, output3, X, 20, 1, Z)," &
"14 (BC_1, DBUFOE, output3, X, 20, 1, Z)," &
"13 (BC_1, SA(12), output3, X, 20, 1, Z)," &
"12 (BC_1, SA(11), output3, X, 20, 1, Z)," &
"11 (BC_1, SA(10), output3, X, 20, 1, Z)," &
"10 (BC_1, SA(9), output3, X, 20, 1, Z)," &
"9 (BC_1, SA(8), output3, X, 20, 1, Z)," &
"8 (BC_1, SA(7), output3, X, 20, 1, Z)," &
"7 (BC_1, SA(6), output3, X, 20, 1, Z)," &
"6 (BC_1, SA(5), output3, X, 20, 1, Z)," &
"5 (BC_1, SA(4), output3, X, 20, 1, Z)," &
"4 (BC_1, SA(3), output3, X, 20, 1, Z)," &
"3 (BC_1, SA(2), output3, X, 20, 1, Z)," &
"2 (BC_1, SA(1), output3, X, 20, 1, Z)," &
"1 (BC_1, SA(0), output3, X, 20, 1, Z)," &
"0 (BC_6, CS8042, bidir, X, 20, 1, Z) " ;
end am386sc300;