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BSDL File: F791775 Download View details  


----------------------------------------------------------------------
--  DRA78x Boundary Scan  
----------------------------------------------------------------------
--  Supported Devices: DRA78x Revision 1.0                 --
----------------------------------------------------------------------
--  Created by    : Texas Instruments Incorporated                  --
--  BSDL Revision : 1.0 originally created                          --
--                                                                  --
--  BSDL Status   : Preliminary                                     --
--  Date Created  : 27 December 2013
--                                                                  --
----------------------------------------------------------------------
--                                                                  --
--                          IMPORTANT NOTICE
--  Texas Instruments Incorporated (TI) reserves the right to make
--  changes to its products or to discontinue any semiconductor
--  product or service without notice, and advises its customers to
--  obtain the latest version of the relevant information to
--  verify, before placing orders, that the information being
--  relied on is current.
--  TI warrants performance of its semiconductor products and
--  related software to the specifications applicable at the time
--  of sale in accordance with TI's standard warranty. Testing and
--  other quality control techniques are utilized to the extent TI
--  deems necessary to support this warranty. Specific testing of
--  all parameters of each device is not necessarily performed,
--  except those mandated by government requirements.
--
--  Certain applications using semiconductor devices may involve
--  potential risks of death, personal injury, or severe property
--  or environmental damage ("Critical Applications").
--    TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
--    AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
--    LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
--    CRITICAL APPLICATIONS.
--  Inclusion of TI products in such applications is understood
--  to be fully at the risk of the customer.  Use of TI products
--  in such applications requires the written approval of an
--  appropriate TI officer. Questions concerning potential risk
--  applications should be directed to TI through a local SC sales
--  office.
--  In order to minimize risks associated with the customer's
--  applications, adequate design and operating safeguards should
--  be provided by the
--  customer to minimize inherent or procedural hazards.

--  TI assumes no liability for applications assistance, customer
--  product design, software performance, or infringement of
--  patents or services described herein.  Nor does TI warrant or
--  represent that any license, either express or implied, is
--  granted under any patent right, copyright, mask work right, or
--  other intellectual property right of TI covering or relating
--  to any combination, machine, or process in which such
--  semiconductor products or services might be or are used.
--            Copyright (c) 2001, Texas Instruments Incorporated
-------------------------------------------------------------------


entity F791775 is

generic(PHYSICAL_PIN_MAP : string := "ABF");

   port( 
		dcan1_rx				:	inout bit;
		dcan1_tx				:	inout bit;
		dcan2_rx				:	inout bit;
		dcan2_tx				:	inout bit;
		ddr1_a0				    	:	inout bit;
		ddr1_a1				    	:	inout bit;
		ddr1_a10				:	inout bit;
		ddr1_a11				:	inout bit;
		ddr1_a12				:	inout bit;
		ddr1_a13				:	inout bit;
		ddr1_a14				:	inout bit;
		ddr1_a15				:	inout bit;
		ddr1_a2				    	:	inout bit;
		ddr1_a3				    	:	inout bit;
		ddr1_a4				    	:	inout bit;
		ddr1_a5				    	:	inout bit;
		ddr1_a6				    	:	inout bit;
		ddr1_a7				    	:	inout bit;
		ddr1_a8				    	:	inout bit;
		ddr1_a9				    	:	inout bit;
		ddr1_ba0				:	inout bit;
		ddr1_ba1				:	inout bit;
		ddr1_ba2				:	inout bit;
		ddr1_casn				:	inout bit;
		ddr1_ck			    		:	inout bit;
		ddr1_cke0				:	out bit;
		ddr1_csn0				:	inout bit;
		ddr1_d0				    	:	inout bit;
		ddr1_d1				    	:	inout bit;
		ddr1_d10				:	inout bit;
		ddr1_d11				:	inout bit;
		ddr1_d12				:	inout bit;
		ddr1_d13				:	inout bit;
		ddr1_d14				:	inout bit;
		ddr1_d15				:	inout bit;
		ddr1_d16				:	inout bit;
		ddr1_d17				:	inout bit;
		ddr1_d18				:	inout bit;
		ddr1_d19				:	inout bit;
		ddr1_d2				    	:	inout bit;
		ddr1_d20				:	inout bit;
		ddr1_d21				:	inout bit;
		ddr1_d22				:	inout bit;
		ddr1_d23				:	inout bit;
		ddr1_d24				:	inout bit;
		ddr1_d25				:	inout bit;
		ddr1_d26				:	inout bit;
		ddr1_d27				:	inout bit;
		ddr1_d28				:	inout bit;
		ddr1_d29				:	inout bit;
		ddr1_d3			    		:	inout bit;
		ddr1_d30				:	inout bit;
		ddr1_d31				:	inout bit;
		ddr1_d4				    	:	inout bit;
		ddr1_d5				    	:	inout bit;
		ddr1_d6				    	:	inout bit;
		ddr1_d7				    	:	inout bit;
		ddr1_d8				    	:	inout bit;
		ddr1_d9				    	:	inout bit;
		ddr1_dqm0				:	inout bit;
		ddr1_dqm1				:	inout bit;
		ddr1_dqm2				:	inout bit;
		ddr1_dqm3				:	inout bit;
		ddr1_dqm_ecc				:	inout bit;
		ddr1_dqs0				:	inout bit;
		ddr1_dqs1				:	inout bit;
		ddr1_dqs2				:	inout bit;
		ddr1_dqs3				:	inout bit;
		ddr1_dqs_ecc				:	inout bit;
		ddr1_dqsn0				:	inout bit;
		ddr1_dqsn1				:	inout bit;
		ddr1_dqsn2				:	inout bit;
		ddr1_dqsn3				:	inout bit;
		ddr1_dqsn_ecc				:	inout bit;
		ddr1_ecc_d0				:	inout bit;
		ddr1_ecc_d1				:	inout bit;
		ddr1_ecc_d2				:	inout bit;
		ddr1_ecc_d3				:	inout bit;
		ddr1_ecc_d4				:	inout bit;
		ddr1_ecc_d5				:	inout bit;
		ddr1_ecc_d6				:	inout bit;
		ddr1_ecc_d7				:	inout bit;
		ddr1_nck				:	inout bit;
		ddr1_odt0				:	inout bit;
		ddr1_rasn				:	inout bit;
		ddr1_rst				:	inout bit;
		ddr1_wen				:	inout bit;
		emu0				    	:	inout bit;
		emu1				    	:	inout bit;
		gpmc_ad0				:	inout bit;
		gpmc_ad1				:	inout bit;
		gpmc_ad10				:	inout bit;
		gpmc_ad11				:	inout bit;
		gpmc_ad12				:	inout bit;
		gpmc_ad13				:	inout bit;
		gpmc_ad14				:	inout bit;
		gpmc_ad15				:	inout bit;
		gpmc_ad2				:	inout bit;
		gpmc_ad3				:	inout bit;
		gpmc_ad4				:	inout bit;
		gpmc_ad5				:	inout bit;
		gpmc_ad6				:	inout bit;
		gpmc_ad7				:	inout bit;
		gpmc_ad8				:	inout bit;
		gpmc_ad9				:	inout bit;
		gpmc_advn_ale				:	inout bit;
		gpmc_ben0				:	inout bit;
		gpmc_ben1				:	inout bit;
		gpmc_clk				:	inout bit;
		gpmc_cs0				:	inout bit;
		gpmc_cs1				:	inout bit;
		gpmc_cs2				:	inout bit;
		gpmc_cs3				:	inout bit;
		gpmc_cs4				:	inout bit;
		gpmc_cs5				:	inout bit;
		gpmc_cs6				:	inout bit;
		gpmc_oen_ren				:	inout bit;
		gpmc_wait0				:	inout bit;
		gpmc_wen				:	inout bit;
		i2c1_scl				:	inout bit;
		i2c1_sda				:	inout bit;
		i2c2_scl				:	inout bit;
		i2c2_sda				:	inout bit;
		mdio_d				    	:	inout bit;
		mdio_mclk				:	inout bit;
		nmin				    	:	inout bit;
		porz				    	:	in bit;
		resetn				    	:	inout bit;
		rgmii0_rxc				:	inout bit;
		rgmii0_rxctl				:	inout bit;
		rgmii0_rxd0				:	inout bit;
		rgmii0_rxd1				:	inout bit;
		rgmii0_rxd2				:	inout bit;
		rgmii0_rxd3				:	inout bit;
		rgmii0_txc				:	inout bit;
		rgmii0_txctl				:	inout bit;
		rgmii0_txd0				:	inout bit;
		rgmii0_txd1				:	inout bit;
		rgmii0_txd2				:	inout bit;
		rgmii0_txd3				:	inout bit;
		rstoutn				    	:	inout bit;
		rtck				    	:	inout bit;
		spi1_cs0				:	inout bit;
		spi1_cs1				:	inout bit;
		spi1_d0				    	:	inout bit;
		spi1_d1				    	:	inout bit;
		spi1_sclk				:	inout bit;
		spi2_cs0				:	inout bit;
		spi2_d0				    	:	inout bit;
		spi2_d1				    	:	inout bit;
		spi2_sclk				:	inout bit;
		tclk				    	:	in bit;
		tdi				        :	in bit;
		tdo				        :	out bit;
		tms				        :	in bit;
		trstn				    	:	in bit;
		uart1_ctsn				:	inout bit;
		uart1_rtsn				:	inout bit;
		uart1_rxd				:	inout bit;
		uart1_txd				:	inout bit;
		uart2_ctsn				:	inout bit;
		uart2_rtsn				:	inout bit;
		uart2_rxd				:	inout bit;
		uart2_txd				:	inout bit;
		vin1a_clk0				:	inout bit;
		vin1a_d0				:	inout bit;
		vin1a_d1				:	inout bit;
		vin1a_d10				:	inout bit;
		vin1a_d11				:	inout bit;
		vin1a_d12				:	inout bit;
		vin1a_d13				:	inout bit;
		vin1a_d14				:	inout bit;
		vin1a_d15				:	inout bit;
		vin1a_d2				:	inout bit;
		vin1a_d3				:	inout bit;
		vin1a_d4				:	inout bit;
		vin1a_d5				:	inout bit;
		vin1a_d6				:	inout bit;
		vin1a_d7				:	inout bit;
		vin1a_d8				:	inout bit;
		vin1a_d9				:	inout bit;
		vin1a_de0				:	inout bit;
		vin1a_fld0				:	inout bit;
		vin1a_hsync0				:	inout bit;
		vin1a_vsync0				:	inout bit;
		vin2a_clk0				:	inout bit;
		vin2a_de0				:	inout bit;
		vin2a_fld0				:	inout bit;
		vout1_clk				:	inout bit;
		vout1_d0				:	inout bit;
		vout1_d1				:	inout bit;
		vout1_d10				:	inout bit;
		vout1_d11				:	inout bit;
		vout1_d12				:	inout bit;
		vout1_d13				:	inout bit;
		vout1_d14				:	inout bit;
		vout1_d15				:	inout bit;
		vout1_d16				:	inout bit;
		vout1_d17				:	inout bit;
		vout1_d18				:	inout bit;
		vout1_d19				:	inout bit;
		vout1_d2				:	inout bit;
		vout1_d20				:	inout bit;
		vout1_d21				:	inout bit;
		vout1_d22				:	inout bit;
		vout1_d23				:	inout bit;
		vout1_d3				:	inout bit;
		vout1_d4				:	inout bit;
		vout1_d5				:	inout bit;
		vout1_d6				:	inout bit;
		vout1_d7				:	inout bit;
		vout1_d8				:	inout bit;
		vout1_d9				:	inout bit;
		vout1_de				:	inout bit;
		vout1_fld				:	inout bit;
		vout1_hsync				:	inout bit;
		vout1_vsync				:	inout bit;
		xref_clk0	            		:   	inout bit;	
		
		iforce				    	:	linkage bit;
		atestv				    	:	linkage bit;
		vsense				    	:	linkage bit;
		xi_osc0				    	:	linkage bit;
		xi_osc1				    	:	linkage bit;
		xo_osc0				    	:	linkage bit;
		xo_osc1				    	:	linkage bit;
		adc_in0				    	:	linkage bit;
		adc_in1				    	:	linkage bit;
		adc_in2				    	:	linkage bit;
		adc_in3				    	:	linkage bit;
		adc_in4				    	:	linkage bit;
		adc_in5				    	:	linkage bit;
		adc_in6				    	:	linkage bit;
		adc_in7				    	:	linkage bit;
		cvideo_rset				:	linkage bit;
		cvideo_tvout				:	linkage bit;
		cvideo_vfb				:	linkage bit;
		csi2_0_dx4				:	linkage bit;
		csi2_0_dx3				:	linkage bit;
		csi2_0_dx2				:	linkage bit;
		csi2_0_dx1				:	linkage bit;
		csi2_0_dx0				:	linkage bit;
		csi2_0_dy4				:	linkage bit;
		csi2_0_dy3				:	linkage bit;
		csi2_0_dy2				:	linkage bit;
		csi2_0_dy1				:	linkage bit;
		csi2_0_dy0				:	linkage bit;

		adc_vrefp				:	linkage bit;
		cap_vddram_core1			:	linkage bit;
		cap_vddram_core2			:	linkage bit;
		cap_vddram_dspeve			:	linkage bit;
		vdd					:	linkage bit_vector(12 downto 0);
		vdd_dspeve				:	linkage bit_vector(6 downto 0);
		vdda_adc				:	linkage bit;
		vdda_csi				:	linkage bit;
		vdda_dac				:	linkage bit;
		vdda_ddr_dsp				:	linkage bit;
		vdda_gmac_core				:	linkage bit;
		vdda_osc				:	linkage bit;
		vdda_per				:	linkage bit;
		vdds_ddr1				:	linkage bit_vector(4 downto 0);
		vdds_ddr2				:	linkage bit_vector(2 downto 0);
		vdds_ddr3				:	linkage bit_vector(2 downto 0);
		vdds18v					:	linkage bit_vector(4 downto 0);
		vdds18v_ddr1				:	linkage bit_vector(1 downto 0);
		vdds18v_ddr2				:	linkage bit;
		vdds18v_ddr3				:	linkage bit_vector(1 downto 0);
		vddshv1					:	linkage bit_vector(3 downto 0);
		vddshv2					:	linkage bit_vector(3 downto 0);
		vddshv3					:	linkage bit;
		vddshv4					:	linkage bit_vector(1 downto 0);
		vddshv5					:	linkage bit_vector(2 downto 0);
		vddshv6					:	linkage bit_vector(3 downto 0);
		vpp					:	linkage bit;
		vss					:	linkage bit_vector(44 downto 0);
		vssa_adc				:	linkage bit;
		vssa_csi				:	linkage bit;
		vssa_dac				:	linkage bit;
		vssa_osc0				:	linkage bit;
		vssa_osc1				:	linkage bit
   );



    use STD_1149_1_2001.all; 

    attribute COMPONENT_CONFORMANCE of F791775 : entity is 
"STD_1149_1_2001"; 
    attribute PIN_MAP of F791775 : entity is PHYSICAL_PIN_MAP; 

    constant ABF : PIN_MAP_STRING :=  
	"adc_in0		:	M19,"&
	"adc_in1		:	M20,"&
	"adc_in2		:	M21,"&
	"adc_in3		:	M22,"&
	"adc_in4		:	N22,"&
	"adc_in5		:	N21,"&
	"adc_in6		:	P19,"&
	"adc_in7		:	P18,"&
	"atestv			:	A21,"&
	"csi2_0_dx0		:	A11,"&
	"csi2_0_dx1		:	A12,"&
	"csi2_0_dx2		:	A13,"&
	"csi2_0_dx3		:	A15,"&
	"csi2_0_dx4		:	A16,"&
	"csi2_0_dy0		:	B11,"&
	"csi2_0_dy1		:	B12,"&
	"csi2_0_dy2		:	B13,"&
	"csi2_0_dy3		:	B15,"&
	"csi2_0_dy4		:	B16,"&
	"cvideo_rset		:	T18,"&
	"cvideo_tvout		:	T17,"&
	"cvideo_vfb		:	P17,"&
	"dcan1_rx		:	N6,"&
	"dcan1_tx		:	N5,"&
	"dcan2_rx		:	W6,"&
	"dcan2_tx		:	W7,"&
	"ddr1_a0		:	U4,"&
	"ddr1_a1		:	C1,"&
	"ddr1_a10		:	D1,"&
	"ddr1_a11		:	R3,"&
	"ddr1_a12		:	U2,"&
	"ddr1_a13		:	C3,"&
	"ddr1_a14		:	R2,"&
	"ddr1_a15		:	V1,"&
	"ddr1_a2		:	D3,"&
	"ddr1_a3		:	R4,"&
	"ddr1_a4		:	T4,"&
	"ddr1_a5		:	N3,"&
	"ddr1_a6		:	T2,"&
	"ddr1_a7		:	N2,"&
	"ddr1_a8		:	T1,"&
	"ddr1_a9		:	U1,"&
	"ddr1_ba0		:	B3,"&
	"ddr1_ba1		:	A3,"&
	"ddr1_ba2		:	D2,"&
	"ddr1_casn		:	F2,"&
	"ddr1_ck		:	G1,"&
	"ddr1_cke0		:	F3,"&
	"ddr1_csn0		:	B2,"&
	"ddr1_d0		:	AA6,"&
	"ddr1_d1		:	AA8,"&
	"ddr1_d10		:	AA21,"&
	"ddr1_d11		:	Y22,"&
	"ddr1_d12		:	AA19,"&
	"ddr1_d13		:	AB20,"&
	"ddr1_d14		:	Y17,"&
	"ddr1_d15		:	AB18,"&
	"ddr1_d16		:	AA3,"&
	"ddr1_d17		:	AA2,"&
	"ddr1_d18		:	Y3,"&
	"ddr1_d19		:	V2,"&
	"ddr1_d2		:	Y8,"&
	"ddr1_d20		:	U3,"&
	"ddr1_d21		:	V3,"&
	"ddr1_d22		:	Y2,"&
	"ddr1_d23		:	Y1,"&
	"ddr1_d24		:	U21,"&
	"ddr1_d25		:	T20,"&
	"ddr1_d26		:	R21,"&
	"ddr1_d27		:	U20,"&
	"ddr1_d28		:	R22,"&
	"ddr1_d29		:	V20,"&
	"ddr1_d3		:	AA7,"&
	"ddr1_d30		:	W22,"&
	"ddr1_d31		:	U22,"&
	"ddr1_d4		:	AB4,"&
	"ddr1_d5		:	Y5,"&
	"ddr1_d6		:	AA4,"&
	"ddr1_d7		:	Y6,"&
	"ddr1_d8		:	AA18,"&
	"ddr1_d9		:	Y21,"&
	"ddr1_dqm_ecc		:	AB13,"&
	"ddr1_dqm0		:	AB8,"&
	"ddr1_dqm1		:	Y18,"&
	"ddr1_dqm2		:	AB3,"&
	"ddr1_dqm3		:	W21,"&
	"ddr1_dqs_ecc		:	AA10,"&
	"ddr1_dqs0		:	AA5,"&
	"ddr1_dqs1		:	AA20,"&
	"ddr1_dqs2		:	W1,"&
	"ddr1_dqs3		:	T21,"&
	"ddr1_dqsn_ecc		:	AB10,"&
	"ddr1_dqsn0		:	AB5,"&
	"ddr1_dqsn1		:	Y20,"&
	"ddr1_dqsn2		:	W2,"&
	"ddr1_dqsn3		:	T22,"&
	"ddr1_ecc_d0		:	Y11,"&
	"ddr1_ecc_d1		:	AA12,"&
	"ddr1_ecc_d2		:	AA11,"&
	"ddr1_ecc_d3		:	Y9,"&
	"ddr1_ecc_d4		:	AA13,"&
	"ddr1_ecc_d5		:	AB11,"&
	"ddr1_ecc_d6		:	AA9,"&
	"ddr1_ecc_d7		:	AB9,"&
	"ddr1_nck		:	G2,"&
	"ddr1_odt0		:	P2,"&
	"ddr1_rasn		:	F1,"&
	"ddr1_rst		:	N1,"&
	"ddr1_wen		:	E3,"&
	"emu0			:	H1,"&
	"emu1			:	H2,"&
	"gpmc_ad0		:	E8,"&
	"gpmc_ad1		:	A7,"&
	"gpmc_ad10		:	D6,"&
	"gpmc_ad11		:	C5,"&
	"gpmc_ad12		:	B5,"&
	"gpmc_ad13		:	D7,"&
	"gpmc_ad14		:	B4,"&
	"gpmc_ad15		:	A4,"&
	"gpmc_ad2		:	F8,"&
	"gpmc_ad3		:	B7,"&
	"gpmc_ad4		:	A6,"&
	"gpmc_ad5		:	F7,"&
	"gpmc_ad6		:	E7,"&
	"gpmc_ad7		:	C6,"&
	"gpmc_ad8		:	B6,"&
	"gpmc_ad9		:	A5,"&
	"gpmc_advn_ale		:	F12,"&
	"gpmc_ben0		:	D12,"&
	"gpmc_ben1		:	E12,"&
	"gpmc_clk		:	C12,"&
	"gpmc_cs0		:	C10,"&
	"gpmc_cs1		:	E10,"&
	"gpmc_cs2		:	D10,"&
	"gpmc_cs3		:	A9,"&
	"gpmc_cs4		:	B9,"&
	"gpmc_cs5		:	F10,"&
	"gpmc_cs6		:	C8,"&
	"gpmc_oen_ren		:	A10,"&
	"gpmc_wait0		:	D8,"&
	"gpmc_wen		:	B10,"&
	"i2c1_scl		:	L3,"&
	"i2c1_sda		:	L4,"&
	"i2c2_scl		:	L6,"&
	"i2c2_sda		:	L5,"&
	"iforce			:	A2,"&
	"mdio_d			:	B17,"&
	"mdio_mclk		:	B19,"&
	"nmin			:	G5,"&
	"porz			:	G3,"&
	"resetn			:	G4,"&
	"rgmii0_rxc		:	B18,"&
	"rgmii0_rxctl		:	C18,"&
	"rgmii0_rxd0		:	A20,"&
	"rgmii0_rxd1		:	C20,"&
	"rgmii0_rxd2		:	B20,"&
	"rgmii0_rxd3		:	A19,"&
	"rgmii0_txc		:	C16,"&
	"rgmii0_txctl		:	C17,"&
	"rgmii0_txd0		:	F17,"&
	"rgmii0_txd1		:	E17,"&
	"rgmii0_txd2		:	D16,"&
	"rgmii0_txd3		:	E16,"&
	"rstoutn		:	F4,"&
	"rtck			:	J6,"&
	"spi1_cs0		:	R6,"&
	"spi1_cs1		:	R5,"&
	"spi1_d0		:	T5,"&
	"spi1_d1		:	U6,"&
	"spi1_sclk		:	M2,"&
	"spi2_cs0		:	L2,"&
	"spi2_d0		:	R7,"&
	"spi2_d1		:	N4,"&
	"spi2_sclk		:	L1,"&
	"tclk			:	J2,"&
	"tdi			:	J1,"&
	"tdo			:	J4,"&
	"tms			:	J3,"&
	"trstn			:	J5,"&
	"uart1_ctsn		:	F14,"&
	"uart1_rtsn		:	C14,"&
	"uart1_rxd		:	F13,"&
	"uart1_txd		:	E14,"&
	"uart2_ctsn		:	F15,"&
	"uart2_rtsn		:	F16,"&
	"uart2_rxd		:	D14,"&
	"uart2_txd		:	D15,"&
	"vin1a_clk0		:	F22,"&
	"vin1a_d0		:	G18,"&
	"vin1a_d1		:	G21,"&
	"vin1a_d10		:	K21,"&
	"vin1a_d11		:	K18,"&
	"vin1a_d12		:	K17,"&
	"vin1a_d13		:	K19,"&
	"vin1a_d14		:	K20,"&
	"vin1a_d15		:	L21,"&
	"vin1a_d2		:	G22,"&
	"vin1a_d3		:	H18,"&
	"vin1a_d4		:	H20,"&
	"vin1a_d5		:	H19,"&
	"vin1a_d6		:	H22,"&
	"vin1a_d7		:	H21,"&
	"vin1a_d8		:	J17,"&
	"vin1a_d9		:	K22,"&
	"vin1a_de0		:	F21,"&
	"vin1a_fld0		:	F20,"&
	"vin1a_hsync0		:	F19,"&
	"vin1a_vsync0		:	G19,"&
	"vin2a_clk0		:	L22,"&
	"vin2a_de0		:	M17,"&
	"vin2a_fld0		:	M18,"&
	"vout1_clk		:	AB17,"&
	"vout1_d0		:	W16,"&
	"vout1_d1		:	V16,"&
	"vout1_d10		:	U13,"&
	"vout1_d11		:	V13,"&
	"vout1_d12		:	Y13,"&
	"vout1_d13		:	W13,"&
	"vout1_d14		:	U11,"&
	"vout1_d15		:	V11,"&
	"vout1_d16		:	U9,"&
	"vout1_d17		:	W11,"&
	"vout1_d18		:	V9,"&
	"vout1_d19		:	W9,"&
	"vout1_d2		:	U15,"&
	"vout1_d20		:	U8,"&
	"vout1_d21		:	W8,"&
	"vout1_d22		:	U7,"&
	"vout1_d23		:	V7,"&
	"vout1_d3		:	V15,"&
	"vout1_d4		:	Y15,"&
	"vout1_d5		:	W15,"&
	"vout1_d6		:	AA15,"&
	"vout1_d7		:	AB15,"&
	"vout1_d8		:	AA14,"&
	"vout1_d9		:	AB14,"&
	"vout1_de		:	U17,"&
	"vout1_fld		:	W17,"&
	"vout1_hsync		:	AA17,"&
	"vout1_vsync		:	U16,"&
	"vsense			:	B1,"&
	"xi_osc0		:	E22,"&
	"xi_osc1		:	B21,"&
	"xo_osc0		:	D22,"&
	"xo_osc1		:	C21,"&
	"xref_clk0		:	M1,"&

	"adc_vrefp		:	P20,"&
	"cap_vddram_core1	:	N15,"&
	"cap_vddram_core2	:	M15,"&
	"cap_vddram_dspeve	:	M14,"&
	"vdd			:	(H12,H13,H7,J10,J11,J15,K12,L12,L15,N12,N16,P10,P14),"&
	"vdd_dspeve		:	(K8,L8,M9,P11,P12,P8,P9),"&
	"vdda_adc		:	P22,"&
	"vdda_csi		:	A14,"&
	"vdda_dac		:	U19,"&
	"vdda_ddr_dsp		:	N8,"&
	"vdda_gmac_core		:	M8,"&
	"vdda_osc		:	E21,"&
	"vdda_per		:	H14,"&
	"vdds_ddr1		:	(AA1,AB6,R1,T7,T8),"&
	"vdds_ddr2		:	(C2,E2,G6),"&
	"vdds_ddr3		:	(AA22,AB19,T15),"&
	"vdds18v		:	(G12,J7,L16,P13,T11),"&
	"vdds18v_ddr1		:	(P7,T9),"&
	"vdds18v_ddr2		:	G7,"&
	"vdds18v_ddr3		:	(T16,V21),"&
	"vddshv1		:	(K2,K7,L7,M7),"&
	"vddshv2		:	(B8,G11,G8,G9),"&
	"vddshv3		:	G14,"&
	"vddshv4		:	(A18,E20),"&
	"vddshv5		:	(H17,J16,J21),"&
	"vddshv6		:	(AA16,T10,T12,T13),"&
	"vpp			:	F6,"&
	"vss			:	(A1,A17,A22,A8,AB1,AB12,AB16,AB2,AB21,AB22,AB7,B22,E1,G10,G16,H10,H11,H15,H16,H8,H9,J22,K1,K10,K11,K13,K14,K15,K16,K9,M10,M11,M12,M13,M16,N10,N7,P1,P15,P16,R12,R16,R9,T14,V22),"&
	"vssa_adc		:	P21,"&
	"vssa_csi		:	B14,"&
	"vssa_dac		:	T19,"&
	"vssa_osc0		:	D21,"&
	"vssa_osc1		:	C22";

    attribute TAP_SCAN_IN of tdi      : signal is true; 
    attribute TAP_SCAN_MODE of tms    : signal is true; 
    attribute TAP_SCAN_OUT of tdo     : signal is true; 
    attribute TAP_SCAN_CLOCK of tclk  : signal is (5.00000000e+06, BOTH); 
    attribute TAP_SCAN_RESET of trstn : signal is true; 

    attribute COMPLIANCE_PATTERNS of F791775 : entity is
        "( " &
        "    porz) " &
        "    (1)";

    attribute INSTRUCTION_LENGTH of F791775 : entity is 6; 
    attribute INSTRUCTION_OPCODE of F791775 : entity is 
      "extest (011000),"  & 
      "idcode (000100),"  & 
      "bypass (111111),"  & 
      "sample (011011),"  & 
      "preload (011100),"  &
      "intest (011001), " & 
      "extest_pulse(100100),"	      &
      "extest_train(100101),"	      &
      "ir_opc_bypass_rsv00(000000),"  &
      "ir_opc_bypass_rsv01(000001),"  &
      "ir_opc_router(000010),"        &
      "ir_opc_bypass_rsv02(000011),"  &
      "ir_opc_icepidcode(000101),"    &
      "ir_opc_bypass_rsv03(000110),"  &
      "ir_opc_conpub(000111),"        &
      "ir_opc_chipspinid(001000),"    &
      "ir_opc_condbypass48(001001),"  &
      "ir_opc_condbypass49(001010),"  &
      "ir_opc_condbypass50(001011),"  &
      "ir_opc_condbypass51(001100),"  &
      "ir_opc_condbypass52(001101),"  &
      "ir_opc_condbypass53(001110),"  &
      "ir_opc_condbypass54(001111),"  &
      "ir_opc_condbypass00(010000),"  &
      "ir_opc_condbypass01(010001),"  &
      "ir_opc_condbypass02(010010),"  &
      "ir_opc_condbypass03(010011),"  &
      "ir_opc_condbypass04(010100),"  &
      "ir_opc_condbypass05(010101),"  &
      "ir_opc_condbypass06(010110),"  &
      "ir_opc_condbypass07(010111),"  &
      "ir_opc_condbypass10(011010),"  &
      "ir_opc_condbypass13(011101),"  &
      "ir_opc_condbypass14(011110),"  &
      "ir_opc_condbypass15(011111),"  &
      "ir_opc_condbypass16(100000),"  &
      "ir_opc_condbypass17(100001),"  &
      "ir_opc_condbypass18(100010),"  &
      "ir_opc_condbypass19(100011),"  &
      "ir_opc_condbypass22(100110),"  &
      "ir_opc_condbypass23(100111),"  &
      "ir_opc_condbypass24(101000),"  &
      "ir_opc_condbypass25(101001),"  &
      "ir_opc_condbypass26(101010),"  &
      "ir_opc_condbypass27(101011),"  &
      "ir_opc_condbypass28(101100),"  &
      "ir_opc_condbypass29(101101),"  &
      "ir_opc_condbypass30(101110),"  &
      "ir_opc_condbypass31(101111),"  &
      "ir_opc_condbypass32(110000),"  &
      "ir_opc_condbypass33(110001),"  &
      "ir_opc_condbypass34(110010),"  &
      "ir_opc_condbypass35(110011),"  &
      "ir_opc_condbypass36(110100),"  &
      "ir_opc_condbypass37(110101),"  &
      "ir_opc_condbypass38(110110),"  &
      "ir_opc_condbypass39(110111),"  &
      "ir_opc_condbypass40(111000),"  &
      "ir_opc_condbypass41(111001),"  &
      "ir_opc_condbypass42(111010),"  &
      "ir_opc_condbypass43(111011),"  &
      "ir_opc_condbypass44(111100),"  &
      "ir_opc_condbypass45(111101),"  &
      "ir_opc_condbypass46(111110)" ; 
       

    attribute INSTRUCTION_CAPTURE of F791775 : entity is "000001"; 

    attribute INSTRUCTION_PRIVATE of F791775 : entity is 
                "extest_train,"  &
                "extest_pulse,"  &
                "ir_opc_bypass_rsv00,"  &
                "ir_opc_bypass_rsv01,"  &
                "ir_opc_router,"        &
                "ir_opc_bypass_rsv02,"  &
                "ir_opc_icepidcode,"    &
                "ir_opc_bypass_rsv03,"  &
                "ir_opc_conpub,"        &
                "ir_opc_chipspinid,"    &
                "ir_opc_condbypass48,"  &
                "ir_opc_condbypass49,"  &
                "ir_opc_condbypass50,"  &
                "ir_opc_condbypass51,"  &
                "ir_opc_condbypass52,"  &
                "ir_opc_condbypass53,"  &
                "ir_opc_condbypass54,"  &
                "ir_opc_condbypass00,"  &
                "ir_opc_condbypass01,"  &
                "ir_opc_condbypass02,"  &
                "ir_opc_condbypass03,"  &
                "ir_opc_condbypass04,"  &
                "ir_opc_condbypass05,"  &
                "ir_opc_condbypass06,"  &
                "ir_opc_condbypass07,"  &
                "ir_opc_condbypass10,"  &
                "ir_opc_condbypass13,"  &
                "ir_opc_condbypass14,"  &
                "ir_opc_condbypass15,"  &
                "ir_opc_condbypass16,"  &
                "ir_opc_condbypass17,"  &
                "ir_opc_condbypass18,"  &
                "ir_opc_condbypass19,"  &
                "ir_opc_condbypass22,"  &
                "ir_opc_condbypass23,"  &
                "ir_opc_condbypass24,"  &
                "ir_opc_condbypass25,"  &
                "ir_opc_condbypass26,"  &
                "ir_opc_condbypass27,"  &
                "ir_opc_condbypass28,"  &
                "ir_opc_condbypass29,"  &
                "ir_opc_condbypass30,"  &
                "ir_opc_condbypass31,"  &
                "ir_opc_condbypass32,"  &
                "ir_opc_condbypass33,"  &
                "ir_opc_condbypass34,"  &
                "ir_opc_condbypass35,"  &
                "ir_opc_condbypass36,"  &
                "ir_opc_condbypass37,"  &
                "ir_opc_condbypass38,"  &
                "ir_opc_condbypass39,"  &
                "ir_opc_condbypass40,"  &
                "ir_opc_condbypass41,"  &
                "ir_opc_condbypass42,"  &
                "ir_opc_condbypass43,"  &
                "ir_opc_condbypass44,"  &
                "ir_opc_condbypass45,"  &
                "ir_opc_condbypass46";
  
    attribute INSTRUCTION_CAPTURE of F791775 : entity is "000001"; 

-----------------
-- Device ID Code
-----------------

	attribute IDCODE_REGISTER of F791775 : entity is
	-- version, part number, manufacturer code of ti, lsb
	"0000" &
	"1011100110110010" &
	"00000010111" &
	"1";


    attribute REGISTER_ACCESS of F791775 : entity is 
        "BOUNDARY (extest,sample,preload, intest), " & 
        "BYPASS (bypass)"; 

    attribute BOUNDARY_LENGTH of F791775 : entity is 741;
    attribute BOUNDARY_REGISTER of F791775 : entity is
------------------------------------------------------------------------ 
--     CELL    CELL       PIN            CELL     SAFE  CNTRL DIS  DIS 
--      #      NAME ,     NAME          ,TYPE    ,VALU ,CELL ,ABLE,VAL 
------------------------------------------------------------------------
"0     (bc_1, ddr1_a12, output3,X , 124, 1 , Z)," &
"1     (bc_1, *	,control,1)," &
"2     (bc_1, ddr1_wen, input, X)," &
"3     (bc_1, ddr1_cke0, output3,X , 148, 1 , Z)," &
"4     (bc_1, *	,control,1)," &
"5     (bc_1, ddr1_csn0, input, X)," &
"6     (bc_1, *	, internal, 0)," &
"7     (bc_1, *	, internal, 0)," &
"8     (bc_1, *	, internal, 0)," &
"9     (bc_1, *	, internal, 0)," &
"10    (bc_1, *	, internal, 0)," &
"11    (bc_1, *	, internal, 0)," &
"12    (bc_1, ddr1_nck, output3,X , 13, 1 , Z)," &
"13    (bc_1, *	,control,1)," &
"14    (bc_1, ddr1_nck, input, X)," &
"15    (bc_1, *	, internal, 0)," &
"16    (bc_1, *	, internal, 0)," &
"17    (bc_1, *	, internal, 0)," &
"18    (bc_1, *	, internal, 0)," &
"19    (bc_1, *	, internal, 0)," &
"20    (bc_1, *	, internal, 0)," &
"21    (bc_1, ddr1_ck, output3,X , 22, 1 , Z)," &
"22    (bc_1, *	,control,1)," &
"23    (bc_1, ddr1_ck, input, X)," &
"24    (bc_1, *	, internal, 0)," &
"25    (bc_1, *	, internal, 0)," &
"26    (bc_1, *	, internal, 0)," &
"27    (bc_1, *	, internal, 0)," &
"28    (bc_1, *	, internal, 0)," &
"29    (bc_1, *	, internal, 0)," &
"30    (bc_1, *	, internal, 0)," &
"31    (bc_1, *	, internal, 0)," &
"32    (bc_1, *	, internal, 0)," &
"33    (bc_1, *	, internal, 0)," &
"34    (bc_1, *	, internal, 0)," &
"35    (bc_1, *	, internal, 0)," &
"36    (bc_1, *	, internal, 0)," &
"37    (bc_1, *	, internal, 0)," &
"38    (bc_1, *	, internal, 0)," &
"39    (bc_1, *	, internal, 0)," &
"40    (bc_1, *	, internal, 0)," &
"41    (bc_1, *	, internal, 0)," &
"42    (bc_1, *	, internal, 0)," &
"43    (bc_1, *	, internal, 0)," &
"44    (bc_1, *	, internal, 0)," &
"45    (bc_1, *	, internal, 0)," &
"46    (bc_1, *	, internal, 0)," &
"47    (bc_1, *	, internal, 0)," &
"48    (bc_1, *	, internal, 0)," &
"49    (bc_1, *	, internal, 0)," &
"50    (bc_1, *	, internal, 0)," &
"51    (bc_1, *	, internal, 0)," &
"52    (bc_1, *	, internal, 0)," &
"53    (bc_1, *	, internal, 0)," &
"54    (bc_1, *	, internal, 0)," &
"55    (bc_1, *	, internal, 0)," &
"56    (bc_1, *	, internal, 0)," &
"57    (bc_1, *	, internal, 0)," &
"58    (bc_1, *	, internal, 0)," &
"59    (bc_1, *	, internal, 0)," &
"60    (bc_1, *	, internal, 0)," &
"61    (bc_1, *	, internal, 0)," &
"62    (bc_1, *	, internal, 0)," &
"63    (bc_1, *	, internal, 0)," &
"64    (bc_1, *	, internal, 0)," &
"65    (bc_1, *	, internal, 0)," &
"66    (bc_1, *	, internal, 0)," &
"67    (bc_1, *	, internal, 0)," &
"68    (bc_1, *	, internal, 0)," &
"69    (bc_1, *	, internal, 0)," &
"70    (bc_1, *	, internal, 0)," &
"71    (bc_1, *	, internal, 0)," &
"72    (bc_1, *	, internal, 0)," &
"73    (bc_1, *	, internal, 0)," &
"74    (bc_1, *	, internal, 0)," &
"75    (bc_1, *	, internal, 0)," &
"76    (bc_1, *	, internal, 0)," &
"77    (bc_1, *	, internal, 0)," &
"78    (bc_1, ddr1_a15, output3,X , 112, 1 , Z)," &
"79    (bc_1, *	, internal, 0)," &
"80    (bc_1, *	, internal, 0)," &
"81    (bc_1, ddr1_a14, output3,X , 115, 1 , Z)," &
"82    (bc_1, *	,control,1)," &
"83    (bc_1, ddr1_odt0, input, X)," &
"84    (bc_1, *	, internal, 0)," &
"85    (bc_1, *	, internal, 0)," &
"86    (bc_1, *	, internal, 0)," &
"87    (bc_1, ddr1_a11, output3,X , 127, 1 , Z)," &
"88    (bc_1, *	,control,1)," &
"89    (bc_1, ddr1_rst, input, X)," &
"90    (bc_1, ddr1_a9, output3,X , 133, 1 , Z)," &
"91    (bc_1, *	,control,1)," &
"92    (bc_1, ddr1_rasn, input, X)," &
"93    (bc_1, ddr1_a8, output3,X , 136, 1 , Z)," &
"94    (bc_1, *	,control,1)," &
"95    (bc_1, ddr1_casn, input, X)," &
"96    (bc_1, ddr1_a7, output3,X , 139, 1 , Z)," &
"97    (bc_1, *	, internal, 0)," &
"98    (bc_1, * , internal, 0)," &
"99    (bc_1, ddr1_a6, output3,X , 142, 1 , Z)," &
"100   (bc_1, *	, internal, 0)," &
"101   (bc_1, *	, internal, 0)," &
"102   (bc_1, ddr1_a5, output3,X , 151, 1 , Z)," &
"103   (bc_1, *	,control,1)," &
"104   (bc_1, ddr1_ba2, input, X)," &
"105   (bc_1, ddr1_a4, output3,X , 154, 1 , Z)," &
"106   (bc_1, *	,control,1)," &
"107   (bc_1, ddr1_ba1, input, X)," &
"108   (bc_1, ddr1_a3, output3,X , 157, 1 , Z)," &
"109   (bc_1, *	,control,1)," &
"110   (bc_1, ddr1_ba0, input, X)," &
"111   (bc_1, ddr1_a0, output3,X , 166, 1 , Z)," &
"112   (bc_1, *	,control,1)," &
"113   (bc_1, ddr1_a15, input, X)," &
"114   (bc_1, ddr1_rst, output3,X , 88, 1 , Z)," &
"115   (bc_1, *	,control,1)," &
"116   (bc_1, ddr1_a14, input, X)," &
"117   (bc_1, ddr1_odt0, output3,X , 82, 1 , Z)," &
"118   (bc_1, *	,control,1)," &
"119   (bc_1, ddr1_a13, input, X)," &
"120   (bc_1, *	, internal, 0)," &
"121   (bc_1, *	, internal, 0)," &
"122   (bc_1, *	, internal, 0)," &
"123   (bc_1, *	, internal, 0)," &
"124   (bc_1, *	,control,1)," &
"125   (bc_1, ddr1_a12, input, X)," &
"126   (bc_1, ddr1_ba0, output3,X , 109, 1 , Z)," &
"127   (bc_1, *	,control,1)," &
"128   (bc_1, ddr1_a11, input, X)," &
"129   (bc_1, ddr1_ba1, output3,X , 106, 1 , Z)," &
"130   (bc_1, *	,control,1)," &
"131   (bc_1, ddr1_a10, input, X)," &
"132   (bc_1, ddr1_a2, output3,X , 160, 1 , Z)," &
"133   (bc_1, *	,control,1)," &
"134   (bc_1, ddr1_a9, input, X)," &
"135   (bc_1, ddr1_ba2, output3,X , 103, 1 , Z)," &
"136   (bc_1, *	,control,1)," &
"137   (bc_1, ddr1_a8, input, X)," &
"138   (bc_1, ddr1_a1, output3,X , 163, 1 , Z)," &
"139   (bc_1, *	,control,1)," &
"140   (bc_1, ddr1_a7, input, X)," &
"141   (bc_1, ddr1_csn0, output3,X , 4, 1 , Z)," &
"142   (bc_1, *	,control,1)," &
"143   (bc_1, ddr1_a6, input, X)," &
"144   (bc_1, *	, internal, 0)," &
"145   (bc_1, *	, internal, 0)," &
"146   (bc_1, * , internal, 0)," &
"147   (bc_1, * , internal, 0)," &
"148   (bc_1, *	,control,1)," &
"149   (bc_1, * ,  internal, 0)," &
"150   (bc_1, ddr1_casn, output3,X , 94, 1 , Z)," &
"151   (bc_1, *	,control,1)," &
"152   (bc_1, ddr1_a5, input, X)," &
"153   (bc_1, * , internal, 0)," &
"154   (bc_1, *	,control,1)," &
"155   (bc_1, ddr1_a4, input, X)," &
"156   (bc_1, ddr1_rasn, output3,X , 91, 1 , Z)," &
"157   (bc_1, *	,control,1)," &
"158   (bc_1, ddr1_a3, input, X)," &
"159   (bc_1, ddr1_wen, output3,X , 1, 1 , Z)," &
"160   (bc_1, *	,control,1)," &
"161   (bc_1, ddr1_a2, input, X)," &
"162   (bc_1, ddr1_a13, output3,X , 118, 1 , Z)," &
"163   (bc_1, *	,control,1)," &
"164   (bc_1, ddr1_a1, input, X)," &
"165   (bc_1, ddr1_a10, output3,X , 130, 1 , Z)," &
"166   (bc_1, *	,control,1)," &
"167   (bc_1, ddr1_a0, input, X)," &
"168   (bc_1, ddr1_dqm_ecc, output3,X , 169, 1 , Z)," &
"169   (bc_1, *	,control,1)," &
"170   (bc_1, ddr1_dqm_ecc, input, X)," &
"171   (bc_1, ddr1_dqm3, output3,X , 172, 1 , Z)," &
"172   (bc_1, *	,control,1)," &
"173   (bc_1, ddr1_dqm3, input, X)," &
"174   (bc_1, ddr1_dqm2, output3,X , 175, 1 , Z)," &
"175   (bc_1, *	,control,1)," &
"176   (bc_1, ddr1_dqm2, input, X)," &
"177   (bc_1, ddr1_dqm1, output3,X , 178, 1 , Z)," &
"178   (bc_1, *	,control,1)," &
"179   (bc_1, ddr1_dqm1, input, X)," &
"180   (bc_1, ddr1_dqm0, output3,X , 181, 1 , Z)," &
"181   (bc_1, *	,control,1)," &
"182   (bc_1, ddr1_dqm0, input, X)," &
"183   (bc_1, ddr1_dqsn_ecc, output3,X , 199, 1 , Z)," &
"184   (bc_1, *	,internal,0)," &
"185   (bc_1, ddr1_dqsn_ecc, input, X)," &
"186   (bc_1, ddr1_dqsn3, output3,X , 202, 1 , Z)," &
"187   (bc_1, *	,internal,0)," &
"188   (bc_1, ddr1_dqsn3, input, X)," &
"189   (bc_1, ddr1_dqsn2, output3,X , 205, 1 , Z)," &
"190   (bc_1, *	,internal,0)," &
"191   (bc_1, ddr1_dqsn2, input, X)," &
"192   (bc_1, ddr1_dqsn1, output3,X , 208, 1 , Z)," &
"193   (bc_1, *	,internal,0)," &
"194   (bc_1, ddr1_dqsn1, input, X)," &
"195   (bc_1, ddr1_dqsn0, output3,X , 211, 1 , Z)," &
"196   (bc_1, *	,internal,0)," &
"197   (bc_1, ddr1_dqsn0, input, X)," &
"198   (bc_1, ddr1_dqs_ecc, output3,X , 199, 1 , Z)," &
"199   (bc_1, *	,control,1)," &
"200   (bc_1, ddr1_dqs_ecc, input, X)," &
"201   (bc_1, ddr1_dqs3, output3,X , 202, 1 , Z)," &
"202   (bc_1, *	,control,1)," &
"203   (bc_1, ddr1_dqs3, input, X)," &
"204   (bc_1, ddr1_dqs2, output3,X , 205, 1 , Z)," &
"205   (bc_1, *	,control,1)," &
"206   (bc_1, ddr1_dqs2, input, X)," &
"207   (bc_1, ddr1_dqs1, output3,X , 208, 1 , Z)," &
"208   (bc_1, *	,control,1)," &
"209   (bc_1, ddr1_dqs1, input, X)," &
"210   (bc_1, ddr1_dqs0, output3,X , 211, 1 , Z)," &
"211   (bc_1, *	,control,1)," &
"212   (bc_1, ddr1_dqs0, input, X)," &
"213   (bc_1, *,         internal, 0)," &
"214   (bc_1, *,         internal, 0)," &
"215   (bc_1, *,         internal, 0)," &
"216   (bc_1, *,         internal, 0)," &
"217   (bc_1, *,         internal, 0)," &
"218   (bc_1, *,         internal, 0)," &
"219   (bc_1, *,         internal, 0)," &
"220   (bc_1, *,         internal, 0)," &
"221   (bc_1, *,         internal, 0)," &
"222   (bc_1, *,         internal, 0)," &
"223   (bc_1, *,         internal, 0)," &
"224   (bc_1, *,         internal, 0)," &
"225   (bc_1, *,         internal, 0)," &
"226   (bc_1, *,         internal, 0)," &
"227   (bc_1, *,         internal, 0)," &
"228   (bc_1, ddr1_ecc_d7, output3,X , 229, 1 , Z)," &
"229   (bc_1, *	,control,1)," &
"230   (bc_1, ddr1_ecc_d7, input, X)," &
"231   (bc_1, ddr1_ecc_d6, output3,X , 232, 1 , Z)," &
"232   (bc_1, *	,control,1)," &
"233   (bc_1, ddr1_ecc_d6, input, X)," &
"234   (bc_1, ddr1_ecc_d5, output3,X , 235, 1 , Z)," &
"235   (bc_1, *	,control,1)," &
"236   (bc_1, ddr1_ecc_d5, input, X)," &
"237   (bc_1, ddr1_ecc_d4, output3,X , 238, 1 , Z)," &
"238   (bc_1, *	,control,1)," &
"239   (bc_1, ddr1_ecc_d4, input, X)," &
"240   (bc_1, ddr1_ecc_d3, output3,X , 241, 1 , Z)," &
"241   (bc_1, *	,control,1)," &
"242   (bc_1, ddr1_ecc_d3, input, X)," &
"243   (bc_1, ddr1_ecc_d2, output3,X , 244, 1 , Z)," &
"244   (bc_1, *	,control,1)," &
"245   (bc_1, ddr1_ecc_d2, input, X)," &
"246   (bc_1, ddr1_ecc_d1, output3,X , 247, 1 , Z)," &
"247   (bc_1, *	,control,1)," &
"248   (bc_1, ddr1_ecc_d1, input, X)," &
"249   (bc_1, ddr1_ecc_d0, output3,X , 250, 1 , Z)," &
"250   (bc_1, *	,control,1)," &
"251   (bc_1, ddr1_ecc_d0, input, X)," &
"252   (bc_1, ddr1_d31, output3,X , 253, 1 , Z)," &
"253   (bc_1, *	,control,1)," &
"254   (bc_1, ddr1_d31, input, X)," &
"255   (bc_1, ddr1_d30, output3,X , 256, 1 , Z)," &
"256   (bc_1, *	,control,1)," &
"257   (bc_1, ddr1_d30, input, X)," &
"258   (bc_1, ddr1_d29, output3,X , 259, 1 , Z)," &
"259   (bc_1, *	,control,1)," &
"260   (bc_1, ddr1_d29, input, X)," &
"261   (bc_1, ddr1_d28, output3,X , 262, 1 , Z)," &
"262   (bc_1, *	,control,1)," &
"263   (bc_1, ddr1_d28, input, X)," &
"264   (bc_1, ddr1_d27, output3,X , 265, 1 , Z)," &
"265   (bc_1, *	,control,1)," &
"266   (bc_1, ddr1_d27, input, X)," &
"267   (bc_1, ddr1_d26, output3,X , 268, 1 , Z)," &
"268   (bc_1, *	,control,1)," &
"269   (bc_1, ddr1_d26, input, X)," &
"270   (bc_1, ddr1_d25, output3,X , 271, 1 , Z)," &
"271   (bc_1, *	,control,1)," &
"272   (bc_1, ddr1_d25, input, X)," &
"273   (bc_1, ddr1_d24, output3,X , 274, 1 , Z)," &
"274   (bc_1, *	,control,1)," &
"275   (bc_1, ddr1_d24, input, X)," &
"276   (bc_1, ddr1_d23, output3,X , 277, 1 , Z)," &
"277   (bc_1, *	,control,1)," &
"278   (bc_1, ddr1_d23, input, X)," &
"279   (bc_1, ddr1_d22, output3,X , 280, 1 , Z)," &
"280   (bc_1, *	,control,1)," &
"281   (bc_1, ddr1_d22, input, X)," &
"282   (bc_1, ddr1_d21, output3,X , 283, 1 , Z)," &
"283   (bc_1, *	,control,1)," &
"284   (bc_1, ddr1_d21, input, X)," &
"285   (bc_1, ddr1_d20, output3,X , 286, 1 , Z)," &
"286   (bc_1, *	,control,1)," &
"287   (bc_1, ddr1_d20, input, X)," &
"288   (bc_1, ddr1_d19, output3,X , 289, 1 , Z)," &
"289   (bc_1, *	,control,1)," &
"290   (bc_1, ddr1_d19, input, X)," &
"291   (bc_1, ddr1_d18, output3,X , 292, 1 , Z)," &
"292   (bc_1, *	,control,1)," &
"293   (bc_1, ddr1_d18, input, X)," &
"294   (bc_1, ddr1_d17, output3,X , 295, 1 , Z)," &
"295   (bc_1, *	,control,1)," &
"296   (bc_1, ddr1_d17, input, X)," &
"297   (bc_1, ddr1_d16, output3,X , 298, 1 , Z)," &
"298   (bc_1, *	,control,1)," &
"299   (bc_1, ddr1_d16, input, X)," &
"300   (bc_1, ddr1_d15, output3,X , 301, 1 , Z)," &
"301   (bc_1, *	,control,1)," &
"302   (bc_1, ddr1_d15, input, X)," &
"303   (bc_1, ddr1_d14, output3,X , 304, 1 , Z)," &
"304   (bc_1, *	,control,1)," &
"305   (bc_1, ddr1_d14, input, X)," &
"306   (bc_1, ddr1_d13, output3,X , 307, 1 , Z)," &
"307   (bc_1, *	,control,1)," &
"308   (bc_1, ddr1_d13, input, X)," &
"309   (bc_1, ddr1_d12, output3,X , 310, 1 , Z)," &
"310   (bc_1, *	,control,1)," &
"311   (bc_1, ddr1_d12, input, X)," &
"312   (bc_1, ddr1_d11, output3,X , 313, 1 , Z)," &
"313   (bc_1, *	,control,1)," &
"314   (bc_1, ddr1_d11, input, X)," &
"315   (bc_1, ddr1_d10, output3,X , 316, 1 , Z)," &
"316   (bc_1, *	,control,1)," &
"317   (bc_1, ddr1_d10, input, X)," &
"318   (bc_1, ddr1_d9, output3,X , 319, 1 , Z)," &
"319   (bc_1, *	,control,1)," &
"320   (bc_1, ddr1_d9, input, X)," &
"321   (bc_1, ddr1_d8, output3,X , 322, 1 , Z)," &
"322   (bc_1, *	,control,1)," &
"323   (bc_1, ddr1_d8, input, X)," &
"324   (bc_1, ddr1_d7, output3,X , 325, 1 , Z)," &
"325   (bc_1, *	,control,1)," &
"326   (bc_1, ddr1_d7, input, X)," &
"327   (bc_1, ddr1_d6, output3,X , 328, 1 , Z)," &
"328   (bc_1, *	,control,1)," &
"329   (bc_1, ddr1_d6, input, X)," &
"330   (bc_1, ddr1_d5, output3,X , 331, 1 , Z)," &
"331   (bc_1, *	,control,1)," &
"332   (bc_1, ddr1_d5, input, X)," &
"333   (bc_1, ddr1_d4, output3,X , 334, 1 , Z)," &
"334   (bc_1, *	,control,1)," &
"335   (bc_1, ddr1_d4, input, X)," &
"336   (bc_1, ddr1_d3, output3,X , 337, 1 , Z)," &
"337   (bc_1, *	,control,1)," &
"338   (bc_1, ddr1_d3, input, X)," &
"339   (bc_1, ddr1_d2, output3,X , 340, 1 , Z)," &
"340   (bc_1, *	,control,1)," &
"341   (bc_1, ddr1_d2, input, X)," &
"342   (bc_1, ddr1_d1, output3,X , 343, 1 , Z)," &
"343   (bc_1, *	,control,1)," &
"344   (bc_1, ddr1_d1, input, X)," &
"345   (bc_1, ddr1_d0, output3,X , 346, 1 , Z)," &
"346   (bc_1, *	,control,1)," &
"347   (bc_1, ddr1_d0, input, X)," &
"348   (bc_1, *	, internal, 0)," &
"349   (bc_1, *	, internal, 0)," &
"350   (bc_1, *	, internal, 0)," &
"351   (bc_1, *	, internal, 0)," &
"352   (bc_1, *	, internal, 0)," &
"353   (bc_1, *	, internal, 0)," &
"354   (bc_1, rstoutn, output3,X , 355, 1 , Z)," &
"355   (bc_1, *	,control,1)," &
"356   (bc_1, rstoutn, input, X)," &
"357   (bc_1, nmin, output3,X , 358, 1 , Z)," &
"358   (bc_1, *	,control,1)," &
"359   (bc_1, nmin	, input, X)," &
"360   (bc_1, resetn, output3,X , 361, 1 , Z)," &
"361   (bc_1, *	,control,1)," &
"362   (bc_1, resetn	, input, X)," &
"363   (bc_1, emu1, output3,X , 364, 1 , Z)," &
"364   (bc_1, *	,control,1)," &
"365   (bc_1, emu1, input, X)," &
"366   (bc_1, emu0, output3,X , 367, 1 , Z)," &
"367   (bc_1, *	,control,1)," &
"368   (bc_1, emu0, input, X)," &
"369   (bc_1, rtck, output3,X , 370, 1 , Z)," &
"370   (bc_1, *	,control,1)," &
"371   (bc_1, rtck, input, X)," &
"372   (bc_1, i2c2_scl, output2, 1 , 372, 1 , weak1)," &
"373   (bc_1, *	,internal,0)," &
"374   (bc_1, i2c2_scl, input, X)," &
"375   (bc_1, i2c2_sda, output2, 1 , 375, 1 , weak1)," &
"376   (bc_1, *	,internal,0)," &
"377   (bc_1, i2c2_sda, input, X)," &
"378   (bc_1, i2c1_scl, output2, 1 , 378, 1 , weak1)," &
"379   (bc_1, *	,internal,0)," &
"380   (bc_1, i2c1_scl, input, X)," &
"381   (bc_1, i2c1_sda, output2, 1 , 381, 1 , weak1)," &
"382   (bc_1, *	,internal,0)," &
"383   (bc_1, i2c1_sda, input, X)," &
"384   (bc_1, uart2_rtsn, output3,X , 385, 1 , Z)," &
"385   (bc_1, *	,control,1)," &
"386   (bc_1, uart2_rtsn, input, X)," &
"387   (bc_1, uart2_ctsn, output3,X , 388, 1 , Z)," &
"388   (bc_1, *	,control,1)," &
"389   (bc_1, uart2_ctsn, input, X)," &
"390   (bc_1, uart2_txd, output3,X , 391, 1 , Z)," &
"391   (bc_1, *	,control,1)," &
"392   (bc_1, uart2_txd, input, X)," &
"393   (bc_1, uart2_rxd, output3,X , 394, 1 , Z)," &
"394   (bc_1, *	,control,1)," &
"395   (bc_1, uart2_rxd, input, X)," &
"396   (bc_1, uart1_rtsn, output3,X , 397, 1 , Z)," &
"397   (bc_1, *	,control,1)," &
"398   (bc_1, uart1_rtsn, input, X)," &
"399   (bc_1, uart1_ctsn, output3,X , 400, 1 , Z)," &
"400   (bc_1, *	,control,1)," &
"401   (bc_1, uart1_ctsn, input, X)," &
"402   (bc_1, uart1_txd, output3,X , 403, 1 , Z)," &
"403   (bc_1, *	,control,1)," &
"404   (bc_1, uart1_txd, input, X)," &
"405   (bc_1, uart1_rxd, output3,X , 406, 1 , Z)," &
"406   (bc_1, *	,control,1)," &
"407   (bc_1, uart1_rxd, input, X)," &
"408   (bc_1, dcan1_rx, output3,X , 409, 1 , Z)," &
"409   (bc_1, *	,control,1)," &
"410   (bc_1, dcan1_rx, input, X)," &
"411   (bc_1, dcan1_tx, output3,X , 412, 1 , Z)," &
"412   (bc_1, *	,control,1)," &
"413   (bc_1, dcan1_tx, input, X)," &
"414   (bc_1, spi2_cs0, output3,X , 415, 1 , Z)," &
"415   (bc_1, *	,control,1)," &
"416   (bc_1, spi2_cs0, input, X)," &
"417   (bc_1, spi2_d0, output3,X , 418, 1 , Z)," &
"418   (bc_1, *	,control,1)," &
"419   (bc_1, spi2_d0, input, X)," &
"420   (bc_1, spi2_d1, output3,X , 421, 1 , Z)," &
"421   (bc_1, *	,control,1)," &
"422   (bc_1, spi2_d1, input, X)," &
"423   (bc_1, spi2_sclk, output3,X , 424, 1 , Z)," &
"424   (bc_1, *	,control,1)," &
"425   (bc_1, spi2_sclk, input, X)," &
"426   (bc_1, spi1_cs1, output3,X , 427, 1 , Z)," &
"427   (bc_1, *	,control,1)," &
"428   (bc_1, spi1_cs1, input, X)," &
"429   (bc_1, spi1_cs0, output3,X , 430, 1 , Z)," &
"430   (bc_1, *	,control,1)," &
"431   (bc_1, spi1_cs0, input, X)," &
"432   (bc_1, spi1_d0, output3,X , 433, 1 , Z)," &
"433   (bc_1, *	,control,1)," &
"434   (bc_1, spi1_d0, input, X)," &
"435   (bc_1, spi1_d1, output3,X , 436, 1 , Z)," &
"436   (bc_1, *	,control,1)," &
"437   (bc_1, spi1_d1, input, X)," &
"438   (bc_1, spi1_sclk, output3,X , 439, 1 , Z)," &
"439   (bc_1, *	,control,1)," &
"440   (bc_1, spi1_sclk, input, X)," &
"441   (bc_1, xref_clk0, output3,X , 442, 1 , Z)," &
"442   (bc_1, *	,control,1)," &
"443   (bc_1, xref_clk0, input, X)," &
"444   (bc_1, rgmii0_rxd0, output3,X , 445, 1 , Z)," &
"445   (bc_1, *	,control,1)," &
"446   (bc_1, rgmii0_rxd0, input, X)," &
"447   (bc_1, rgmii0_rxd1, output3,X , 448, 1 , Z)," &
"448   (bc_1, *	,control,1)," &
"449   (bc_1, rgmii0_rxd1, input, X)," &
"450   (bc_1, rgmii0_rxd2, output3,X , 451, 1 , Z)," &
"451   (bc_1, *	,control,1)," &
"452   (bc_1, rgmii0_rxd2, input, X)," &
"453   (bc_1, rgmii0_rxd3, output3,X , 454, 1 , Z)," &
"454   (bc_1, *	,control,1)," &
"455   (bc_1, rgmii0_rxd3, input, X)," &
"456   (bc_1, rgmii0_rxctl, output3,X , 457, 1 , Z)," &
"457   (bc_1, *	,control,1)," &
"458   (bc_1, rgmii0_rxctl, input, X)," &
"459   (bc_1, rgmii0_rxc, output3,X , 460, 1 , Z)," &
"460   (bc_1, *	,control,1)," &
"461   (bc_1, rgmii0_rxc, input, X)," &
"462   (bc_1, rgmii0_txd0, output3,X , 463, 1 , Z)," &
"463   (bc_1, *	,control,1)," &
"464   (bc_1, rgmii0_txd0, input, X)," &
"465   (bc_1, rgmii0_txd1, output3,X , 466, 1 , Z)," &
"466   (bc_1, *	,control,1)," &
"467   (bc_1, rgmii0_txd1, input, X)," &
"468   (bc_1, rgmii0_txd2, output3,X , 469, 1 , Z)," &
"469   (bc_1, *	,control,1)," &
"470   (bc_1, rgmii0_txd2, input, X)," &
"471   (bc_1, rgmii0_txd3, output3,X , 472, 1 , Z)," &
"472   (bc_1, *	,control,1)," &
"473   (bc_1, rgmii0_txd3, input, X)," &
"474   (bc_1, rgmii0_txctl, output3,X , 475, 1 , Z)," &
"475   (bc_1, *	,control,1)," &
"476   (bc_1, rgmii0_txctl, input, X)," &
"477   (bc_1, rgmii0_txc, output3,X , 478, 1 , Z)," &
"478   (bc_1, *	,control,1)," &
"479   (bc_1, rgmii0_txc, input, X)," &
"480   (bc_1, mdio_d, output3,X , 481, 1 , Z)," &
"481   (bc_1, *	,control,1)," &
"482   (bc_1, mdio_d, input, X)," &
"483   (bc_1, mdio_mclk, output3,X , 484, 1 , Z)," &
"484   (bc_1, *	,control,1)," &
"485   (bc_1, mdio_mclk, input, X)," &
"486   (bc_1, dcan2_rx, output3,X , 487, 1 , Z)," &
"487   (bc_1, *	,control,1)," &
"488   (bc_1, dcan2_rx, input, X)," &
"489   (bc_1, dcan2_tx, output3,X , 490, 1 , Z)," &
"490   (bc_1, *	,control,1)," &
"491   (bc_1, dcan2_tx, input, X)," &
"492   (bc_1, vout1_d23, output3,X , 493, 1 , Z)," &
"493   (bc_1, *	,control,1)," &
"494   (bc_1, vout1_d23, input, X)," &
"495   (bc_1, vout1_d22, output3,X , 496, 1 , Z)," &
"496   (bc_1, *	,control,1)," &
"497   (bc_1, vout1_d22, input, X)," &
"498   (bc_1, vout1_d21, output3,X , 499, 1 , Z)," &
"499   (bc_1, *	,control,1)," &
"500   (bc_1, vout1_d21, input, X)," &
"501   (bc_1, vout1_d20, output3,X , 502, 1 , Z)," &
"502   (bc_1, *	,control,1)," &
"503   (bc_1, vout1_d20, input, X)," &
"504   (bc_1, vout1_d19, output3,X , 505, 1 , Z)," &
"505   (bc_1, *	,control,1)," &
"506   (bc_1, vout1_d19, input, X)," &
"507   (bc_1, vout1_d18, output3,X , 508, 1 , Z)," &
"508   (bc_1, *	,control,1)," &
"509   (bc_1, vout1_d18, input, X)," &
"510   (bc_1, vout1_d17, output3,X , 511, 1 , Z)," &
"511   (bc_1, *	,control,1)," &
"512   (bc_1, vout1_d17, input, X)," &
"513   (bc_1, vout1_d16, output3,X , 514, 1 , Z)," &
"514   (bc_1, *	,control,1)," &
"515   (bc_1, vout1_d16, input, X)," &
"516   (bc_1, vout1_d15, output3,X , 517, 1 , Z)," &
"517   (bc_1, *	,control,1)," &
"518   (bc_1, vout1_d15, input, X)," &
"519   (bc_1, vout1_d14, output3,X , 520, 1 , Z)," &
"520   (bc_1, *	,control,1)," &
"521   (bc_1, vout1_d14, input, X)," &
"522   (bc_1, vout1_d13, output3,X , 523, 1 , Z)," &
"523   (bc_1, *	,control,1)," &
"524   (bc_1, vout1_d13, input, X)," &
"525   (bc_1, vout1_d12, output3,X , 526, 1 , Z)," &
"526   (bc_1, *	,control,1)," &
"527   (bc_1, vout1_d12, input, X)," &
"528   (bc_1, vout1_d11, output3,X , 529, 1 , Z)," &
"529   (bc_1, *	,control,1)," &
"530   (bc_1, vout1_d11, input, X)," &
"531   (bc_1, vout1_d10, output3,X , 532, 1 , Z)," &
"532   (bc_1, *	,control,1)," &
"533   (bc_1, vout1_d10, input, X)," &
"534   (bc_1, vout1_d9, output3,X , 535, 1 , Z)," &
"535   (bc_1, *	,control,1)," &
"536   (bc_1, vout1_d9, input, X)," &
"537   (bc_1, vout1_d8, output3,X , 538, 1 , Z)," &
"538   (bc_1, *	,control,1)," &
"539   (bc_1, vout1_d8, input, X)," &
"540   (bc_1, vout1_d7, output3,X , 541, 1 , Z)," &
"541   (bc_1, *	,control,1)," &
"542   (bc_1, vout1_d7, input, X)," &
"543   (bc_1, vout1_d6, output3,X , 544, 1 , Z)," &
"544   (bc_1, *	,control,1)," &
"545   (bc_1, vout1_d6, input, X)," &
"546   (bc_1, vout1_d5, output3,X , 547, 1 , Z)," &
"547   (bc_1, *	,control,1)," &
"548   (bc_1, vout1_d5, input, X)," &
"549   (bc_1, vout1_d4, output3,X , 550, 1 , Z)," &
"550   (bc_1, *	,control,1)," &
"551   (bc_1, vout1_d4, input, X)," &
"552   (bc_1, vout1_d3, output3,X , 553, 1 , Z)," &
"553   (bc_1, *	,control,1)," &
"554   (bc_1, vout1_d3, input, X)," &
"555   (bc_1, vout1_d2, output3,X , 556, 1 , Z)," &
"556   (bc_1, *	,control,1)," &
"557   (bc_1, vout1_d2, input, X)," &
"558   (bc_1, vout1_d1, output3,X , 559, 1 , Z)," &
"559   (bc_1, *	,control,1)," &
"560   (bc_1, vout1_d1, input, X)," &
"561   (bc_1, vout1_d0, output3,X , 562, 1 , Z)," &
"562   (bc_1, *	,control,1)," &
"563   (bc_1, vout1_d0, input, X)," &
"564   (bc_1, vout1_vsync, output3,X , 565, 1 , Z)," &
"565   (bc_1, *	,control,1)," &
"566   (bc_1, vout1_vsync, input, X)," &
"567   (bc_1, vout1_hsync, output3,X , 568, 1 , Z)," &
"568   (bc_1, *	,control,1)," &
"569   (bc_1, vout1_hsync, input, X)," &
"570   (bc_1, vout1_fld, output3,X , 571, 1 , Z)," &
"571   (bc_1, *	,control,1)," &
"572   (bc_1, vout1_fld, input, X)," &
"573   (bc_1, vout1_de, output3,X , 574, 1 , Z)," &
"574   (bc_1, *	,control,1)," &
"575   (bc_1, vout1_de, input, X)," &
"576   (bc_1, vout1_clk, output3,X , 577, 1 , Z)," &
"577   (bc_1, *	,control,1)," &
"578   (bc_1, vout1_clk, input, X)," &
"579   (bc_1, vin2a_fld0, output3,X , 580, 1 , Z)," &
"580   (bc_1, *	,control,1)," &
"581   (bc_1, vin2a_fld0, input, X)," &
"582   (bc_1, vin2a_de0, output3,X , 583, 1 , Z)," &
"583   (bc_1, *	,control,1)," &
"584   (bc_1, vin2a_de0, input, X)," &
"585   (bc_1, vin2a_clk0, output3,X , 586, 1 , Z)," &
"586   (bc_1, *	,control,1)," &
"587   (bc_1, vin2a_clk0, input, X)," &
"588   (bc_1, vin1a_d15, output3,X , 589, 1 , Z)," &
"589   (bc_1, *	,control,1)," &
"590   (bc_1, vin1a_d15, input, X)," &
"591   (bc_1, vin1a_d14, output3,X , 592, 1 , Z)," &
"592   (bc_1, *	,control,1)," &
"593   (bc_1, vin1a_d14, input, X)," &
"594   (bc_1, vin1a_d13, output3,X , 595, 1 , Z)," &
"595   (bc_1, *	,control,1)," &
"596   (bc_1, vin1a_d13, input, X)," &
"597   (bc_1, vin1a_d12, output3,X , 598, 1 , Z)," &
"598   (bc_1, *	,control,1)," &
"599   (bc_1, vin1a_d12, input, X)," &
"600   (bc_1, vin1a_d11, output3,X , 601, 1 , Z)," &
"601   (bc_1, *	,control,1)," &
"602   (bc_1, vin1a_d11, input, X)," &
"603   (bc_1, vin1a_d10, output3,X , 604, 1 , Z)," &
"604   (bc_1, *	,control,1)," &
"605   (bc_1, vin1a_d10, input, X)," &
"606   (bc_1, vin1a_d9, output3,X , 607, 1 , Z)," &
"607   (bc_1, *	,control,1)," &
"608   (bc_1, vin1a_d9, input, X)," &
"609   (bc_1, vin1a_d8, output3,X , 610, 1 , Z)," &
"610   (bc_1, *	,control,1)," &
"611   (bc_1, vin1a_d8, input, X)," &
"612   (bc_1, vin1a_d7, output3,X , 613, 1 , Z)," &
"613   (bc_1, *	,control,1)," &
"614   (bc_1, vin1a_d7, input, X)," &
"615   (bc_1, vin1a_d6, output3,X , 616, 1 , Z)," &
"616   (bc_1, *	,control,1)," &
"617   (bc_1, vin1a_d6, input, X)," &
"618   (bc_1, vin1a_d5, output3,X , 619, 1 , Z)," &
"619   (bc_1, *	,control,1)," &
"620   (bc_1, vin1a_d5, input, X)," &
"621   (bc_1, vin1a_d4, output3,X , 622, 1 , Z)," &
"622   (bc_1, *	,control,1)," &
"623   (bc_1, vin1a_d4, input, X)," &
"624   (bc_1, vin1a_d3, output3,X , 625, 1 , Z)," &
"625   (bc_1, *	,control,1)," &
"626   (bc_1, vin1a_d3, input, X)," &
"627   (bc_1, vin1a_d2, output3,X , 628, 1 , Z)," &
"628   (bc_1, *	,control,1)," &
"629   (bc_1, vin1a_d2, input, X)," &
"630   (bc_1, vin1a_d1, output3,X , 631, 1 , Z)," &
"631   (bc_1, *	,control,1)," &
"632   (bc_1, vin1a_d1, input, X)," &
"633   (bc_1, vin1a_d0, output3,X , 634, 1 , Z)," &
"634   (bc_1, *	,control,1)," &
"635   (bc_1, vin1a_d0, input, X)," &
"636   (bc_1, vin1a_vsync0, output3,X , 637, 1 , Z)," &
"637   (bc_1, *	,control,1)," &
"638   (bc_1, vin1a_vsync0, input, X)," &
"639   (bc_1, vin1a_hsync0, output3,X , 640, 1 , Z)," &
"640   (bc_1, *	,control,1)," &
"641   (bc_1, vin1a_hsync0, input, X)," &
"642   (bc_1, vin1a_fld0, output3,X , 643, 1 , Z)," &
"643   (bc_1, *	,control,1)," &
"644   (bc_1, vin1a_fld0, input, X)," &
"645   (bc_1, vin1a_de0, output3,X , 646, 1 , Z)," &
"646   (bc_1, *	,control,1)," &
"647   (bc_1, vin1a_de0, input, X)," &
"648   (bc_1, vin1a_clk0, output3,X , 649, 1 , Z)," &
"649   (bc_1, *	,control,1)," &
"650   (bc_1, vin1a_clk0, input, X)," &
"651   (bc_1, gpmc_ad15, output3,X , 652, 1 , Z)," &
"652   (bc_1, *	,control,1)," &
"653   (bc_1, gpmc_ad15, input, X)," &
"654   (bc_1, gpmc_ad14, output3,X , 655, 1 , Z)," &
"655   (bc_1, *	,control,1)," &
"656   (bc_1, gpmc_ad14, input, X)," &
"657   (bc_1, gpmc_ad13, output3,X , 658, 1 , Z)," &
"658   (bc_1, *	,control,1)," &
"659   (bc_1, gpmc_ad13, input, X)," &
"660   (bc_1, gpmc_ad12, output3,X , 661, 1 , Z)," &
"661   (bc_1, *	,control,1)," &
"662   (bc_1, gpmc_ad12, input, X)," &
"663   (bc_1, gpmc_ad11, output3,X , 664, 1 , Z)," &
"664   (bc_1, *	,control,1)," &
"665   (bc_1, gpmc_ad11, input, X)," &
"666   (bc_1, gpmc_ad10, output3,X , 667, 1 , Z)," &
"667   (bc_1, *	,control,1)," &
"668   (bc_1, gpmc_ad10, input, X)," &
"669   (bc_1, gpmc_ad9, output3,X , 670, 1 , Z)," &
"670   (bc_1, *	,control,1)," &
"671   (bc_1, gpmc_ad9, input, X)," &
"672   (bc_1, gpmc_ad8, output3,X , 673, 1 , Z)," &
"673   (bc_1, *	,control,1)," &
"674   (bc_1, gpmc_ad8, input, X)," &
"675   (bc_1, gpmc_ad7, output3,X , 676, 1 , Z)," &
"676   (bc_1, *	,control,1)," &
"677   (bc_1, gpmc_ad7, input, X)," &
"678   (bc_1, gpmc_ad6, output3,X , 679, 1 , Z)," &
"679   (bc_1, *	,control,1)," &
"680   (bc_1, gpmc_ad6, input, X)," &
"681   (bc_1, gpmc_ad5, output3,X , 682, 1 , Z)," &
"682   (bc_1, *	,control,1)," &
"683   (bc_1, gpmc_ad5, input, X)," &
"684   (bc_1, gpmc_ad4, output3,X , 685, 1 , Z)," &
"685   (bc_1, *	,control,1)," &
"686   (bc_1, gpmc_ad4, input, X)," &
"687   (bc_1, gpmc_ad3, output3,X , 688, 1 , Z)," &
"688   (bc_1, *	,control,1)," &
"689   (bc_1, gpmc_ad3, input, X)," &
"690   (bc_1, gpmc_ad2, output3,X , 691, 1 , Z)," &
"691   (bc_1, *	,control,1)," &
"692   (bc_1, gpmc_ad2, input, X)," &
"693   (bc_1, gpmc_ad1, output3,X , 694, 1 , Z)," &
"694   (bc_1, *	,control,1)," &
"695   (bc_1, gpmc_ad1, input, X)," &
"696   (bc_1, gpmc_ad0, output3,X , 697, 1 , Z)," &
"697   (bc_1, *	,control,1)," &
"698   (bc_1, gpmc_ad0, input, X)," &
"699   (bc_1, gpmc_wait0, output3,X , 700, 1 , Z)," &
"700   (bc_1, *	,control,1)," &
"701   (bc_1, gpmc_wait0, input, X)," &
"702   (bc_1, gpmc_cs6, output3,X , 703, 1 , Z)," &
"703   (bc_1, *	,control,1)," &
"704   (bc_1, gpmc_cs6, input, X)," &
"705   (bc_1, gpmc_cs5, output3,X , 706, 1 , Z)," &
"706   (bc_1, *	,control,1)," &
"707   (bc_1, gpmc_cs5, input, X)," &
"708   (bc_1, gpmc_cs4, output3,X , 709, 1 , Z)," &
"709   (bc_1, *	,control,1)," &
"710   (bc_1, gpmc_cs4, input, X)," &
"711   (bc_1, gpmc_cs3, output3,X , 712, 1 , Z)," &
"712   (bc_1, *	,control,1)," &
"713   (bc_1, gpmc_cs3, input, X)," &
"714   (bc_1, gpmc_cs2, output3,X , 715, 1 , Z)," &
"715   (bc_1, *	,control,1)," &
"716   (bc_1, gpmc_cs2, input, X)," &
"717   (bc_1, gpmc_cs1, output3,X , 718, 1 , Z)," &
"718   (bc_1, *	,control,1)," &
"719   (bc_1, gpmc_cs1, input, X)," &
"720   (bc_1, gpmc_cs0, output3,X , 721, 1 , Z)," &
"721   (bc_1, *	,control,1)," &
"722   (bc_1, gpmc_cs0, input, X)," &
"723   (bc_1, gpmc_wen, output3,X , 724, 1 , Z)," &
"724   (bc_1, *	,control,1)," &
"725   (bc_1, gpmc_wen, input, X)," &
"726   (bc_1, gpmc_oen_ren, output3, X, 727 , 1 , Z)," &
"727   (bc_1, 	* , control, 1)," &
"728   (bc_1, gpmc_oen_ren	, input, X)," &
"729   (bc_1, gpmc_advn_ale, output3,X , 730, 1 , Z)," &
"730   (bc_1, *	,control,1)," &
"731   (bc_1, gpmc_advn_ale, input, X)," &
"732   (bc_1, gpmc_ben1, output3,X , 733, 1 , Z)," &
"733   (bc_1, *	,control,1)," &
"734   (bc_1, gpmc_ben1, input, X)," &
"735   (bc_1, gpmc_ben0, output3,X , 736, 1 , Z)," &
"736   (bc_1, *	,control,1)," &
"737   (bc_1, gpmc_ben0, input, X)," &
"738   (bc_1, gpmc_clk, output3,X , 739, 1 , Z)," &
"739   (bc_1, *	,control,1)," &
"740   (bc_1, gpmc_clk, input, X)" ;


end F791775 ;

This library contains 10579 BSDL files (for 7657 distinct entities) from 71 vendors
Last BSDL model (CYCLONE_10_10CX220F780) was added on May 21, 2018 13:01
info@bsdl.info