-- *****************************************************************************
-- BSDL file for design UCD90320
-- Created by Synopsys Version Y-2006.06-SP5-1 (Mar 08, 2007)
-- Manually Modified to describe 90320 (Sept 8, 2016)
-- Verified using Asset Intertech Scanworks Sacn Path Verify (Sept 9, 2016)
-- Designer: Digital Power DWs
-- Company: Texas Instruments
-- Date: Thu Sep 8 10:49:46 2012
entity UCD90320 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "BGA169");
-- This section declares all the ports in the design.
port ( TCK : IN bit;
TDI : IN bit;
TDO : OUT bit;
TMS : IN bit;
AMON1 : inout bit;
AMON2 : inout bit;
AMON3 : inout bit;
AMON4 : inout bit;
AMON5 : inout bit;
AMON6 : inout bit;
AMON7 : inout bit;
AMON8 : inout bit;
AMON9 : inout bit;
AMON10 : inout bit;
AMON11 : inout bit;
AMON12 : inout bit;
AMON13 : inout bit;
AMON14 : inout bit;
AMON15 : inout bit;
AMON16 : inout bit;
AMON17 : inout bit;
AMON18 : inout bit;
AMON19 : inout bit;
AMON20 : inout bit;
AMON21 : inout bit;
AMON22 : inout bit;
AMON23 : inout bit;
AMON24 : inout bit;
EN1 : inout bit;
EN2 : inout bit;
EN3 : inout bit;
EN4 : inout bit;
EN5 : inout bit;
EN6 : inout bit;
EN7 : inout bit;
EN8 : inout bit;
EN9 : inout bit;
EN10 : inout bit;
EN11 : inout bit;
EN12 : inout bit;
EN13 : inout bit;
EN14 : inout bit;
EN15 : inout bit;
EN16 : inout bit;
EN17 : inout bit;
EN18 : inout bit;
EN19 : inout bit;
EN20 : inout bit;
EN21 : inout bit;
EN22 : inout bit;
EN23 : inout bit;
EN24 : inout bit;
EN25 : inout bit;
EN26 : inout bit;
EN27 : inout bit;
EN28 : inout bit;
EN29 : inout bit;
EN30 : inout bit;
EN31 : inout bit;
EN32 : inout bit;
MAR1 : inout bit;
MAR2 : inout bit;
MAR3 : inout bit;
MAR4 : inout bit;
MAR5 : inout bit;
MAR6 : inout bit;
MAR7 : inout bit;
MAR8 : inout bit;
MAR9 : inout bit;
MAR10 : inout bit;
MAR11 : inout bit;
MAR12 : inout bit;
MAR13 : inout bit;
MAR14 : inout bit;
MAR15 : inout bit;
MAR16 : inout bit;
MAR17 : inout bit;
MAR18 : inout bit;
MAR19 : inout bit;
MAR20 : inout bit;
MAR21 : inout bit;
MAR22 : inout bit;
MAR23 : inout bit;
MAR24 : inout bit;
DMON1 : inout bit;
DMON2 : inout bit;
DMON3 : inout bit;
DMON4 : inout bit;
DMON5 : inout bit;
DMON6 : inout bit;
DMON7 : inout bit;
DMON8 : inout bit;
GPIO1 : inout bit;
GPIO2 : inout bit;
GPIO3 : inout bit;
GPIO4 : inout bit;
SYNC_CLK : inout bit;
LGPO1 : inout bit;
LGPO2 : inout bit;
LGPO3 : inout bit;
LGPO4 : inout bit;
LGPO5 : inout bit;
LGPO6 : inout bit;
LGPO7 : inout bit;
LGPO8 : inout bit;
LGPO9 : inout bit;
LGPO10 : inout bit;
LGPO11 : inout bit;
LGPO12 : inout bit;
LGPO13 : inout bit;
LGPO14 : inout bit;
LGPO15 : inout bit;
LGPO16 : inout bit;
PMBUS_CLK : inout bit;
PMBUS_DATA : inout bit;
PMBUS_ALERT : inout bit;
PMBUS_CNTRL : inout bit;
PMBUS_ADDR0 : inout bit;
PMBUS_ADDR1 : inout bit;
PMBUS_ADDR2 : inout bit;
n_RESET : linkage bit;
V33A : linkage bit;
V33D_1 : linkage bit;
V33D_2 : linkage bit;
V33D_3 : linkage bit;
V33D_4 : linkage bit;
V33D_5 : linkage bit;
V33D_6 : linkage bit;
V33D_7 : linkage bit;
V33D_8 : linkage bit;
BPCAP_1 : linkage bit;
BPCAP_2 : linkage bit;
BPCAP_3 : linkage bit;
BPCAP_4 : linkage bit;
AVSS_1 : linkage bit;
AVSS_2 : linkage bit;
DVSS_1 : linkage bit;
DVSS_2 : linkage bit;
DVSS_3 : linkage bit;
DVSS_4 : linkage bit;
DVSS_5 : linkage bit;
DVSS_6 : linkage bit;
DVSS_7 : linkage bit;
DVSS_8 : linkage bit;
DVSS_9 : linkage bit;
DVSS_10 : linkage bit;
DVSS_11 : linkage bit;
DVSS_12 : linkage bit;
DVSS_13 : linkage bit;
DVSS_14 : linkage bit;
DVSS_15 : linkage bit;
DVSS_16 : linkage bit;
DVSS_17 : linkage bit;
DVSS_18 : linkage bit;
DVSS_19 : linkage bit;
DVSS_20 : linkage bit;
DVSS_21 : linkage bit;
DVSS_22 : linkage bit;
VREFA_P : linkage bit;
VREFA_N : linkage bit;
NC_1 : linkage bit;
NC_2 : linkage bit;
NC_3 : linkage bit;
NC_4 : linkage bit;
UNUSED_DVSS_1 : linkage bit;
UNUSED_DVSS_2 : linkage bit;
UNUSED_DVSS_3 : linkage bit;
UNUSED_DVSS_4 : linkage bit;
UNUSED_V33D : linkage bit
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of UCD90320: entity is "STD_1149_1_2001";
attribute PIN_MAP of UCD90320: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information is
-- extracted from the port-to-pin map file that was read in using the
-- "read_pin_map" command.
constant BGA169: PIN_MAP_STRING :=
"TCK : C10," &
"TDI : B10," &
"TDO : A11," &
"TMS : A10," &
"AMON1 : E2," &
"AMON2 : E1," &
"AMON3 : F2," &
"AMON4 : F1," &
"AMON5 : B3," &
"AMON6 : A3," &
"AMON7 : B4," &
"AMON8 : A4," &
"AMON9 : B5," &
"AMON10 : A5," &
"AMON11 : B6," &
"AMON12 : A6," &
"AMON13 : C1," &
"AMON14 : C2," &
"AMON15 : B1," &
"AMON16 : B2," &
"AMON17 : G2," &
"AMON18 : G1," &
"AMON19 : H1," &
"AMON20 : H2," &
"AMON21 : B7," &
"AMON22 : A7," &
"AMON23 : B8," &
"AMON24 : A8," &
"EN1 : M9," &
"EN2 : N9," &
"EN3 : L10," &
"EN4 : K10," &
"EN5 : L9," &
"EN6 : K9," &
"EN7 : N8," &
"EN8 : M8," &
"EN9 : L8," &
"EN10 : K8," &
"EN11 : N7," &
"EN12 : M7," &
"EN13 : K7," &
"EN14 : L7," &
"EN15 : N4," &
"EN16 : N3," &
"EN17 : K3," &
"EN18 : K4," &
"EN19 : J4," &
"EN20 : J2," &
"EN21 : J3," &
"EN22 : H4," &
"EN23 : H3," &
"EN24 : G4," &
"EN25 : F13," &
"EN26 : F12," &
"EN27 : G11," &
"EN28 : H10," &
"EN29 : H13," &
"EN30 : H12," &
"EN31 : H11," &
"EN32 : L13," &
"MAR1 : J13," &
"MAR2 : L5," &
"MAR3 : D8," &
"MAR4 : K6," &
"MAR5 : D4," &
"MAR6 : E4," &
"MAR7 : F5," &
"MAR8 : N5," &
"MAR9 : N6," &
"MAR10 : K5," &
"MAR11 : M6," &
"MAR12 : L6," &
"MAR13 : D11," &
"MAR14 : C12," &
"MAR15 : A13," &
"MAR16 : B13," &
"MAR17 : D12," &
"MAR18 : C13," &
"MAR19 : E12," &
"MAR20 : E13," &
"MAR21 : M13," &
"MAR22 : L12," &
"MAR23 : M5," &
"MAR24 : J12," &
"DMON1 : F4," &
"DMON2 : F3," &
"DMON3 : G3," &
"DMON4 : D10," &
"DMON5 : L11," &
"DMON6 : N12," &
"DMON7 : N11," &
"DMON8 : M11," &
"GPIO1 : B11," &
"GPIO2 : B12," &
"GPIO3 : C11," &
"GPIO4 : A12," &
"SYNC_CLK : K2," &
"LGPO1 : C9," &
"LGPO2 : B9," &
"LGPO3 : A9," &
"LGPO4 : C8," &
"LGPO5 : D5," &
"LGPO6 : C5," &
"LGPO7 : C6," &
"LGPO8 : C4," &
"LGPO9 : L3," &
"LGPO10 : M1," &
"LGPO11 : M2," &
"LGPO12 : M3," &
"LGPO13 : L4," &
"LGPO14 : N1," &
"LGPO15 : M4," &
"LGPO16 : N2," &
"PMBUS_CLK : E10," &
"PMBUS_DATA : D13," &
"PMBUS_ALERT : F11," &
"PMBUS_CNTRL : E11," &
"PMBUS_ADDR0 : L2," &
"PMBUS_ADDR1 : L1," &
"PMBUS_ADDR2 : K1," &
"n_RESET : G10," &
"V33A : D3," &
"V33D_1 : D7," &
"V33D_2 : E6," &
"V33D_3 : E8," &
"V33D_4 : E9," &
"V33D_5 : F10," &
"V33D_6 : J7," &
"V33D_7 : J9," &
"V33D_8 : J10," &
"BPCAP_1 : D6," &
"BPCAP_2 : J1," &
"BPCAP_3 : J6," &
"BPCAP_4 : K13," &
"AVSS_1 : C3," &
"AVSS_2 : E3," &
"DVSS_1 : A1," &
"DVSS_2 : C7," &
"DVSS_3 : D9," &
"DVSS_4 : E5," &
"DVSS_5 : F9," &
"DVSS_6 : H5," &
"DVSS_7 : H9," &
"DVSS_8 : J5," &
"DVSS_9 : J8," &
"DVSS_10 : J11," &
"DVSS_11 : H6," &
"DVSS_12 : H7," &
"DVSS_13 : H8," &
"DVSS_14 : G5," &
"DVSS_15 : G6," &
"DVSS_16 : G7," &
"DVSS_17 : G8," &
"DVSS_18 : G9," &
"DVSS_19 : F6," &
"DVSS_20 : F7," &
"DVSS_21 : F8," &
"DVSS_22 : E7," &
"VREFA_P : D2," &
"VREFA_N : D1," &
"NC_1 : A2," &
"NC_2 : G13," &
"NC_3 : M12," &
"NC_4 : N10," &
"UNUSED_DVSS_1 : G12," &
"UNUSED_DVSS_2 : K11," &
"UNUSED_DVSS_3 : M10," &
"UNUSED_DVSS_4 : N13," &
"UNUSED_V33D : K12";
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in
-- the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of UCD90320: entity is 4;
-- Specifies the boundary-scan instructions implemented in the design and their
-- opcodes.
attribute INSTRUCTION_OPCODE of UCD90320: entity is
"ABORT (1000)," &
"DPACC (1010)," &
"APACC (1011)," &
"EXTEST (0000)," &
"BYPASS (1111)," &
"SAMPLE (0010)," &
"PRELOAD (0010)," &
"IDCODE (1110)";
-- Specifies the bit pattern that is loaded into the instruction register when
-- the TAP controller passes through the Capture-IR state. The standard mandates
-- that the two LSBs must be "01". The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of UCD90320: entity is "0001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during
-- the IDCODE instruction when the TAP controller passes through the Capture-DR
-- state.
attribute IDCODE_REGISTER of UCD90320: entity is
"0100" &
-- 4-bit version number
"1011101000000000" &
-- 16-bit part number
"01000111011" &
-- 11-bit identity of the manufacturer
"1";
-- Required by IEEE Std 1149.1
attribute INSTRUCTION_PRIVATE of UCD90320 : entity is
"ABORT, DPACC, APACC"; -- ARM debug access port private instructions
-- This section specifies the test data register placed between TDI and TDO for
-- each implemented instruction.
attribute REGISTER_ACCESS of UCD90320: entity is
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of UCD90320: entity is 352;
-- The following list specifies the characteristics of each cell in the boundary
-- scan register from TDI to TDO. The following is a description of the label
-- fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not have a port
-- name.
-- function: Is the function of the cell as defined by the standard. Is one
-- of input, output2, output3, bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be loaded with
-- for safe operation when the software might otherwise choose a
-- random value.
-- ccell : The control cell number. Specifies the control cell that
-- drives the output enable for this port.
-- disval : Specifies the value that is loaded into the control cell to
-- disable the output enable for the corresponding port.
-- rslt : Resulting state. Shows the state of the driver when it is
-- disabled.
attribute BOUNDARY_REGISTER of UCD90320: entity is
--
-- num cell port function safe [ccell disval rslt]
--
" 0 (BC_1, *, CONTROL, 1 ), " &
" 1 (BC_1, AMON5, OUTPUT3, X , 0, 1, Z ), " &
" 2 (BC_1, AMON5, INPUT, X ), " &
" 3 (BC_1, *, CONTROL, 1 ), " &
" 4 (BC_1, AMON6, OUTPUT3, X , 3, 1, Z ), " &
" 5 (BC_1, AMON6, INPUT, X ), " &
" 6 (BC_1, *, CONTROL, 1 ), " &
" 7 (BC_1, AMON7, OUTPUT3, X , 6, 1, Z ), " &
" 8 (BC_1, AMON7, INPUT, X ), " &
" 9 (BC_1, *, CONTROL, 1 ), " &
" 10 (BC_1, AMON8, OUTPUT3, X , 9, 1, Z ), " &
" 11 (BC_1, AMON8, INPUT, X ), " &
" 12 (BC_1, *, CONTROL, 1 ), " &
" 13 (BC_1, AMON9, OUTPUT3, X , 12, 1, Z ), " &
" 14 (BC_1, AMON9, INPUT, X ), " &
" 15 (BC_1, *, CONTROL, 1 ), " &
" 16 (BC_1, AMON10, OUTPUT3, X , 15, 1, Z ), " &
" 17 (BC_1, AMON10, INPUT, X ), " &
" 18 (BC_1, *, CONTROL, 1 ), " &
" 19 (BC_1, AMON11, OUTPUT3, X , 18, 1, Z ), " &
" 20 (BC_1, AMON11, INPUT, X ), " &
" 21 (BC_1, *, CONTROL, 1 ), " &
" 22 (BC_1, AMON12, OUTPUT3, X , 21, 1, Z ), " &
" 23 (BC_1, AMON12, INPUT, X ), " &
" 24 (BC_1, *, CONTROL, 1 ), " &
" 25 (BC_1, AMON21, OUTPUT3, X , 24, 1, Z ), " &
" 26 (BC_1, AMON21, INPUT, X ), " &
" 27 (BC_1, *, CONTROL, 1 ), " &
" 28 (BC_1, AMON22, OUTPUT3, X , 27, 1, Z ), " &
" 29 (BC_1, AMON22, INPUT, X ), " &
" 30 (BC_1, *, CONTROL, 1 ), " &
" 31 (BC_1, AMON23, OUTPUT3, X , 30, 1, Z ), " &
" 32 (BC_1, AMON23, INPUT, X ), " &
" 33 (BC_1, *, CONTROL, 1 ), " &
" 34 (BC_1, AMON24, OUTPUT3, X , 33, 1, Z ), " &
" 35 (BC_1, AMON24, INPUT, X ), " &
" 36 (BC_1, *, CONTROL, 1 ), " &
" 37 (BC_1, LGPO8, OUTPUT3, X , 36, 1, Z ), " &
" 38 (BC_1, LGPO8, INPUT, X ), " &
" 39 (BC_1, *, CONTROL, 1 ), " &
" 40 (BC_1, LGPO7, OUTPUT3, X , 39, 1, Z ), " &
" 41 (BC_1, LGPO7, INPUT, X ), " &
" 42 (BC_1, *, CONTROL, 1 ), " &
" 43 (BC_1, LGPO6, OUTPUT3, X , 42, 1, Z ), " &
" 44 (BC_1, LGPO6, INPUT, X ), " &
" 45 (BC_1, *, CONTROL, 1 ), " &
" 46 (BC_1, LGPO5, OUTPUT3, X , 45, 1, Z ), " &
" 47 (BC_1, LGPO5, INPUT, X ), " &
" 48 (BC_1, *, CONTROL, 1 ), " &
" 49 (BC_1, MAR3, OUTPUT3, X , 48, 1, Z ), " &
" 50 (BC_1, MAR3, INPUT, X ), " &
" 51 (BC_1, *, CONTROL, 1 ), " &
" 52 (BC_1, LGPO4, OUTPUT3, X , 51, 1, Z ), " &
" 53 (BC_1, LGPO4, INPUT, X ), " &
" 54 (BC_1, *, CONTROL, 1 ), " &
" 55 (BC_1, LGPO3, OUTPUT3, X , 54, 1, Z ), " &
" 56 (BC_1, LGPO3, INPUT, X ), " &
" 57 (BC_1, *, CONTROL, 1 ), " &
" 58 (BC_1, LGPO2, OUTPUT3, X , 57, 1, Z ), " &
" 59 (BC_1, LGPO2, INPUT, X ), " &
" 60 (BC_1, *, CONTROL, 1 ), " &
" 61 (BC_1, LGPO1, OUTPUT3, X , 60, 1, Z ), " &
" 62 (BC_1, LGPO1, INPUT, X ), " &
" 63 (BC_1, *, CONTROL, 1 ), " &
" 64 (BC_1, DMON4, OUTPUT3, X , 63, 1, Z ), " &
" 65 (BC_1, DMON4, INPUT, X ), " &
" 66 (BC_1, *, CONTROL, 1 ), " &
" 67 (BC_1, GPIO1, OUTPUT3, X , 66, 1, Z ), " &
" 68 (BC_1, GPIO1, INPUT, X ), " &
" 69 (BC_1, *, CONTROL, 1 ), " &
" 70 (BC_1, GPIO2, OUTPUT3, X , 69, 1, Z ), " &
" 71 (BC_1, GPIO2, INPUT, X ), " &
" 72 (BC_1, *, CONTROL, 1 ), " &
" 73 (BC_1, GPIO3, OUTPUT3, X , 72, 1, Z ), " &
" 74 (BC_1, GPIO3, INPUT, X ), " &
" 75 (BC_1, *, CONTROL, 1 ), " &
" 76 (BC_1, GPIO4, OUTPUT3, X , 75, 1, Z ), " &
" 77 (BC_1, GPIO4, INPUT, X ), " &
" 78 (BC_1, *, CONTROL, 1 ), " &
" 79 (BC_1, MAR13, OUTPUT3, X , 78, 1, Z ), " &
" 80 (BC_1, MAR13, INPUT, X ), " &
" 81 (BC_1, *, CONTROL, 1 ), " &
" 82 (BC_1, MAR14, OUTPUT3, X , 81, 1, Z ), " &
" 83 (BC_1, MAR14, INPUT, X ), " &
" 84 (BC_1, *, CONTROL, 1 ), " &
" 85 (BC_1, MAR15, OUTPUT3, X , 84, 1, Z ), " &
" 86 (BC_1, MAR15, INPUT, X ), " &
" 87 (BC_1, *, CONTROL, 1 ), " &
" 88 (BC_1, MAR16, OUTPUT3, X , 87, 1, Z ), " &
" 89 (BC_1, MAR16, INPUT, X ), " &
" 90 (BC_1, *, CONTROL, 1 ), " &
" 91 (BC_1, MAR17, OUTPUT3, X , 90, 1, Z ), " &
" 92 (BC_1, MAR17, INPUT, X ), " &
" 93 (BC_1, *, CONTROL, 1 ), " &
" 94 (BC_1, MAR18, OUTPUT3, X , 93, 1, Z ), " &
" 95 (BC_1, MAR18, INPUT, X ), " &
" 96 (BC_1, *, CONTROL, 1 ), " &
" 97 (BC_1, PMBUS_DATA, OUTPUT3, X , 96, 1, Z ), " &
" 98 (BC_1, PMBUS_DATA, INPUT, X ), " &
" 99 (BC_1, *, CONTROL, 1 ), " &
" 100 (BC_1, PMBUS_CLK, OUTPUT3, X , 99, 1, Z ), " &
" 101 (BC_1, PMBUS_CLK, INPUT, X ), " &
" 102 (BC_1, *, CONTROL, 1 ), " &
" 103 (BC_1, PMBUS_CNTRL, OUTPUT3, X , 102, 1, Z ), " &
" 104 (BC_1, PMBUS_CNTRL, INPUT, X ), " &
" 105 (BC_1, *, CONTROL, 1 ), " &
" 106 (BC_1, PMBUS_ALERT, OUTPUT3, X , 105, 1, Z ), " &
" 107 (BC_1, PMBUS_ALERT, INPUT, X ), " &
" 108 (BC_1, *, CONTROL, 1 ), " &
" 109 (BC_1, MAR19, OUTPUT3, X , 108, 1, Z ), " &
" 110 (BC_1, MAR19, INPUT, X ), " &
" 111 (BC_1, *, CONTROL, 1 ), " &
" 112 (BC_1, MAR20, OUTPUT3, X , 111, 1, Z ), " &
" 113 (BC_1, MAR20, INPUT, X ), " &
" 114 (BC_4, *, INTERNAL, 0 ), " &
" 115 (BC_4, *, INTERNAL, 0 ), " &
" 116 (BC_4, *, INTERNAL, 0 ), " &
" 117 (BC_4, *, INTERNAL, 0 ), " &
" 118 (BC_1, *, CONTROL, 1 ), " &
" 119 (BC_1, EN25, OUTPUT3, X , 118, 1, Z ), " &
" 120 (BC_1, EN25, INPUT, X ), " &
" 121 (BC_1, *, CONTROL, 1 ), " &
" 122 (BC_1, EN26, OUTPUT3, X , 121, 1, Z ), " &
" 123 (BC_1, EN26, INPUT, X ), " &
" 124 (BC_1, *, CONTROL, 1 ), " &
" 125 (BC_1, EN27, OUTPUT3, X , 124, 1, Z ), " &
" 126 (BC_1, EN27, INPUT, X ), " &
" 127 (BC_1, *, CONTROL, 1 ), " &
" 128 (BC_1, EN28, OUTPUT3, X , 127, 1, Z ), " &
" 129 (BC_1, EN28, INPUT, X ), " &
" 130 (BC_1, *, CONTROL, 1 ), " &
" 131 (BC_1, EN29, OUTPUT3, X , 130, 1, Z ), " &
" 132 (BC_1, EN29, INPUT, X ), " &
" 133 (BC_1, *, CONTROL, 1 ), " &
" 134 (BC_1, EN30, OUTPUT3, X , 133, 1, Z ), " &
" 135 (BC_1, EN30, INPUT, X ), " &
" 136 (BC_1, *, CONTROL, 1 ), " &
" 137 (BC_1, EN31, OUTPUT3, X , 136, 1, Z ), " &
" 138 (BC_1, EN31, INPUT, X ), " &
" 139 (BC_1, *, CONTROL, 1 ), " &
" 140 (BC_1, EN32, OUTPUT3, X , 139, 1, Z ), " &
" 141 (BC_1, EN32, INPUT, X ), " &
" 142 (BC_1, *, CONTROL, 1 ), " &
" 143 (BC_1, MAR21, OUTPUT3, X , 142, 1, Z ), " &
" 144 (BC_1, MAR21, INPUT, X ), " &
" 145 (BC_1, *, CONTROL, 1 ), " &
" 146 (BC_1, MAR22, OUTPUT3, X , 145, 1, Z ), " &
" 147 (BC_1, MAR22, INPUT, X ), " &
" 148 (BC_1, *, CONTROL, 1 ), " &
" 149 (BC_1, MAR1, OUTPUT3, X , 148, 1, Z ), " &
" 150 (BC_1, MAR1, INPUT, X ), " &
" 151 (BC_1, *, CONTROL, 1 ), " &
" 152 (BC_1, MAR24, OUTPUT3, X , 151, 1, Z ), " &
" 153 (BC_1, MAR24, INPUT, X ), " &
" 154 (BC_1, *, CONTROL, 1 ), " &
" 155 (BC_1, DMON5, OUTPUT3, X , 154, 1, Z ), " &
" 156 (BC_1, DMON5, INPUT, X ), " &
" 157 (BC_1, *, CONTROL, 1 ), " &
" 158 (BC_1, DMON6, OUTPUT3, X , 157, 1, Z ), " &
" 159 (BC_1, DMON6, INPUT, X ), " &
" 160 (BC_1, *, CONTROL, 1 ), " &
" 161 (BC_1, DMON7, OUTPUT3, X , 160, 1, Z ), " &
" 162 (BC_1, DMON7, INPUT, X ), " &
" 163 (BC_1, *, CONTROL, 1 ), " &
" 164 (BC_1, DMON8, OUTPUT3, X , 163, 1, Z ), " &
" 165 (BC_1, DMON8, INPUT, X ), " &
" 166 (BC_1, *, CONTROL, 1 ), " &
" 167 (BC_1, EN4, OUTPUT3, X , 166, 1, Z ), " &
" 168 (BC_1, EN4, INPUT, X ), " &
" 169 (BC_1, *, CONTROL, 1 ), " &
" 170 (BC_1, EN3, OUTPUT3, X , 169, 1, Z ), " &
" 171 (BC_1, EN3, INPUT, X ), " &
" 172 (BC_1, *, CONTROL, 1 ), " &
" 173 (BC_1, EN2, OUTPUT3, X , 172, 1, Z ), " &
" 174 (BC_1, EN2, INPUT, X ), " &
" 175 (BC_1, *, CONTROL, 1 ), " &
" 176 (BC_1, EN1, OUTPUT3, X , 175, 1, Z ), " &
" 177 (BC_1, EN1, INPUT, X ), " &
" 178 (BC_1, *, CONTROL, 1 ), " &
" 179 (BC_1, EN5, OUTPUT3, X , 178, 1, Z ), " &
" 180 (BC_1, EN5, INPUT, X ), " &
" 181 (BC_1, *, CONTROL, 1 ), " &
" 182 (BC_1, EN6, OUTPUT3, X , 181, 1, Z ), " &
" 183 (BC_1, EN6, INPUT, X ), " &
" 184 (BC_1, *, CONTROL, 1 ), " &
" 185 (BC_1, EN7, OUTPUT3, X , 184, 1, Z ), " &
" 186 (BC_1, EN7, INPUT, X ), " &
" 187 (BC_1, *, CONTROL, 1 ), " &
" 188 (BC_1, EN8, OUTPUT3, X , 187, 1, Z ), " &
" 189 (BC_1, EN8, INPUT, X ), " &
" 190 (BC_1, *, CONTROL, 1 ), " &
" 191 (BC_1, EN9, OUTPUT3, X , 190, 1, Z ), " &
" 192 (BC_1, EN9, INPUT, X ), " &
" 193 (BC_1, *, CONTROL, 1 ), " &
" 194 (BC_1, EN10, OUTPUT3, X , 193, 1, Z ), " &
" 195 (BC_1, EN10, INPUT, X ), " &
" 196 (BC_1, *, CONTROL, 1 ), " &
" 197 (BC_1, EN11, OUTPUT3, X , 196, 1, Z ), " &
" 198 (BC_1, EN11, INPUT, X ), " &
" 199 (BC_1, *, CONTROL, 1 ), " &
" 200 (BC_1, EN12, OUTPUT3, X , 199, 1, Z ), " &
" 201 (BC_1, EN12, INPUT, X ), " &
" 202 (BC_1, *, CONTROL, 1 ), " &
" 203 (BC_1, EN13, OUTPUT3, X , 202, 1, Z ), " &
" 204 (BC_1, EN13, INPUT, X ), " &
" 205 (BC_1, *, CONTROL, 1 ), " &
" 206 (BC_1, EN14, OUTPUT3, X , 205, 1, Z ), " &
" 207 (BC_1, EN14, INPUT, X ), " &
" 208 (BC_1, *, CONTROL, 1 ), " &
" 209 (BC_1, MAR12, OUTPUT3, X , 208, 1, Z ), " &
" 210 (BC_1, MAR12, INPUT, X ), " &
" 211 (BC_1, *, CONTROL, 1 ), " &
" 212 (BC_1, MAR11, OUTPUT3, X , 211, 1, Z ), " &
" 213 (BC_1, MAR11, INPUT, X ), " &
" 214 (BC_1, *, CONTROL, 1 ), " &
" 215 (BC_1, MAR10, OUTPUT3, X , 214, 1, Z ), " &
" 216 (BC_1, MAR10, INPUT, X ), " &
" 217 (BC_1, *, CONTROL, 1 ), " &
" 218 (BC_1, MAR9, OUTPUT3, X , 217, 1, Z ), " &
" 219 (BC_1, MAR9, INPUT, X ), " &
" 220 (BC_1, *, CONTROL, 1 ), " &
" 221 (BC_1, MAR8, OUTPUT3, X , 220, 1, Z ), " &
" 222 (BC_1, MAR8, INPUT, X ), " &
" 223 (BC_1, *, CONTROL, 1 ), " &
" 224 (BC_1, MAR4, OUTPUT3, X , 223, 1, Z ), " &
" 225 (BC_1, MAR4, INPUT, X ), " &
" 226 (BC_1, *, CONTROL, 1 ), " &
" 227 (BC_1, MAR2, OUTPUT3, X , 226, 1, Z ), " &
" 228 (BC_1, MAR2, INPUT, X ), " &
" 229 (BC_1, *, CONTROL, 1 ), " &
" 230 (BC_1, MAR23, OUTPUT3, X , 229, 1, Z ), " &
" 231 (BC_1, MAR23, INPUT, X ), " &
" 232 (BC_1, *, CONTROL, 1 ), " &
" 233 (BC_1, EN15, OUTPUT3, X , 232, 1, Z ), " &
" 234 (BC_1, EN15, INPUT, X ), " &
" 235 (BC_1, *, CONTROL, 1 ), " &
" 236 (BC_1, EN16, OUTPUT3, X , 235, 1, Z ), " &
" 237 (BC_1, EN16, INPUT, X ), " &
" 238 (BC_1, *, CONTROL, 1 ), " &
" 239 (BC_1, LGPO16, OUTPUT3, X , 238, 1, Z ), " &
" 240 (BC_1, LGPO16, INPUT, X ), " &
" 241 (BC_1, *, CONTROL, 1 ), " &
" 242 (BC_1, GPIO3, OUTPUT3, X , 241, 1, Z ), " &
" 243 (BC_1, GPIO3, INPUT, X ), " &
" 244 (BC_1, *, CONTROL, 1 ), " &
" 245 (BC_1, LGPO14, OUTPUT3, X , 244, 1, Z ), " &
" 246 (BC_1, LGPO14, INPUT, X ), " &
" 247 (BC_1, *, CONTROL, 1 ), " &
" 248 (BC_1, LGPO13, OUTPUT3, X , 247, 1, Z ), " &
" 249 (BC_1, LGPO13, INPUT, X ), " &
" 250 (BC_1, *, CONTROL, 1 ), " &
" 251 (BC_1, LGPO12, OUTPUT3, X , 250, 1, Z ), " &
" 252 (BC_1, LGPO12, INPUT, X ), " &
" 253 (BC_1, *, CONTROL, 1 ), " &
" 254 (BC_1, LGPO11, OUTPUT3, X , 253, 1, Z ), " &
" 255 (BC_1, LGPO11, INPUT, X ), " &
" 256 (BC_1, *, CONTROL, 1 ), " &
" 257 (BC_1, LGPO10, OUTPUT3, X , 256, 1, Z ), " &
" 258 (BC_1, LGPO10, INPUT, X ), " &
" 259 (BC_1, *, CONTROL, 1 ), " &
" 260 (BC_1, LGPO9, OUTPUT3, X , 259, 1, Z ), " &
" 261 (BC_1, LGPO9, INPUT, X ), " &
" 262 (BC_1, *, CONTROL, 1 ), " &
" 263 (BC_1, PMBUS_ADDR0, OUTPUT3, X , 262, 1, Z ), " &
" 264 (BC_1, PMBUS_ADDR0, INPUT, X ), " &
" 265 (BC_1, *, CONTROL, 1 ), " &
" 266 (BC_1, PMBUS_ADDR1, OUTPUT3, X , 265, 1, Z ), " &
" 267 (BC_1, PMBUS_ADDR1, INPUT, X ), " &
" 268 (BC_1, *, CONTROL, 1 ), " &
" 269 (BC_1, PMBUS_ADDR2, OUTPUT3, X , 268, 1, Z ), " &
" 270 (BC_1, PMBUS_ADDR2, INPUT, X ), " &
" 271 (BC_1, *, CONTROL, 1 ), " &
" 272 (BC_1, SYNC_CLK, OUTPUT3, X , 271, 1, Z ), " &
" 273 (BC_1, SYNC_CLK, INPUT, X ), " &
" 274 (BC_1, *, CONTROL, 1 ), " &
" 275 (BC_1, EN17, OUTPUT3, X , 274, 1, Z ), " &
" 276 (BC_1, EN17, INPUT, X ), " &
" 277 (BC_1, *, CONTROL, 1 ), " &
" 278 (BC_1, EN18, OUTPUT3, X , 277, 1, Z ), " &
" 279 (BC_1, EN18, INPUT, X ), " &
" 280 (BC_1, *, CONTROL, 1 ), " &
" 281 (BC_1, EN19, OUTPUT3, X , 280, 1, Z ), " &
" 282 (BC_1, EN19, INPUT, X ), " &
" 283 (BC_1, *, CONTROL, 1 ), " &
" 284 (BC_1, EN20, OUTPUT3, X , 283, 1, Z ), " &
" 285 (BC_1, EN20, INPUT, X ), " &
" 286 (BC_1, *, CONTROL, 1 ), " &
" 287 (BC_1, EN21, OUTPUT3, X , 286, 1, Z ), " &
" 288 (BC_1, EN21, INPUT, X ), " &
" 289 (BC_1, *, CONTROL, 1 ), " &
" 290 (BC_1, EN22, OUTPUT3, X , 289, 1, Z ), " &
" 291 (BC_1, EN22, INPUT, X ), " &
" 292 (BC_1, *, CONTROL, 1 ), " &
" 293 (BC_1, EN23, OUTPUT3, X , 292, 1, Z ), " &
" 294 (BC_1, EN23, INPUT, X ), " &
" 295 (BC_1, *, CONTROL, 1 ), " &
" 296 (BC_1, EN24, OUTPUT3, X , 295, 1, Z ), " &
" 297 (BC_1, EN24, INPUT, X ), " &
" 298 (BC_1, *, CONTROL, 1 ), " &
" 299 (BC_1, DMON3, OUTPUT3, X , 298, 1, Z ), " &
" 300 (BC_1, DMON3, INPUT, X ), " &
" 301 (BC_1, *, CONTROL, 1 ), " &
" 302 (BC_1, AMON20, OUTPUT3, X , 301, 1, Z ), " &
" 303 (BC_1, AMON20, INPUT, X ), " &
" 304 (BC_1, *, CONTROL, 1 ), " &
" 305 (BC_1, AMON19, OUTPUT3, X , 304, 1, Z ), " &
" 306 (BC_1, AMON19, INPUT, X ), " &
" 307 (BC_1, *, CONTROL, 1 ), " &
" 308 (BC_1, AMON18, OUTPUT3, X , 307, 1, Z ), " &
" 309 (BC_1, AMON18, INPUT, X ), " &
" 310 (BC_1, *, CONTROL, 1 ), " &
" 311 (BC_1, AMON17, OUTPUT3, X , 310, 1, Z ), " &
" 312 (BC_1, AMON17, INPUT, X ), " &
" 313 (BC_1, *, CONTROL, 1 ), " &
" 314 (BC_1, AMON4, OUTPUT3, X , 313, 1, Z ), " &
" 315 (BC_1, AMON4, INPUT, X ), " &
" 316 (BC_1, *, CONTROL, 1 ), " &
" 317 (BC_1, AMON3, OUTPUT3, X , 316, 1, Z ), " &
" 318 (BC_1, AMON3, INPUT, X ), " &
" 319 (BC_1, *, CONTROL, 1 ), " &
" 320 (BC_1, AMON2, OUTPUT3, X , 319, 1, Z ), " &
" 321 (BC_1, AMON2, INPUT, X ), " &
" 322 (BC_1, *, CONTROL, 1 ), " &
" 323 (BC_1, AMON1, OUTPUT3, X , 322, 1, Z ), " &
" 324 (BC_1, AMON1, INPUT, X ), " &
" 325 (BC_1, *, CONTROL, 1 ), " &
" 326 (BC_1, MAR7, OUTPUT3, X , 325, 1, Z ), " &
" 327 (BC_1, MAR7, INPUT, X ), " &
" 328 (BC_1, *, CONTROL, 1 ), " &
" 329 (BC_1, DMON2, OUTPUT3, X , 328, 1, Z ), " &
" 330 (BC_1, DMON2, INPUT, X ), " &
" 331 (BC_1, *, CONTROL, 1 ), " &
" 332 (BC_1, DMON1, OUTPUT3, X , 331, 1, Z ), " &
" 333 (BC_1, DMON1, INPUT, X ), " &
" 334 (BC_1, *, CONTROL, 1 ), " &
" 335 (BC_1, MAR6, OUTPUT3, X , 334, 1, Z ), " &
" 336 (BC_1, MAR6, INPUT, X ), " &
" 337 (BC_1, *, CONTROL, 1 ), " &
" 338 (BC_1, MAR5, OUTPUT3, X , 337, 1, Z ), " &
" 339 (BC_1, MAR5, INPUT, X ), " &
" 340 (BC_1, *, CONTROL, 1 ), " &
" 341 (BC_1, AMON13, OUTPUT3, X , 340, 1, Z ), " &
" 342 (BC_1, AMON13, INPUT, X ), " &
" 343 (BC_1, *, CONTROL, 1 ), " &
" 344 (BC_1, AMON14, OUTPUT3, X , 343, 1, Z ), " &
" 345 (BC_1, AMON14, INPUT, X ), " &
" 346 (BC_1, *, CONTROL, 1 ), " &
" 347 (BC_1, AMON15, OUTPUT3, X , 346, 1, Z ), " &
" 348 (BC_1, AMON15, INPUT, X ), " &
" 349 (BC_1, *, CONTROL, 1 ), " &
" 350 (BC_1, AMON16, OUTPUT3, X , 349, 1, Z ), " &
" 351 (BC_1, AMON16, INPUT, X ) ";
end UCD90320;
--