--*******************************************************************************************************
--** Copyright (c) 2002 Cypress Semiconductor
--** All rights reserved.
--**
--** File Name: 1381C_x36_119.bsdl
--** Release: 1.0
--** Last Updated: July 6 2005
--**
--** Part #: CY7C1381C
--** Package: 119-BGA
--** Function: 512K x 36 Synchronous Flowthrough SRAM, BSDL file for JTAG
--**
--** Notes: IMPORTANT NOTE: Please be aware that the CY7C1381C_119 device is NOT IEEE
--** 1149.1 compliant. (Refer to datasheet for more.)
--**
--** Written by : Cypress MPD Applications
--** Queries ? :contact Cypress MPD Applications
--** Reference CY7C1381C datasheet at http://www.cypress.com
--**
--*******************************************************************************************************
entity CY7C1381C_119 is
generic (PHYSICAL_PIN_MAP : string := "BGA");
port (
A: in bit_vector(0 to 18);
ADSC_n: in bit;
ADSP_n: in bit;
ADV_n: in bit;
BW_A_n: in bit;
BW_B_n: in bit;
BW_C_n: in bit;
BW_D_n: in bit;
BWE_n: in bit;
CE1_n: in bit;
CLK: in bit;
DQ_A: in bit_vector(0 to 7);
DQ_B: in bit_vector(0 to 7);
DQ_C: in bit_vector(0 to 7);
DQ_D: in bit_vector(0 to 7);
DP_A: in bit;
DP_B: in bit;
DP_C: in bit;
DP_D: in bit;
GW_n: in bit;
OE_n: in bit;
MODE: in bit;
TMS: in bit;
TDI: in bit;
TCK: in bit;
TDO: out bit;
ZZ: in bit;
VDD: linkage bit_vector(0 to 4);
VDDQ: linkage bit_vector(0 to 9);
VSS: linkage bit_vector(0 to 15);
NC: linkage bit_vector(0 to 14)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of CY7C1381C_119 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of CY7C1381C_119 : entity is PHYSICAL_PIN_MAP;
constant BGA:PIN_MAP_STRING:=
"A:(P4,N4,C6,A6,B5,B3,C5,C3,C2,A2,T4,B6,B2,R6, " &
" T5,T3,R2,A5,A3), " &-- Address
"ADSC_n: B4, " &
"ADSP_n: A4, " &
"ADV_n: G4, " &
"BW_A_n: L5, " &
"BW_B_n: G5, " &
"BW_C_n: G3, " &
"BW_D_n: L3, " &-- Byte Write
"BWE_n: M4, " &
"CE1_n: E4, " &
"CLK: K4, " & -- Clock
"DQ_A:(K7,L6,N6,P7,K6,L7,M6,N7), " &
"DQ_B:(D7,E6,G6,H7,E7,F6,G7,H6), " &
"DQ_C:(H1,G2,E2,D1,H2,G1,F2,E1), " &
"DQ_D:(P1,N2,L2,K1,N1,M2,L1,K2), " &
"DP_A: P6, " &
"DP_B: D6, " &
"DP_C: D2, " &
"DP_D: P2, " &
"GW_n:H4, " &
"OE_n:F4, " &
"MODE:R3, " &
"TMS: U2, " &
"TDI: U3, " &
"TCK: U4, " &
"TDO: U5, " &
"VDD: (C4,J2,J4,J6,R4), " &
"VDDQ:(A1,A7,F1,F7,J1,J7,M1,M7,U1,U7), " &
"VSS: (D3,D5,E3,E5,F3,F5,H3,H5,K3,K5, " &
" M3,M5,N3,N5,P3,P5), " &
"ZZ:T7, " &
"NC:(B1,B7,C1,C7,D4,J3,J5,L4,R1,R5,R7,T1,T2,T6,U6) ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);
attribute INSTRUCTION_LENGTH of CY7C1381C_119 : entity is 3;
attribute INSTRUCTION_OPCODE of CY7C1381C_119 : entity is
"EXTEST (000)," &
"IDCODE (001)," &
"SAMPLE (010)," &-- Sample-Z
"SAMPLD (100)," &-- Sample/Preload
"BYPASS (111) ";
attribute INSTRUCTION_CAPTURE of CY7C1381C_119: entity is "001";
attribute IDCODE_REGISTER of CY7C1381C_119 : entity is
"010"& -- Reserved for version number
"01010"& -- Defines the voltage of the part
"000001"& -- Defines the architecture of the part
"100101"& -- Defines the width and density of the part
"00000110100"& -- Manufacturer identity
"1"; -- ID register Presence indicator
attribute REGISTER_ACCESS of CY7C1381C_119 : entity is
"BOUNDARY (EXTEST,SAMPLE,SAMPLD)," &
"BYPASS (BYPASS)";
attribute BOUNDARY_LENGTH of CY7C1381C_119 : entity is 72;
attribute BOUNDARY_REGISTER of CY7C1381C_119 : entity is
"0 (BC_4, CLK, input, X)," &
"1 (BC_4, GW_n, input, X)," &
"2 (BC_4, BWE_n, input, X)," &
"3 (BC_4, OE_n, input, X)," &
"4 (BC_4, ADSC_n, input, X)," &
"5 (BC_4, ADSP_n, input, X)," &
"6 (BC_4, ADV_n, input, X)," &
"7 (BC_4, A(2), input, X)," &
"8 (BC_4, A(3), input, X)," &
"9 (BC_4, DP_B, input, X)," &
"10 (BC_4, DQ_B(0), input, X)," &
"11 (BC_4, DQ_B(1), input, X)," &
"12 (BC_4, DQ_B(2), input, X)," &
"13 (BC_4, DQ_B(3), input, X)," &
"14 (BC_4, DQ_B(4), input, X)," &
"15 (BC_4, DQ_B(5), input, X)," &
"16 (BC_4, DQ_B(6), input, X)," &
"17 (BC_4, DQ_B(7), input, X)," &
"18 (BC_4, ZZ, input, X)," &
"19 (BC_4, DQ_A(0), input, X)," &
"20 (BC_4, DQ_A(1), input, X)," &
"21 (BC_4, DQ_A(2), input, X)," &
"22 (BC_4, DQ_A(3), input, X)," &
"23 (BC_4, DQ_A(4), input, X)," &
"24 (BC_4, DQ_A(5), input, X)," &
"25 (BC_4, DQ_A(6), input, X)," &
"26 (BC_4, DQ_A(7), input, X)," &
"27 (BC_4, DP_A, input, X)," &
"28 (BC_4, A(4), input, X)," &
"29 (BC_4, A(5), input, X)," &
"30 (BC_4, A(6), input, X)," &
"31 (BC_4, A(7), input, X)," &
"32 (BC_4, A(8), input, X)," &
"33 (BC_4, A(9), input, X)," &
"34 (BC_4, A(10), input, X)," &
"35 (BC_4, A(11), input, X)," &
"36 (BC_4, A(12), input, X)," &
"37 (BC_4, A(0), input, X)," &
"38 (BC_4, A(1), input, X)," &
"39 (BC_4, A(13), input, X)," &
"40 (BC_4, A(14), input, X)," &
"41 (BC_4, A(15), input, X)," &
"42 (BC_4, A(16), input, X)," &
"43 (BC_4, MODE, input, X)," &
"44 (BC_4, DP_D, input, X)," &
"45 (BC_4, DQ_D(0), input, X)," &
"46 (BC_4, DQ_D(1), input, X)," &
"47 (BC_4, DQ_D(2), input, X)," &
"48 (BC_4, DQ_D(3), input, X)," &
"49 (BC_4, DQ_D(4), input, X)," &
"50 (BC_4, DQ_D(5), input, X)," &
"51 (BC_4, DQ_D(6), input, X)," &
"52 (BC_4, DQ_D(7), input, X)," &
"53 (BC_4, *, internal, X)," &
"54 (BC_4, DQ_C(0), input, X)," &
"55 (BC_4, DQ_C(1), input, X)," &
"56 (BC_4, DQ_C(2), input, X)," &
"57 (BC_4, DQ_C(3), input, X)," &
"58 (BC_4, DQ_C(4), input, X)," &
"59 (BC_4, DQ_C(5), input, X)," &
"60 (BC_4, DQ_C(6), input, X)," &
"61 (BC_4, DQ_C(7), input, X)," &
"62 (BC_4, DP_C, input, X)," &
"63 (BC_4, A(17), input, X)," &
"64 (BC_4, A(18), input, X)," &
"65 (BC_4, CE1_n, input, X)," &
"66 (BC_4, *, internal, X)," &
"67 (BC_4, BW_D_n, input, X)," &
"68 (BC_4, BW_C_n, input, X)," &
"69 (BC_4, BW_B_n, input, X)," &
"70 (BC_4, BW_A_n, input, X)," &
"71 (BC_4, *, internal, X)";
end CY7C1381C_119;