--*******************************************************************************************************
--** Copyright (c) 2000 Cypress Semiconductor
--** All rights reserved.
--**
--** File Name: cy7c1304v25.bsdl
--** Release: 1.0
--** Last Updated: July 31, 2000
--**
--** Function: 256x36 QDR SRAM, BSDL file for JTAG
--** Part #: CY7C1304V25
--**
--** Notes: IMPORTANT NOTE: Please be aware that the CY7C1304V25 QDR device is NOT IEEE
--** 1149.1 compliant. Therefore, the BSDL simulation file given below is intended as
--** an example.
--** Ref CY7C1304V25 Datasheet at www.cypress.com
--**
--** Queries ?: Contact MPD Applications at 408-943-2891 or e-mail: cyapps@cypress.com
--*******************************************************************************************************
entity CY7C1304V25 is
generic (PHYSICAL_PIN_MAP : string := "FBGA");
port (
A: in bit_vector(0 to 16);
BWS_b_0: in bit;
BWS_b_1: in bit;
C: in bit;
C_b: in bit;
D: in bit_vector(0 to 17);
K: in bit;
K_b: in bit;
RPS_b: in bit;
WPS_b: in bit;
Q: in bit_vector(0 to 17);
TMS: in bit;
TDI: in bit;
TCK: in bit;
TDO: out bit;
ZQ: linkage bit;
VREF: linkage bit_vector(0 to 1);
VDD: linkage bit_vector(0 to 10);
VSS: linkage bit_vector(0 to 26);
VDDQ: linkage bit_vector(0 to 15);
NC: linkage bit_vector(0 to 43)
);
use STD_1149_1_1994.all;
attribute PIN_MAP of CY7C1304V25 : entity is PHYSICAL_PIN_MAP;
constant FBGA:PIN_MAP_STRING:=
"A: (B4,B8,C5,C7,N5,N6,N7,P4,P5, " &
" P7,P8,R3,R4,R5,R7,R8,R9), " &
-- Address
"BWS_b_0: B7, " &
"BWS_b_1: A5, " & -- Byte Write
"C: P6, " & -- Positive Output Clock
"C_b: R6, " & -- Negative Output Clock
"D: (P10,N11,M11,K10,J11,G11,E10,D11,C11, " &
" B3,C3,D2,F3,G2,J3,L3,M3,N2), " &
-- Data In
"K: B6, " & -- Positive Input Clock
"K_b: A6, " & -- Negative Input Clock
"RPS_b: A8, " & -- Read Port Select
"WPS_b: A4, " & -- Write Port Select
"Q: (P11,M10,L11,K11,J10,F11,E11,C10,B11, " &
" B2,D3,E3,F2,G3,K3,L2,N3,P3), " &
"TMS: R10, " &
"TDI: R11, " &
"TCK: R2, " &
"TDO: R1, " &
"ZQ: H11, " &
"VREF: (H2,H10), " &
"VDD: (F5,F7,G5,G7,H5,H7,J5,J7,K5,K7), " &
"VSS: (A2,A10,C4,C8,D4,D5,D6,D7,D8,E5, " &
" E6,E7,F6,G6,H6,J6,K6,L5,L6,L7, " &
" M4,M5,M6,M7,M8,N4,N8), " &
"VDDQ: (E4,E8,F4,F8,G4,G8,H3,H4,H8,H9,J4,J8,K4,K8,L4,L8), " &
"NC: (A1,A3,A7,A9,A11,B1,B5,B9,B10,C1,C2,C6,C9,D1,D9,D10, " &
" E1,E2,E9,F1,F9,F10,G1,G9,G10,H1,J1,J2,J9, " &
" K1,K2,K9,L1,L9,L10,M1,M2,M9,N1,N9,N10,P1,P2,P9) ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of CY7C1304V25 : entity is 3;
attribute INSTRUCTION_OPCODE of CY7C1304V25 : entity is
"EXTEST (000)," &
"IDCODE (001)," &
"SAMPLE (010)," & -- Sample-Z
"SAMPLD (100)," & -- Sample/Preload
"BYPASS (111) ";
attribute INSTRUCTION_CAPTURE of CY7C1304V25 : entity is "001";
attribute IDCODE_REGISTER of CY7C1304V25 : entity is
"000" & -- Reserved for version number
"01011010011010110" & -- Defines the type of device
"00000110100" & -- Manufacturer identity
"1"; -- ID register Presence indicator
attribute REGISTER_ACCESS of CY7C1304V25 : entity is
"BOUNDARY (EXTEST,SAMPLE,SAMPLD)," &
"BYPASS (BYPASS)";
attribute BOUNDARY_LENGTH of CY7C1304V25 : entity is 69;
attribute BOUNDARY_REGISTER of CY7C1304V25 : entity is
"0 (BC_4, C_b, input, X)," &
"1 (BC_4, C, input, X)," &
"2 (BC_4, A(0), input, X)," &
"3 (BC_4, A(1), input, X)," &
"4 (BC_4, A(2), input, X)," &
"5 (BC_4, A(3), input, X)," &
"6 (BC_4, A(4), input, X)," &
"7 (BC_4, A(5), input, X)," &
"8 (BC_4, A(6), input, X)," &
"9 (BC_4, D(0), input, X)," &
"10 (BC_4, Q(0), input, X)," &
"11 (BC_4, D(1), input, X)," &
"12 (BC_4, Q(1), input, X)," &
"13 (BC_4, D(2), input, X)," &
"14 (BC_4, Q(2), input, X)," &
"15 (BC_4, D(3), input, X)," &
"16 (BC_4, Q(3), input, X)," &
"17 (BC_4, D(4), input, X)," &
"18 (BC_4, *, internal, X)," &
"19 (BC_4, Q(4), input, X)," &
"20 (BC_4, D(5), input, X)," &
"21 (BC_4, Q(5), input, X)," &
"22 (BC_4, D(6), input, X)," &
"23 (BC_4, Q(6), input, X)," &
"24 (BC_4, D(7), input, X)," &
"25 (BC_4, Q(7), input, X)," &
"26 (BC_4, D(8), input, X)," &
"27 (BC_4, Q(8), input, X)," &
"28 (BC_4, *, internal, X)," &
"29 (BC_4, *, internal, X)," &
"30 (BC_4, *, internal, X)," &
"31 (BC_4, A(7), input, X)," &
"32 (BC_4, A(8), input, X)," &
"33 (BC_4, *, internal, X)," &
"34 (BC_4, RPS_b, input, X)," &
"35 (BC_4, BWS_b_0, input, X)," &
"36 (BC_4, K, input, X)," &
"37 (BC_4, K_b, input, X)," &
"38 (BC_4, BWS_b_1, input, X)," &
"39 (BC_4, WPS_b, input, X)," &
"40 (BC_4, A(9), input, X)," &
"41 (BC_4, A(10), input, X)," &
"42 (BC_4, *, internal, X)," &
"43 (BC_4, *, internal, X)," &
"44 (BC_4, *, internal, X)," &
"45 (BC_4, D(9), input, X)," &
"46 (BC_4, Q(9), input, X)," &
"47 (BC_4, D(10), input, X)," &
"48 (BC_4, Q(10), input, X)," &
"49 (BC_4, D(11), input, X)," &
"50 (BC_4, Q(11), input, X)," &
"51 (BC_4, D(12), input, X)," &
"52 (BC_4, Q(12), input, X)," &
"53 (BC_4, D(13), input, X)," &
"54 (BC_4, Q(13), input, X)," &
"55 (BC_4, D(14), input, X)," &
"56 (BC_4, Q(14), input, X)," &
"57 (BC_4, D(15), input, X)," &
"58 (BC_4, Q(15), input, X)," &
"59 (BC_4, D(16), input, X)," &
"60 (BC_4, Q(16), input, X)," &
"61 (BC_4, D(17), input, X)," &
"62 (BC_4, Q(17), input, X)," &
"63 (BC_4, A(11), input, X)," &
"64 (BC_4, A(12), input, X)," &
"65 (BC_4, A(13), input, X)," &
"66 (BC_4, A(14), input, X)," &
"67 (BC_4, A(15), input, X)," &
"68 (BC_4, A(16), input, X) ";
end CY7C1304V25;