BSDL Files Library for JTAG
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BSDL File: JX_Processor Download View details  


--****************************************************************************
-- Intel Corporation makes no warranty for the use of this products
-- and assumes no responsibility for any errors which may appear in
-- this document nor does it make a commitment to update the information
-- contained herein.
--****************************************************************************
-- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto
-- standard means of describing essential features of ANSI/IEEE 1149.1-1990
-- compliant devices.  This language is under consideration by the IEEE for
-- formal inclusion within a supplement to the 1149.1-1990 standard.  The
-- generation of the supplement entails an extensive IEEE review and a formal
-- acceptance balloting procedure which may change the resultant form of the
-- language.  Be aware that this process may extend well into 1993, and at
-- this time the IEEE does not endorse or hold an opinion on the language.
--****************************************************************************
--
-- i960(R) Processor BSDL Model
-- File **NOT** verified electrically
-- ---------------------------------------------------------

entity JX_Processor is
   generic(PHYSICAL_PIN_MAP : string := "PBGA_196");
port(TDI                : in bit;
     RDYRCVBAR          : in bit;
     Reserved1           : in bit;
     Reserved2          : in bit;
     Reserved3          : in bit;
     TRSTBAR            : in bit;
     TCK                : in bit;
     TMS                : in bit;
     HOLD               : in bit;
     XINTBARX           : in bit_vector(0 to 7);
     NMIBAR             : in bit;
     Reserved4          : in bit;
     Reserved5          : in bit;
     Reserved6          : in bit;
     Reserved7      	: out bit;
     FAILBAR            : out bit;
     ALEBAR             : out bit;
     TDO                : out bit;
     WIDTH              : out bit_vector(1 downto 0);
     A32                : out bit_vector(0 to 1);
     Reserved8          : out bit;
     Reserved9          : out bit;
     Reserved10         : out bit;
     Reserved11           : out bit;
     BLASTBAR           : out bit;
     DCBAR              : out bit;
     ADSBAR             : out bit;
     WRBAR              : out bit;
     DTRBAR             : out bit;
     DENBAR             : out bit;
     HOLDA              : out bit;
     ALE                : out bit;
     LOCKONCEBAR        : inout bit;
     BSTAT              : out bit;
     BEBAR              : out bit_vector(0 to 3);
     Reserved12           : in bit;
     Reserved13           : in bit;
     Reserved14           : in bit;
     Reserved15           : inout bit_vector(7 downto 0);
     AD                 : inout bit_vector(31 downto 0);
     CLKIN              : in bit;
     Reserved16           : in bit;
     Reserved17           : in bit;
     Reserved18           : in bit;
     RESETBAR           : in bit;
     Reserved19           : in bit;
     STEST              : in bit;
     VCC                : linkage bit_vector(0 to 24);
     VSS                : linkage bit_vector(0 to 24);
     AVCC               : linkage bit;
     NC                 : linkage bit_vector(1 to 3));
   use STD_1149_1_1990.all;
   use i960jx_a.all;
--This list describes the physical pin layout of all signals
   attribute PIN_MAP of JX_Processor : entity is PHYSICAL_PIN_MAP;
   constant PBGA_196 : PIN_MAP_STRING :=        -- Define PinOut of PBGA
        "TDI          : J12,"&
        "RDYRCVBAR    : L14,"&
        "TRSTBAR      : M13,"&
        "TCK          : M14,"&
        "TMS          : M12,"&
        "HOLD         : N14,"&
        "XINTBARX     : (M11, N12, M10, N13, N09, P12, N11, P11),"&
        "NMIBAR       : P10,"&
        "FAILBAR      : P07,"&
        "ALEBAR       : M07,"&
        "TDO          : N07,"&
        "WIDTH        : (P05, P06),"&
        "A32          : (N05, M05),"&
        "BLASTBAR     : P03,"&
        "DCBAR        : N02,"&
        "ADSBAR       : P02,"&
        "WRBAR        : N01,"&
        "DTRBAR       : M01,"&
        "DENBAR       : L02,"&
        "HOLDA        : L01,"&
        "ALE          : K01,"&
        "LOCKONCEBAR  : K02,"&
        "BSTAT        : J03,"&
        "BEBAR        : (J02, H01, H02, H03),"&
        "AD           : (C02, B02, B04, A02, B03, C04, C05, C06, B06, A06,"&
        "                C07, B07, C08, A08, B08, C09, A10, B09, A11, B10,"&
        "                C12, B11, B12, A13, B13, C13, D12, B14, D11, C14,"&
        "                D14, D13),"&
        "CLKIN        : G13,"&
        "RESETBAR     : J14,"&
        "STEST        : K14,"&
        "VCC          : (P13, P04, N06, M09, M06, M02, L03, K13, K03, J01," &
        "               H13, GO3, F13, F12, F03, E14, E13, E12, E03, C11," &
        "               C10, B05, B01, A12, A09, A07, A05, A03)," &
        "VSS          : (L11, L10, L09, L08, L07, L06, L05, L04, K11," &
        "               K10, K09, K08, K07, K06, K05, K04, J11, J10, J09," &
        "               J08, J07, J06, J05, J04, H11, H10, H09, H08, H07, H06, H05, H04," &
                        G11, G10, G09, G08, G07, G06, G05, G04, F11, F10, F09, F08, F07, " &
                        F06, F05, F04, E11, E10, E09, E08, E07, E06, E05, E04, " &
                        D10, D09, D08, D07, D06, D05, D04)," &
        "AVCC         : F14 ";
   attribute Tap_Scan_In    of  TDI   : signal is true;
   attribute Tap_Scan_Mode  of  TMS   : signal is true;
   attribute Tap_Scan_Out   of  TDO   : signal is true;
   attribute Tap_Scan_Reset of  TRSTBAR  : signal is true;
   attribute Tap_Scan_Clock of  TCK   : signal is (33.0e6, BOTH);
   attribute Instruction_Length of JX_Processor: entity is 4;
   attribute Instruction_Opcode of JX_Processor: entity is
      "BYPASS   (1111)," &
      "EXTEST   (0000)," &
      "SAMPLE   (0001)," &
      "IDCODE   (0010)," &
      "RUNBIST  (0111)," &
      "Reserved (1100, 1011)";
attribute Instruction_Capture of JX_Processor: entity is "0001";
   -- there is no Instruction_Disable attribute for JX_Processor
   attribute Instruction_Private of JX_Processor: entity is "Reserved" ;
   --attribute Instruction_Usage of JX_Processor: entity is
   --   "RUNBIST (registers Runbist; "  &
   --   "result 0;"                  &
   --   "clock CLK in Run_Test_Idle;"&
   --   "length 524288)";
   -- attribute Idcode_Register of JX_Processor: entity is
   --    "0000"                  &  --version, A-step
   --    "0000001010100001"      &  --part number
   --    "00000001001"           &  --manufacturers identity
   --    "1";                       --required by the standard
   -- attribute Idcode_Register of JX_Processor: entity is
   --    "0010"                  &  --version, B-step
   --    "0000001010110001"      &  --part number B0primeprime
   --    "00000001001"           &  --manufacturers identity
   --    "1";                       --required by the standard
   attribute Idcode_Register of JX_Processor: entity is
      "0011"                  &  --version, C-Step
      "0000100000110011"      &  --part number ??
      "00000001001"           &  --manufacturers identity
      "1";                       --required by the standard
   attribute Register_Access of JX_Processor: entity is
        "Runbist[1]     (RUNBIST)";
--{*******************************************************************}
--{  The first cell, cell 0, is closest to TD0                        }
--{  BC_4:Input  BC_1: Output3, Bidirectional                         }
--{*******************************************************************}
attribute Boundary_Cells of JX_Processor: entity is "CBSC_1, BC_1";
   attribute Boundary_Length of JX_Processor: entity is 70;
   attribute Boundary_Register of JX_Processor: entity is
     "0 (BC_1, STEST, input, X)," &
     "1 (BC_1, RESETBAR, input, X)," &
     "2 (BC_1, CLKIN, input, X)," &
     "3 (CBSC_1, AD(0), bidir, X, 15, 1, Z)," &
     "4 (CBSC_1, AD(1), bidir, X, 15, 1, Z)," &
     "5 (CBSC_1, AD(2), bidir, X, 15, 1, Z)," &
     "6 (CBSC_1, AD(3), bidir, X, 15, 1, Z)," &
     "7 (CBSC_1, AD(4), bidir, X, 15, 1, Z)," &
     "8 (CBSC_1, AD(5), bidir, X, 15, 1, Z)," &
     "9 (CBSC_1, AD(6), bidir, X, 15, 1, Z)," &
     "10 (CBSC_1, AD(7), bidir, X, 15, 1, Z)," &
     "11 (CBSC_1, AD(8), bidir, X, 15, 1, Z)," &
     "12 (CBSC_1, AD(9), bidir, X, 15, 1, Z)," &
     "13 (CBSC_1, AD(10), bidir, X, 15, 1, Z)," &
     "14 (CBSC_1, AD(11), bidir, X, 15, 1, Z)," &
     "15 (BC_1, *, control, 1)," &
     "16 (CBSC_1, AD(12), bidir, X, 15, 1, Z)," &
     "17 (CBSC_1, AD(13), bidir, X, 15, 1, Z)," &
     "18 (CBSC_1, AD(14), bidir, X, 15, 1, Z)," &
     "19 (CBSC_1, AD(15), bidir, X, 15, 1, Z)," &
     "20 (CBSC_1, AD(16), bidir, X, 15, 1, Z)," &
     "21 (CBSC_1, AD(17), bidir, X, 15, 1, Z)," &
     "22 (CBSC_1, AD(18), bidir, X, 15, 1, Z)," &
     "23 (CBSC_1, AD(19), bidir, X, 15, 1, Z)," &
     "24 (CBSC_1, AD(20), bidir, X, 15, 1, Z)," &
     "25 (CBSC_1, AD(21), bidir, X, 15, 1, Z)," &
     "26 (CBSC_1, AD(22), bidir, X, 15, 1, Z)," &
     "27 (CBSC_1, AD(23), bidir, X, 15, 1, Z)," &
     "28 (CBSC_1, AD(24), bidir, X, 15, 1, Z)," &
     "29 (CBSC_1, AD(25), bidir, X, 15, 1, Z)," &
     "30 (CBSC_1, AD(26), bidir, X, 15, 1, Z)," &
     "31 (CBSC_1, AD(27), bidir, X, 15, 1, Z)," &
     "32 (CBSC_1, AD(28), bidir, X, 15, 1, Z)," &
     "33 (CBSC_1, AD(29), bidir, X, 15, 1, Z)," &
     "34 (CBSC_1, AD(30), bidir, X, 15, 1, Z)," &
     "35 (CBSC_1, AD(31), bidir, X, 15, 1, Z)," &
     "36 (BC_1, BEBAR(3), output3, X, 51, 1, Z)," &
     "37 (BC_1, BEBAR(2), output3, X, 51, 1, Z)," &
     "38 (BC_1, BEBAR(1), output3, X, 51, 1, Z)," &
     "39 (BC_1, BEBAR(0), output3, X, 51, 1, Z)," &
     "40 (BC_1, BSTAT, output3, X, 52, 1, Z)," &
     "41 (CBSC_1, LOCKONCEBAR, bidir, X, 42, 1, Z)," &
     "42 (BC_1, *, control, 1)," &
     "43 (BC_1, ALE, output3, X, 51, 1, Z)," &
     "44 (BC_1, HOLDA, output3, X, 52, 1, Z)," &
     "45 (BC_1, DENBAR, output3, X, 51, 1, Z)," &
     "46 (BC_1, DTRBAR, output3, X, 51, 1, Z)," &
     "47 (BC_1, WRBAR, output3, X, 51, 1, Z)," &
     "48 (BC_1, ADSBAR, output3, X, 51, 1, Z)," &
     "49 (BC_1, DCBAR, output3, X, 51, 1, Z)," &
     "50 (BC_1, BLASTBAR, output3, X, 51, 1, Z)," &
     "51 (BC_1, *, control, 1)," &
     "52 (BC_1, *, control, 1)," &
     "53 (BC_1, A32(1), output3, X, 51, 1, Z)," &
     "54 (BC_1, A32(0), output3, X, 51, 1, Z)," &
     "55 (BC_1, WIDTH(0), output3, X, 51, 1, Z)," &
     "56 (BC_1, WIDTH(1), output3, X, 51, 1, Z)," &
     "57 (BC_1, ALEBAR, output3, X, 51, 1, Z)," &
     "58 (BC_1, FAILBAR, output3, X, 52, 1, Z)," &
     "59 (BC_1, NMIBAR, input, X)," &
     "60 (BC_1, XINTBARX(7), input, X)," &
     "61 (BC_1, XINTBARX(6), input, X)," &
     "62 (BC_1, XINTBARX(5), input, X)," &
     "63 (BC_1, XINTBARX(4), input, X)," &
     "64 (BC_1, XINTBARX(3), input, X)," &
     "65 (BC_1, XINTBARX(2), input, X)," &
     "66 (BC_1, XINTBARX(1), input, X)," &
     "67 (BC_1, XINTBARX(0), input, X)," &
     "68 (BC_1, HOLD, input, X)," &
     "69 (BC_1, RDYRCVBAR, input, X)";
     end JX_Processor;


This library contains 7815 BSDL files (for 6182 distinct entities) from 66 vendors
Last BSDL model (PIC24FJ64GA002) was added on Nov 10, 2017 08:41
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