-------------------------------------------------------------------------------
-- TI TMS320DM335 Fixed-Point DSP with Boundary Scan --
-------------------------------------------------------------------------------
-- Supported Devices: TMS320DM335 Revision 1.0 --
-------------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320DM335 Users Guide --
-- BSDL Revision : 0.2 --
-- --
-- BSDL Status : Preliminary --
-- Date Created : 07/01/2008 --
-- --
-------------------------------------------------------------------------------
-- --
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-------------------------------------------------------------------------------
entity TMS320DM335 is
generic(PHYSICAL_PIN_MAP : string := "ZCE");
port(
CAM_HD : inout bit;
CAM_VD : inout bit;
CAM_WEN_FIELD : inout bit;
CIN0 : inout bit;
CIN1 : inout bit;
CIN2 : inout bit;
CIN3 : inout bit;
CIN4 : inout bit;
CIN5 : inout bit;
CIN6 : inout bit;
CIN7 : inout bit;
CLKOUT1 : inout bit;
CLKOUT2 : inout bit;
CLKOUT3 : inout bit;
COUT0 : inout bit;
COUT1 : inout bit;
COUT2 : inout bit;
COUT3 : inout bit;
COUT4 : inout bit;
COUT5 : inout bit;
COUT6 : inout bit;
COUT7 : inout bit;
DDR_A00 : inout bit;
DDR_A01 : inout bit;
DDR_A02 : inout bit;
DDR_A03 : inout bit;
DDR_A04 : inout bit;
DDR_A05 : inout bit;
DDR_A06 : inout bit;
DDR_A07 : inout bit;
DDR_A08 : inout bit;
DDR_A09 : inout bit;
DDR_A10 : inout bit;
DDR_A11 : inout bit;
DDR_A12 : inout bit;
DDR_A13 : inout bit;
DDR_BA0 : inout bit;
DDR_BA1 : inout bit;
DDR_BA2 : inout bit;
DDR_CASN : inout bit;
DDR_CKE : inout bit;
DDR_CLKN : inout bit;
DDR_CLKP : inout bit;
DDR_CSN : inout bit;
DDR_DQ00 : inout bit;
DDR_DQ01 : inout bit;
DDR_DQ02 : inout bit;
DDR_DQ03 : inout bit;
DDR_DQ04 : inout bit;
DDR_DQ05 : inout bit;
DDR_DQ06 : inout bit;
DDR_DQ07 : inout bit;
DDR_DQ08 : inout bit;
DDR_DQ09 : inout bit;
DDR_DQ10 : inout bit;
DDR_DQ11 : inout bit;
DDR_DQ12 : inout bit;
DDR_DQ13 : inout bit;
DDR_DQ14 : inout bit;
DDR_DQ15 : inout bit;
DDR_DQM0 : inout bit;
DDR_DQM1 : inout bit;
DDR_DQS0 : inout bit;
DDR_DQS1 : inout bit;
DDR_RASN : inout bit;
DDR_WEN : inout bit;
EM_A00 : inout bit;
EM_A01 : inout bit;
EM_A02 : inout bit;
EM_A03 : inout bit;
EM_A04 : inout bit;
EM_A05 : inout bit;
EM_A06 : inout bit;
EM_A07 : inout bit;
EM_A08 : inout bit;
EM_A09 : inout bit;
EM_A10 : inout bit;
EM_A11 : inout bit;
EM_A12 : inout bit;
EM_A13 : inout bit;
EM_ADV : inout bit;
EM_BA0 : inout bit;
EM_BA1 : inout bit;
EM_CE0 : inout bit;
EM_CE1 : inout bit;
EM_CLK : inout bit;
EM_D00 : inout bit;
EM_D01 : inout bit;
EM_D02 : inout bit;
EM_D03 : inout bit;
EM_D04 : inout bit;
EM_D05 : inout bit;
EM_D06 : inout bit;
EM_D07 : inout bit;
EM_D08 : inout bit;
EM_D09 : inout bit;
EM_D10 : inout bit;
EM_D11 : inout bit;
EM_D12 : inout bit;
EM_D13 : inout bit;
EM_D14 : inout bit;
EM_D15 : inout bit;
EM_OE : inout bit;
EM_WAIT : inout bit;
EM_WE : inout bit;
GIO000 : inout bit;
GIO001 : inout bit;
GIO002 : inout bit;
GIO003 : inout bit;
GIO004 : inout bit;
GIO005 : inout bit;
GIO006 : inout bit;
GIO007 : inout bit;
HSYNC : inout bit;
VSYNC : inout bit;
PCLK : inout bit;
VCLK : inout bit;
I2C_SCL : inout bit;
I2C_SDA : inout bit;
ASP0_CLKR : inout bit;
ASP0_CLKX : inout bit;
ASP0_DR : inout bit;
ASP0_DX : inout bit;
ASP0_FSR : inout bit;
ASP0_FSX : inout bit;
ASP1_CLKR : inout bit;
ASP1_CLKX : inout bit;
ASP1_DR : inout bit;
ASP1_DX : inout bit;
ASP1_FSR : inout bit;
ASP1_FSX : inout bit;
ASP1_CLKS : in bit;
MMCSD0_CLK : inout bit;
MMCSD0_CMD : inout bit;
MMCSD0_DATA0 : inout bit;
MMCSD0_DATA1 : inout bit;
MMCSD0_DATA2 : inout bit;
MMCSD0_DATA3 : inout bit;
MMCSD1_CLK : inout bit;
MMCSD1_CMD : inout bit;
MMCSD1_DATA0 : inout bit;
MMCSD1_DATA1 : inout bit;
MMCSD1_DATA2 : inout bit;
MMCSD1_DATA3 : inout bit;
SPI0_SCLK : inout bit;
SPI0_SDENA0 : inout bit;
SPI0_SDI : inout bit;
SPI0_SDO : inout bit;
SPI1_SCLK : inout bit;
SPI1_SDENA0 : inout bit;
SPI1_SDI : inout bit;
SPI1_SDO : inout bit;
UART0_RXD : in bit;
UART0_TXD : out bit;
UART1_RXD : inout bit;
UART1_TXD : inout bit;
YIN0 : inout bit;
YIN1 : inout bit;
YIN2 : inout bit;
YIN3 : inout bit;
YIN4 : inout bit;
YIN5 : inout bit;
YIN6 : inout bit;
YIN7 : inout bit;
YOUT0 : inout bit;
YOUT1 : inout bit;
YOUT2 : inout bit;
YOUT3 : inout bit;
YOUT4 : inout bit;
YOUT5 : inout bit;
YOUT6 : inout bit;
YOUT7 : inout bit;
RESETN : in bit;
EXTCLK : inout bit;
FIELD : inout bit;
TRSTN : in bit;
TCK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
EMU0 : in bit; -- B.8.10.3.d compliance pins must be type in
EMU1 : in bit; -- B.8.10.3.d compliance pins must be type in
LCD_OE : inout bit;
USB_DRVVBUS : out bit;
-- DDR_GATE0 : inout bit;
-- DDR_GATE1 : inout bit;
-- DDR_ZN : out bit;
-- IBIAS : inout bit;
-- IOUT : inout bit;
-- MXI1 : in bit;
-- MXI2 : in bit;
-- MXO1 : out bit;
-- MXO2 : out bit;
-- NC : inout bit;
-- RTCK : out bit;
-- RSV01 : inout bit;
-- RSV02 : inout bit;
-- RSV03 : inout bit;
-- RSV04 : inout bit;
-- RSV05 : inout bit;
-- RSV06 : inout bit;
-- RSV07 : inout bit;
-- TVOUT : inout bit;
-- USB_DM : inout bit;
-- USB_DP : inout bit;
-- USB_ID : inout bit;
-- USB_R1 : inout bit;
-- USB_VBUS : inout bit;
-- VFB : inout bit;
-- VREF : inout bit;
VSS : linkage bit_vector(1 to 62);
VDD : linkage bit_vector(1 to 65));
use STD_1149_1_2001.all; -- Get standard attributes and definitions
attribute COMPONENT_CONFORMANCE of TMS320DM335: entity is
"STD_1149_1_2001";
attribute PIN_MAP of TMS320DM335: entity is PHYSICAL_PIN_MAP;
constant ZCE : PIN_MAP_STRING :=
"CAM_HD :N5," &
"CAM_VD :R4," &
"CAM_WEN_FIELD :R5," &
"CIN0 :J3," &
"CIN1 :L3," &
"CIN2 :J5," &
"CIN3 :J4," &
"CIN4 :L4," &
"CIN5 :M3," &
"CIN6 :K5," &
"CIN7 :N3," &
"CLKOUT1 :D12," &
"CLKOUT2 :A11," &
"CLKOUT3 :C11," &
"COUT0 :F4," &
"COUT1 :F3," &
"COUT2 :E4," &
"COUT3 :E3," &
"COUT4 :D3," &
"COUT5 :C1," &
"COUT6 :D2," &
"COUT7 :C2," &
"DDR_A00 :V2," &
"DDR_A01 :V3," &
"DDR_A02 :W2," &
"DDR_A03 :W3," &
"DDR_A04 :V4," &
"DDR_A05 :W4," &
"DDR_A06 :U5," &
"DDR_A07 :V5," &
"DDR_A08 :W5," &
"DDR_A09 :W6," &
"DDR_A10 :V6," &
"DDR_A11 :W7," &
"DDR_A12 :V7," &
"DDR_A13 :U6," &
"DDR_BA0 :U8," &
"DDR_BA1 :U7," &
"DDR_BA2 :V8," &
"DDR_CASN :V9," &
"DDR_CKE :V10," &
"DDR_CLKN :W8," &
"DDR_CLKP :W9," &
"DDR_CSN :T8," &
"DDR_DQ00 :V11," &
"DDR_DQ01 :W11," &
"DDR_DQ02 :U11," &
"DDR_DQ03 :T11," &
"DDR_DQ04 :U12," &
"DDR_DQ05 :W12," &
"DDR_DQ06 :V13," &
"DDR_DQ07 :W13," &
"DDR_DQ08 :U13," &
"DDR_DQ09 :V14," &
"DDR_DQ10 :W14," &
"DDR_DQ11 :W15," &
"DDR_DQ12 :U16," &
"DDR_DQ13 :W16," &
"DDR_DQ14 :V16," &
"DDR_DQ15 :W17," &
"DDR_DQM0 :T12," &
"DDR_DQM1 :U15," &
"DDR_DQS0 :V12," &
"DDR_DQS1 :V15," &
"DDR_RASN :T6," &
"DDR_WEN :W10," &
"EM_A00 :M16," &
"EM_A01 :N17," &
"EM_A02 :N15," &
"EM_A03 :N18," &
"EM_A04 :P15," &
"EM_A05 :R19," &
"EM_A06 :P18," &
"EM_A07 :P16," &
"EM_A08 :T19," &
"EM_A09 :P17," &
"EM_A10 :R18," &
"EM_A11 :R16," &
"EM_A12 :U19," &
"EM_A13 :V19," &
"EM_ADV :H16," &
"EM_BA0 :N19," &
"EM_BA1 :P19," &
"EM_CE0 :J16," &
"EM_CE1 :G19," &
"EM_CLK :E19," &
"EM_D00 :H18," &
"EM_D01 :J17," &
"EM_D02 :H19," &
"EM_D03 :J18," &
"EM_D04 :L15," &
"EM_D05 :J19," &
"EM_D06 :K17," &
"EM_D07 :K19," &
"EM_D08 :L16," &
"EM_D09 :K18," &
"EM_D10 :L19," &
"EM_D11 :L17," &
"EM_D12 :L18," &
"EM_D13 :M15," &
"EM_D14 :M19," &
"EM_D15 :M18," &
"EM_OE :F19," &
"EM_WAIT :G18," &
"EM_WE :J15," &
"EMU0 :E8," &
"EMU1 :E7," &
"EXTCLK :G3," &
"FIELD :H4," &
"GIO000 :C16," &
"GIO001 :E14," &
"GIO002 :F15," &
"GIO003 :G15," &
"GIO004 :B17," &
"GIO005 :D15," &
"GIO006 :B18," &
"GIO007 :C17," &
"HSYNC :F5," &
"LCD_OE :H5," &
"PCLK :T3," &
"VCLK :H3," &
"I2C_SCL :R14," &
"I2C_SDA :R13," &
"ASP0_CLKR :F17," &
"ASP0_CLKX :F18," &
"ASP0_DR :E18," &
"ASP0_DX :H15," &
"ASP0_FSR :F16," &
"ASP0_FSX :G17," &
"ASP1_CLKR :D18," &
"ASP1_CLKS :D17," &
"ASP1_CLKX :D19," &
"ASP1_DR :C19," &
"ASP1_DX :C18," &
"ASP1_FSR :E17," &
"ASP1_FSX :E16," &
"TRSTN :C9," &
"RESETN :D11," &
"MMCSD0_CLK :A15," &
"MMCSD0_CMD :C14," &
"MMCSD0_DATA0 :B14," &
"MMCSD0_DATA1 :D14," &
"MMCSD0_DATA2 :B13," &
"MMCSD0_DATA3 :A14," &
"MMCSD1_CLK :C15," &
"MMCSD1_CMD :A17," &
"MMCSD1_DATA0 :A18," &
"MMCSD1_DATA1 :B15," &
"MMCSD1_DATA2 :A16," &
"MMCSD1_DATA3 :B16," &
"SPI0_SCLK :C12," &
"SPI0_SDENA0 :B12," &
"SPI0_SDI :A12," &
"SPI0_SDO :B11," &
"SPI1_SCLK :C13," &
"SPI1_SDENA0 :E13," &
"SPI1_SDI :A13," &
"SPI1_SDO :E12," &
"TCK :E10," &
"TDI :D9," &
"TDO :E9," &
"TMS :D8," &
"UART0_RXD :U18," &
"UART0_TXD :T18," &
"UART1_RXD :R15," &
"UART1_TXD :R17," &
"USB_DRVVBUS :C5," &
"VSYNC :G5," &
"YIN0 :P5," &
"YIN1 :P2," &
"YIN2 :P4," &
"YIN3 :R3," &
"YIN4 :P3," &
"YIN5 :M5," &
"YIN6 :M4," &
"YIN7 :L5," &
"YOUT0 :B1," &
"YOUT1 :A2," &
"YOUT2 :A3," &
"YOUT3 :B2," &
"YOUT4 :B3," &
"YOUT5 :B4," &
"YOUT6 :A4," &
"YOUT7 :C3," &
-- "DDR_DQGATE0 :W18," &
-- "DDR_DQGATE1 :V17," &
-- "DDR_ZN :T9," &
-- "IBIAS :F2," &
-- "IOUT :E1," &
-- "MXI1 :A9," &
-- "MXI2 :R1," &
-- "MXO1 :B9," &
-- "MXO2 :T1," &
-- "NC :H8," &
-- "RTCK :E11," &
-- "RSV01 :J1," &
-- "RSV02 :K1," &
-- "RSV03 :L1," &
-- "RSV04 :M1," &
-- "RSV05 :N2," &
-- "RSV06 :M2," &
-- "RSV07 :K2," &
-- "TVOUT :F1," &
-- "USB_DM :A6," &
-- "USB_DP :A7," &
-- "USB_ID :D5," &
-- "USB_R1 :C7," &
-- "USB_VBUS :E5," &
-- "VFB :G1," &
-- "VREF :J7," &
"VSS :(A5, A8, A19, B5, B8, B10, D1, E2, E15, G2, G9, H1, H2, H6, H11, H14," &
"J2, J6, J10, J14, K3, K9, K10, K14, L2, L9, L10, L14, M6, M7, M8, M14," &
"M17, N1, N8, N9, N14, R2, R6, T2, T5, T15, U1, U2, U3, U4, U9, U14, U17," &
"V1, V18, W1, L8, R11, H12, J9, E6, B7, D6, C8, P1, C10),"&
"VDD :(A1, A10, B19, C4, G6, G11, H10, H13, H17, J11, J12, J13, K6, K11," &
"K12, L11, L12, N6, R7, R8, T17, W19, G12, H9, L7, H7, J8, R10," &
"B6, C6, M9, P9, P10, P11, P12, P13, P14, R9, R12, T14, F9, F10, F11," &
"F12, F13, F14, G8, G14, K15, L13, M10, M11, M12, M13, N11, N12, L6," &
"K8, P6, P7, P8, F6, F7, F8, U10)";
-- *********************************************************
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTN : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of TMS320DM335: entity is "(EMU1,EMU0)(11)";
attribute INSTRUCTION_LENGTH of TMS320DM335: entity is 6;
attribute INSTRUCTION_OPCODE of TMS320DM335: entity is
"EXTEST (011000), " &
"BYPASS (111111), " &
"HIGHZ (011110), " &
"PRELOAD (011100), " &
"IDCODE (000100), " &
"SAMPLE (011011), " &
"PRIVATE (000000, " &
" 000001, " &
" 000010, " &
" 000011, " &
" 000101, " &
" 000110, " &
" 000111, " &
" 001000, " &
" 001001, " &
" 001010, " &
" 001011, " &
" 001100, " &
" 001101, " &
" 001110, " &
" 001111, " &
" 010000, " &
" 010001, " &
" 010010, " &
" 010011, " &
" 010100, " &
" 010101, " &
" 010110, " &
" 010111, " &
" 011001, " &
" 011010, " &
" 011101, " &
" 011111, " &
" 100000, " &
" 100001, " &
" 100010, " &
" 100011, " &
" 100100, " &
" 100101, " &
" 100110, " &
" 100111, " &
" 101000, " &
" 101001, " &
" 101010, " &
" 101011, " &
" 101100, " &
" 101101, " &
" 101110, " &
" 101111, " &
" 110000, " &
" 110001, " &
" 110010, " &
" 110011, " &
" 110100, " &
" 110101, " &
" 110110, " &
" 110111, " &
" 111000, " &
" 111001, " &
" 111010, " &
" 111011, " &
" 111100, " &
" 111101, " &
" 111110) " ;
attribute INSTRUCTION_CAPTURE of TMS320DM335: entity is "XXXX01";
attribute INSTRUCTION_PRIVATE of TMS320DM335: entity is "PRIVATE";
-- Do not support SAMPLE on DDR outputs
-- Do not support INTEST on DDR inputs
attribute IDCODE_REGISTER of TMS320DM335: entity is
"0000" & -- Version number
"1011011100111011" & -- Part number -- DM350 pin package ID
"00000010111" & -- Manufacturer ID -- Texas Instruments
"1"; -- Required by IEEE Std.
attribute REGISTER_ACCESS of TMS320DM335: entity is
"BOUNDARY (EXTEST, PRELOAD, SAMPLE)," &
"BYPASS (BYPASS, HIGHZ) " ;
attribute BOUNDARY_LENGTH of TMS320DM335: entity is 523;
attribute BOUNDARY_REGISTER of TMS320DM335: entity is
--- num cell port function safe ccell disval rslt
"0 (bc_1, *, control, 1)," &
"1 (bc_1, CLKOUT3, output3, X, 0, 1, Z)," &
"2 (bc_1, CLKOUT3, input, X)," &
"3 (bc_1, RESETN, input, X)," &
"4 (bc_1, *, control, 1)," &
"5 (bc_1, CLKOUT2, output3, X, 4, 1, Z)," &
"6 (bc_1, CLKOUT2, input, X)," &
"7 (bc_1, *, control, 1)," &
"8 (bc_1, CLKOUT1, output3, X, 7, 1, Z)," &
"9 (bc_1, CLKOUT1, input, X)," &
"10 (bc_1, *, control, 1)," &
"11 (bc_1, SPI0_SDO, output3, X, 10, 1, Z)," &
"12 (bc_1, SPI0_SDO, input, X)," &
"13 (bc_1, *, control, 1)," &
"14 (bc_1, SPI0_SDI, output3, X, 13, 1, Z)," &
"15 (bc_1, SPI0_SDI, input, X)," &
"16 (bc_1, *, control, 1)," &
"17 (bc_1, SPI0_SCLK, output3, X, 16, 1, Z)," &
"18 (bc_1, SPI0_SCLK, input, X)," &
"19 (bc_1, *, control, 1)," &
"20 (bc_1, SPI0_SDENA0, output3, X, 19, 1, Z)," &
"21 (bc_1, SPI0_SDENA0, input, X)," &
"22 (bc_1, *, control, 1)," &
"23 (bc_1, SPI1_SDO, output3, X, 22, 1, Z)," &
"24 (bc_1, SPI1_SDO, input, X)," &
"25 (bc_1, *, control, 1)," &
"26 (bc_1, SPI1_SDI, output3, X, 25, 1, Z)," &
"27 (bc_1, SPI1_SDI, input, X)," &
"28 (bc_1, *, control, 1)," &
"29 (bc_1, SPI1_SCLK, output3, X, 28, 1, Z)," &
"30 (bc_1, SPI1_SCLK, input, X)," &
"31 (bc_1, *, control, 1)," &
"32 (bc_1, SPI1_SDENA0, output3, X, 31, 1, Z)," &
"33 (bc_1, SPI1_SDENA0, input, X)," &
"34 (bc_1, *, control, 1)," &
"35 (bc_1, MMCSD0_DATA0, output3, X, 34, 1, Z)," &
"36 (bc_1, MMCSD0_DATA0, input, X)," &
"37 (bc_1, *, control, 1)," &
"38 (bc_1, MMCSD0_DATA1, output3, X, 37, 1, Z)," &
"39 (bc_1, MMCSD0_DATA1, input, X)," &
"40 (bc_1, *, control, 1)," &
"41 (bc_1, MMCSD0_DATA2, output3, X, 40, 1, Z)," &
"42 (bc_1, MMCSD0_DATA2, input, X)," &
"43 (bc_1, *, control, 1)," &
"44 (bc_1, MMCSD0_DATA3, output3, X, 43, 1, Z)," &
"45 (bc_1, MMCSD0_DATA3, input, X)," &
"46 (bc_1, *, control, 1)," &
"47 (bc_1, MMCSD0_CMD, output3, X, 46, 1, Z)," &
"48 (bc_1, MMCSD0_CMD, input, X)," &
"49 (bc_1, *, control, 1)," &
"50 (bc_1, MMCSD0_CLK, output3, X, 49, 1, Z)," &
"51 (bc_1, MMCSD0_CLK, input, X)," &
"52 (bc_1, *, control, 1)," &
"53 (bc_1, MMCSD1_DATA0, output3, X, 52, 1, Z)," &
"54 (bc_1, MMCSD1_DATA0, input, X)," &
"55 (bc_1, *, control, 1)," &
"56 (bc_1, MMCSD1_DATA1, output3, X, 55, 1, Z)," &
"57 (bc_1, MMCSD1_DATA1, input, X)," &
"58 (bc_1, *, control, 1)," &
"59 (bc_1, MMCSD1_DATA2, output3, X, 58, 1, Z)," &
"60 (bc_1, MMCSD1_DATA2, input, X)," &
"61 (bc_1, *, control, 1)," &
"62 (bc_1, MMCSD1_DATA3, output3, X, 61, 1, Z)," &
"63 (bc_1, MMCSD1_DATA3, input, X)," &
"64 (bc_1, *, control, 1)," &
"65 (bc_1, MMCSD1_CMD, output3, X, 64, 1, Z)," &
"66 (bc_1, MMCSD1_CMD, input, X)," &
"67 (bc_1, *, control, 1)," &
"68 (bc_1, MMCSD1_CLK, output3, X, 67, 1, Z)," &
"69 (bc_1, MMCSD1_CLK, input, X)," &
"70 (bc_1, *, control, 1)," &
"71 (bc_1, GIO000, output3, X, 70, 1, Z)," &
"72 (bc_1, GIO000, input, X)," &
"73 (bc_1, *, control, 1)," &
"74 (bc_1, GIO001, output3, X, 73, 1, Z)," &
"75 (bc_1, GIO001, input, X)," &
"76 (bc_1, *, control, 1)," &
"77 (bc_1, GIO002, output3, X, 76, 1, Z)," &
"78 (bc_1, GIO002, input, X)," &
"79 (bc_1, *, control, 1)," &
"80 (bc_1, GIO003, output3, X, 79, 1, Z)," &
"81 (bc_1, GIO003, input, X)," &
"82 (bc_1, *, control, 1)," &
"83 (bc_1, GIO004, output3, X, 82, 1, Z)," &
"84 (bc_1, GIO004, input, X)," &
"85 (bc_1, *, control, 1)," &
"86 (bc_1, GIO005, output3, X, 85, 1, Z)," &
"87 (bc_1, GIO005, input, X)," &
"88 (bc_1, *, control, 1)," &
"89 (bc_1, GIO006, output3, X, 88, 1, Z)," &
"90 (bc_1, GIO006, input, X)," &
"91 (bc_1, *, control, 1)," &
"92 (bc_1, GIO007, output3, X, 91, 1, Z)," &
"93 (bc_1, GIO007, input, X)," &
"94 (bc_1, *, control, 1)," &
"95 (bc_1, ASP1_DR, output3, X, 94, 1, Z)," &
"96 (bc_1, ASP1_DR, input, X)," &
"97 (bc_1, *, control, 1)," &
"98 (bc_1, ASP1_DX, output3, X, 97, 1, Z)," &
"99 (bc_1, ASP1_DX, input, X)," &
"100 (bc_1, *, control, 1)," &
"101 (bc_1, ASP1_CLKR, output3, X, 100, 1, Z)," &
"102 (bc_1, ASP1_CLKR, input, X)," &
"103 (bc_1, *, control, 1)," &
"104 (bc_1, ASP1_CLKX, output3, X, 103, 1, Z)," &
"105 (bc_1, ASP1_CLKX, input, X)," &
"106 (bc_1, ASP1_CLKS, input, X)," &
"107 (bc_1, *, control, 1)," &
"108 (bc_1, ASP1_FSR, output3, X, 107, 1, Z)," &
"109 (bc_1, ASP1_FSR, input, X)," &
"110 (bc_1, *, control, 1)," &
"111 (bc_1, ASP1_FSX, output3, X, 110, 1, Z)," &
"112 (bc_1, ASP1_FSX, input, X)," &
"113 (bc_1, *, control, 1)," &
"114 (bc_1, ASP0_FSR, output3, X, 113, 1, Z)," &
"115 (bc_1, ASP0_FSR, input, X)," &
"116 (bc_1, *, control, 1)," &
"117 (bc_1, ASP0_CLKR, output3, X, 116, 1, Z)," &
"118 (bc_1, ASP0_CLKR, input, X)," &
"119 (bc_1, *, control, 1)," &
"120 (bc_1, ASP0_DR, output3, X, 119, 1, Z)," &
"121 (bc_1, ASP0_DR, input, X)," &
"122 (bc_1, *, control, 1)," &
"123 (bc_1, ASP0_FSX, output3, X, 122, 1, Z)," &
"124 (bc_1, ASP0_FSX, input, X)," &
"125 (bc_1, *, control, 1)," &
"126 (bc_1, ASP0_CLKX, output3, X, 125, 1, Z)," &
"127 (bc_1, ASP0_CLKX, input, X)," &
"128 (bc_1, *, control, 1)," &
"129 (bc_1, ASP0_DX, output3, X, 128, 1, Z)," &
"130 (bc_1, ASP0_DX, input, X)," &
"131 (bc_1, *, control, 1)," &
"132 (bc_1, EM_CLK, output3, X, 131, 1, Z)," &
"133 (bc_1, EM_CLK, input, X)," &
"134 (bc_1, *, control, 1)," &
"135 (bc_1, EM_ADV, output3, X, 134, 1, Z)," &
"136 (bc_1, EM_ADV, input, X)," &
"137 (bc_1, *, control, 1)," &
"138 (bc_1, EM_WAIT, output3, X, 137, 1, Z)," &
"139 (bc_1, EM_WAIT, input, X)," &
"140 (bc_1, *, control, 1)," &
"141 (bc_1, EM_OE, output3, X, 140, 1, Z)," &
"142 (bc_1, EM_OE, input, X)," &
"143 (bc_1, *, control, 1)," &
"144 (bc_1, EM_WE, output3, X, 143, 1, Z)," &
"145 (bc_1, EM_WE, input, X)," &
"146 (bc_1, *, control, 1)," &
"147 (bc_1, EM_CE1, output3, X, 146, 1, Z)," &
"148 (bc_1, EM_CE1, input, X)," &
"149 (bc_1, *, control, 1)," &
"150 (bc_1, EM_CE0, output3, X, 149, 1, Z)," &
"151 (bc_1, EM_CE0, input, X)," &
"152 (bc_1, *, control, 1)," &
"153 (bc_1, EM_D00, output3, X, 152, 1, Z)," &
"154 (bc_1, EM_D00, input, X)," &
"155 (bc_1, *, control, 1)," &
"156 (bc_1, EM_D01, output3, X, 155, 1, Z)," &
"157 (bc_1, EM_D01, input, X)," &
"158 (bc_1, *, control, 1)," &
"159 (bc_1, EM_D02, output3, X, 158, 1, Z)," &
"160 (bc_1, EM_D02, input, X)," &
"161 (bc_1, *, control, 1)," &
"162 (bc_1, EM_D03, output3, X, 161, 1, Z)," &
"163 (bc_1, EM_D03, input, X)," &
"164 (bc_1, *, control, 1)," &
"165 (bc_1, EM_D04, output3, X, 164, 1, Z)," &
"166 (bc_1, EM_D04, input, X)," &
"167 (bc_1, *, control, 1)," &
"168 (bc_1, EM_D05, output3, X, 167, 1, Z)," &
"169 (bc_1, EM_D05, input, X)," &
"170 (bc_1, *, control, 1)," &
"171 (bc_1, EM_D06, output3, X, 170, 1, Z)," &
"172 (bc_1, EM_D06, input, X)," &
"173 (bc_1, *, control, 1)," &
"174 (bc_1, EM_D07, output3, X, 173, 1, Z)," &
"175 (bc_1, EM_D07, input, X)," &
"176 (bc_1, *, control, 1)," &
"177 (bc_1, EM_D08, output3, X, 176, 1, Z)," &
"178 (bc_1, EM_D08, input, X)," &
"179 (bc_1, *, control, 1)," &
"180 (bc_1, EM_D09, output3, X, 179, 1, Z)," &
"181 (bc_1, EM_D09, input, X)," &
"182 (bc_1, *, control, 1)," &
"183 (bc_1, EM_D10, output3, X, 182, 1, Z)," &
"184 (bc_1, EM_D10, input, X)," &
"185 (bc_1, *, control, 1)," &
"186 (bc_1, EM_D11, output3, X, 185, 1, Z)," &
"187 (bc_1, EM_D11, input, X)," &
"188 (bc_1, *, control, 1)," &
"189 (bc_1, EM_D12, output3, X, 188, 1, Z)," &
"190 (bc_1, EM_D12, input, X)," &
"191 (bc_1, *, control, 1)," &
"192 (bc_1, EM_D13, output3, X, 191, 1, Z)," &
"193 (bc_1, EM_D13, input, X)," &
"194 (bc_1, *, control, 1)," &
"195 (bc_1, EM_D14, output3, X, 194, 1, Z)," &
"196 (bc_1, EM_D14, input, X)," &
"197 (bc_1, *, control, 1)," &
"198 (bc_1, EM_D15, output3, X, 197, 1, Z)," &
"199 (bc_1, EM_D15, input, X)," &
"200 (bc_1, *, control, 1)," &
"201 (bc_1, EM_BA0, output3, X, 200, 1, Z)," &
"202 (bc_1, EM_BA0, input, X)," &
"203 (bc_1, *, control, 1)," &
"204 (bc_1, EM_BA1, output3, X, 203, 1, Z)," &
"205 (bc_1, EM_BA1, input, X)," &
"206 (bc_1, *, control, 1)," &
"207 (bc_1, EM_A00, output3, X, 206, 1, Z)," &
"208 (bc_1, EM_A00, input, X)," &
"209 (bc_1, *, control, 1)," &
"210 (bc_1, EM_A01, output3, X, 209, 1, Z)," &
"211 (bc_1, EM_A01, input, X)," &
"212 (bc_1, *, control, 1)," &
"213 (bc_1, EM_A02, output3, X, 212, 1, Z)," &
"214 (bc_1, EM_A02, input, X)," &
"215 (bc_1, *, control, 1)," &
"216 (bc_1, EM_A03, output3, X, 215, 1, Z)," &
"217 (bc_1, EM_A03, input, X)," &
"218 (bc_1, *, control, 1)," &
"219 (bc_1, EM_A04, output3, X, 218, 1, Z)," &
"220 (bc_1, EM_A04, input, X)," &
"221 (bc_1, *, control, 1)," &
"222 (bc_1, EM_A05, output3, X, 221, 1, Z)," &
"223 (bc_1, EM_A05, input, X)," &
"224 (bc_1, *, control, 1)," &
"225 (bc_1, EM_A06, output3, X, 224, 1, Z)," &
"226 (bc_1, EM_A06, input, X)," &
"227 (bc_1, *, control, 1)," &
"228 (bc_1, EM_A07, output3, X, 227, 1, Z)," &
"229 (bc_1, EM_A07, input, X)," &
"230 (bc_1, *, control, 1)," &
"231 (bc_1, EM_A08, output3, X, 230, 1, Z)," &
"232 (bc_1, EM_A08, input, X)," &
"233 (bc_1, *, control, 1)," &
"234 (bc_1, EM_A09, output3, X, 233, 1, Z)," &
"235 (bc_1, EM_A09, input, X)," &
"236 (bc_1, *, control, 1)," &
"237 (bc_1, EM_A10, output3, X, 236, 1, Z)," &
"238 (bc_1, EM_A10, input, X)," &
"239 (bc_1, *, control, 1)," &
"240 (bc_1, EM_A11, output3, X, 239, 1, Z)," &
"241 (bc_1, EM_A11, input, X)," &
"242 (bc_1, *, control, 1)," &
"243 (bc_1, EM_A12, output3, X, 242, 1, Z)," &
"244 (bc_1, EM_A12, input, X)," &
"245 (bc_1, *, control, 1)," &
"246 (bc_1, EM_A13, output3, X, 245, 1, Z)," &
"247 (bc_1, EM_A13, input, X)," &
"248 (bc_1, *, control, 1)," &
"249 (bc_1, UART1_TXD, output3, X, 248, 1, Z)," &
"250 (bc_1, UART1_TXD, input, X)," &
"251 (bc_1, *, control, 1)," &
"252 (bc_1, UART1_RXD, output3, X, 251, 1, Z)," &
"253 (bc_1, UART1_RXD, input, X)," &
"254 (bc_1, *, control, 1)," &
"255 (bc_1, UART0_TXD, output3, X, 254, 1, Z)," &
"256 (bc_1, UART0_RXD, input, X)," &
"257 (bc_4, *, internal, 0)," &
"258 (bc_1, I2C_SCL, output2, 1, 258, 1, Weak1)," &
"259 (bc_1, I2C_SCL, input, X)," &
"260 (bc_4, *, internal, 0)," &
"261 (bc_1, I2C_SDA, output2, 1, 261, 1, Weak1)," &
"262 (bc_1, I2C_SDA, input, X)," &
"263 (bc_1, *, control, 1)," &
"264 (bc_1, DDR_DQ15, output3, X, 263, 1, Z)," &
"265 (bc_1, DDR_DQ15, input, X)," &
"266 (bc_1, *, control, 1)," &
"267 (bc_1, DDR_DQ14, output3, X, 266, 1, Z)," &
"268 (bc_1, DDR_DQ14, input, X)," &
"269 (bc_1, *, control, 1)," &
"270 (bc_1, DDR_DQ13, output3, X, 269, 1, Z)," &
"271 (bc_1, DDR_DQ13, input, X)," &
"272 (bc_1, *, control, 1)," &
"273 (bc_1, DDR_DQ12, output3, X, 272, 1, Z)," &
"274 (bc_1, DDR_DQ12, input, X)," &
"275 (bc_1, *, control, 1)," &
"276 (bc_1, DDR_DQM1, output3, X, 275, 1, Z)," &
"277 (bc_1, DDR_DQM1, input, X)," &
"278 (bc_1, *, control, 1)," &
"279 (bc_1, DDR_DQS1, output3, X, 278, 1, Z)," &
"280 (bc_1, DDR_DQS1, input, X)," &
"281 (bc_1, *, control, 1)," &
"282 (bc_1, DDR_DQ11, output3, X, 281, 1, Z)," &
"283 (bc_1, DDR_DQ11, input, X)," &
"284 (bc_1, *, control, 1)," &
"285 (bc_1, DDR_DQ10, output3, X, 284, 1, Z)," &
"286 (bc_1, DDR_DQ10, input, X)," &
"287 (bc_1, *, control, 1)," &
"288 (bc_1, DDR_DQ09, output3, X, 287, 1, Z)," &
"289 (bc_1, DDR_DQ09, input, X)," &
"290 (bc_1, *, control, 1)," &
"291 (bc_1, DDR_DQ08, output3, X, 290, 1, Z)," &
"292 (bc_1, DDR_DQ08, input, X)," &
"293 (bc_1, *, control, 1)," &
"294 (bc_1, DDR_DQ07, output3, X, 293, 1, Z)," &
"295 (bc_1, DDR_DQ07, input, X)," &
"296 (bc_1, *, control, 1)," &
"297 (bc_1, DDR_DQ06, output3, X, 296, 1, Z)," &
"298 (bc_1, DDR_DQ06, input, X)," &
"299 (bc_1, *, control, 1)," &
"300 (bc_1, DDR_DQ05, output3, X, 299, 1, Z)," &
"301 (bc_1, DDR_DQ05, input, X)," &
"302 (bc_1, *, control, 1)," &
"303 (bc_1, DDR_DQ04, output3, X, 302, 1, Z)," &
"304 (bc_1, DDR_DQ04, input, X)," &
"305 (bc_1, *, control, 1)," &
"306 (bc_1, DDR_DQS0, output3, X, 305, 1, Z)," &
"307 (bc_1, DDR_DQS0, input, X)," &
"308 (bc_1, *, control, 1)," &
"309 (bc_1, DDR_DQM0, output3, X, 308, 1, Z)," &
"310 (bc_1, DDR_DQM0, input, X)," &
"311 (bc_1, *, control, 1)," &
"312 (bc_1, DDR_DQ03, output3, X, 311, 1, Z)," &
"313 (bc_1, DDR_DQ03, input, X)," &
"314 (bc_1, *, control, 1)," &
"315 (bc_1, DDR_DQ02, output3, X, 314, 1, Z)," &
"316 (bc_1, DDR_DQ02, input, X)," &
"317 (bc_1, *, control, 1)," &
"318 (bc_1, DDR_DQ01, output3, X, 317, 1, Z)," &
"319 (bc_1, DDR_DQ01, input, X)," &
"320 (bc_1, *, control, 1)," &
"321 (bc_1, DDR_DQ00, output3, X, 320, 1, Z)," &
"322 (bc_1, DDR_DQ00, input, X)," &
"323 (bc_1, *, control, 1)," &
"324 (bc_1, DDR_CLKP, output3, X, 323, 1, Z)," &
"325 (bc_1, DDR_CLKP, input, X)," &
"326 (bc_1, *, control, 1)," &
"327 (bc_1, DDR_CLKN, output3, X, 326, 1, Z)," &
"328 (bc_1, DDR_CLKN, input, X)," &
"329 (bc_1, *, control, 1)," &
"330 (bc_1, DDR_CASN, output3, X, 329, 1, Z)," &
"331 (bc_1, DDR_CASN, input, X)," &
"332 (bc_1, *, control, 1)," &
"333 (bc_1, DDR_RASN, output3, X, 332, 1, Z)," &
"334 (bc_1, DDR_RASN, input, X)," &
"335 (bc_1, *, control, 1)," &
"336 (bc_1, DDR_WEN, output3, X, 335, 1, Z)," &
"337 (bc_1, DDR_WEN, input, X)," &
"338 (bc_1, *, control, 1)," &
"339 (bc_1, DDR_CSN, output3, X, 338, 1, Z)," &
"340 (bc_1, DDR_CSN, input, X)," &
"341 (bc_1, *, control, 1)," &
"342 (bc_1, DDR_CKE, output3, X, 341, 1, Z)," &
"343 (bc_1, DDR_CKE, input, X)," &
"344 (bc_1, *, control, 1)," &
"345 (bc_1, DDR_BA2, output3, X, 344, 1, Z)," &
"346 (bc_1, DDR_BA2, input, X)," &
"347 (bc_1, *, control, 1)," &
"348 (bc_1, DDR_BA1, output3, X, 347, 1, Z)," &
"349 (bc_1, DDR_BA1, input, X)," &
"350 (bc_1, *, control, 1)," &
"351 (bc_1, DDR_BA0, output3, X, 350, 1, Z)," &
"352 (bc_1, DDR_BA0, input, X)," &
"353 (bc_1, *, control, 1)," &
"354 (bc_1, DDR_A13, output3, X, 353, 1, Z)," &
"355 (bc_1, DDR_A13, input, X)," &
"356 (bc_1, *, control, 1)," &
"357 (bc_1, DDR_A12, output3, X, 356, 1, Z)," &
"358 (bc_1, DDR_A12, input, X)," &
"359 (bc_1, *, control, 1)," &
"360 (bc_1, DDR_A11, output3, X, 359, 1, Z)," &
"361 (bc_1, DDR_A11, input, X)," &
"362 (bc_1, *, control, 1)," &
"363 (bc_1, DDR_A10, output3, X, 362, 1, Z)," &
"364 (bc_1, DDR_A10, input, X)," &
"365 (bc_1, *, control, 1)," &
"366 (bc_1, DDR_A09, output3, X, 365, 1, Z)," &
"367 (bc_1, DDR_A09, input, X)," &
"368 (bc_1, *, control, 1)," &
"369 (bc_1, DDR_A08, output3, X, 368, 1, Z)," &
"370 (bc_1, DDR_A08, input, X)," &
"371 (bc_1, *, control, 1)," &
"372 (bc_1, DDR_A07, output3, X, 371, 1, Z)," &
"373 (bc_1, DDR_A07, input, X)," &
"374 (bc_1, *, control, 1)," &
"375 (bc_1, DDR_A06, output3, X, 374, 1, Z)," &
"376 (bc_1, DDR_A06, input, X)," &
"377 (bc_1, *, control, 1)," &
"378 (bc_1, DDR_A05, output3, X, 377, 1, Z)," &
"379 (bc_1, DDR_A05, input, X)," &
"380 (bc_1, *, control, 1)," &
"381 (bc_1, DDR_A04, output3, X, 380, 1, Z)," &
"382 (bc_1, DDR_A04, input, X)," &
"383 (bc_1, *, control, 1)," &
"384 (bc_1, DDR_A03, output3, X, 383, 1, Z)," &
"385 (bc_1, DDR_A03, input, X)," &
"386 (bc_1, *, control, 1)," &
"387 (bc_1, DDR_A02, output3, X, 386, 1, Z)," &
"388 (bc_1, DDR_A02, input, X)," &
"389 (bc_1, *, control, 1)," &
"390 (bc_1, DDR_A01, output3, X, 389, 1, Z)," &
"391 (bc_1, DDR_A01, input, X)," &
"392 (bc_1, *, control, 1)," &
"393 (bc_1, DDR_A00, output3, X, 392, 1, Z)," &
"394 (bc_1, DDR_A00, input, X)," &
"395 (bc_1, *, control, 1)," &
"396 (bc_1, PCLK, output3, X, 395, 1, Z)," &
"397 (bc_1, PCLK, input, X)," &
"398 (bc_1, *, control, 1)," &
"399 (bc_1, CAM_WEN_FIELD, output3, X, 398, 1, Z)," &
"400 (bc_1, CAM_WEN_FIELD, input, X)," &
"401 (bc_1, *, control, 1)," &
"402 (bc_1, CAM_VD, output3, X, 401, 1, Z)," &
"403 (bc_1, CAM_VD, input, X)," &
"404 (bc_1, *, control, 1)," &
"405 (bc_1, CAM_HD, output3, X, 404, 1, Z)," &
"406 (bc_1, CAM_HD, input, X)," &
"407 (bc_1, *, control, 1)," &
"408 (bc_1, YIN0, output3, X, 407, 1, Z)," &
"409 (bc_1, YIN0, input, X)," &
"410 (bc_1, *, control, 1)," &
"411 (bc_1, YIN1, output3, X, 410, 1, Z)," &
"412 (bc_1, YIN1, input, X)," &
"413 (bc_1, *, control, 1)," &
"414 (bc_1, YIN2, output3, X, 413, 1, Z)," &
"415 (bc_1, YIN2, input, X)," &
"416 (bc_1, *, control, 1)," &
"417 (bc_1, YIN3, output3, X, 416, 1, Z)," &
"418 (bc_1, YIN3, input, X)," &
"419 (bc_1, *, control, 1)," &
"420 (bc_1, YIN4, output3, X, 419, 1, Z)," &
"421 (bc_1, YIN4, input, X)," &
"422 (bc_1, *, control, 1)," &
"423 (bc_1, YIN5, output3, X, 422, 1, Z)," &
"424 (bc_1, YIN5, input, X)," &
"425 (bc_1, *, control, 1)," &
"426 (bc_1, YIN6, output3, X, 425, 1, Z)," &
"427 (bc_1, YIN6, input, X)," &
"428 (bc_1, *, control, 1)," &
"429 (bc_1, YIN7, output3, X, 428, 1, Z)," &
"430 (bc_1, YIN7, input, X)," &
"431 (bc_1, *, control, 1)," &
"432 (bc_1, CIN7, output3, X, 431, 1, Z)," &
"433 (bc_1, CIN7, input, X)," &
"434 (bc_1, *, control, 1)," &
"435 (bc_1, CIN6, output3, X, 434, 1, Z)," &
"436 (bc_1, CIN6, input, X)," &
"437 (bc_1, *, control, 1)," &
"438 (bc_1, CIN5, output3, X, 437, 1, Z)," &
"439 (bc_1, CIN5, input, X)," &
"440 (bc_1, *, control, 1)," &
"441 (bc_1, CIN4, output3, X, 440, 1, Z)," &
"442 (bc_1, CIN4, input, X)," &
"443 (bc_1, *, control, 1)," &
"444 (bc_1, CIN3, output3, X, 443, 1, Z)," &
"445 (bc_1, CIN3, input, X)," &
"446 (bc_1, *, control, 1)," &
"447 (bc_1, CIN2, output3, X, 446, 1, Z)," &
"448 (bc_1, CIN2, input, X)," &
"449 (bc_1, *, control, 1)," &
"450 (bc_1, CIN1, output3, X, 449, 1, Z)," &
"451 (bc_1, CIN1, input, X)," &
"452 (bc_1, *, control, 1)," &
"453 (bc_1, CIN0, output3, X, 452, 1, Z)," &
"454 (bc_1, CIN0, input, X)," &
"455 (bc_1, *, control, 1)," &
"456 (bc_1, VCLK, output3, X, 455, 1, Z)," &
"457 (bc_1, VCLK, input, X)," &
"458 (bc_1, *, control, 1)," &
"459 (bc_1, EXTCLK, output3, X, 458, 1, Z)," &
"460 (bc_1, EXTCLK, input, X)," &
"461 (bc_1, *, control, 1)," &
"462 (bc_1, FIELD, output3, X, 461, 1, Z)," &
"463 (bc_1, FIELD, input, X)," &
"464 (bc_1, *, control, 1)," &
"465 (bc_1, LCD_OE, output3, X, 464, 1, Z)," &
"466 (bc_1, LCD_OE, input, X)," &
"467 (bc_1, *, control, 1)," &
"468 (bc_1, VSYNC, output3, X, 467, 1, Z)," &
"469 (bc_1, VSYNC, input, X)," &
"470 (bc_1, *, control, 1)," &
"471 (bc_1, HSYNC, output3, X, 470, 1, Z)," &
"472 (bc_1, HSYNC, input, X)," &
"473 (bc_1, *, control, 1)," &
"474 (bc_1, COUT0, output3, X, 473, 1, Z)," &
"475 (bc_1, COUT0, input, X)," &
"476 (bc_1, *, control, 1)," &
"477 (bc_1, COUT1, output3, X, 476, 1, Z)," &
"478 (bc_1, COUT1, input, X)," &
"479 (bc_1, *, control, 1)," &
"480 (bc_1, COUT2, output3, X, 479, 1, Z)," &
"481 (bc_1, COUT2, input, X)," &
"482 (bc_1, *, control, 1)," &
"483 (bc_1, COUT3, output3, X, 482, 1, Z)," &
"484 (bc_1, COUT3, input, X)," &
"485 (bc_1, *, control, 1)," &
"486 (bc_1, COUT4, output3, X, 485, 1, Z)," &
"487 (bc_1, COUT4, input, X)," &
"488 (bc_1, *, control, 1)," &
"489 (bc_1, COUT5, output3, X, 488, 1, Z)," &
"490 (bc_1, COUT5, input, X)," &
"491 (bc_1, *, control, 1)," &
"492 (bc_1, COUT6, output3, X, 491, 1, Z)," &
"493 (bc_1, COUT6, input, X)," &
"494 (bc_1, *, control, 1)," &
"495 (bc_1, COUT7, output3, X, 494, 1, Z)," &
"496 (bc_1, COUT7, input, X)," &
"497 (bc_1, *, control, 1)," &
"498 (bc_1, YOUT0, output3, X, 497, 1, Z)," &
"499 (bc_1, YOUT0, input, X)," &
"500 (bc_1, *, control, 1)," &
"501 (bc_1, YOUT1, output3, X, 500, 1, Z)," &
"502 (bc_1, YOUT1, input, X)," &
"503 (bc_1, *, control, 1)," &
"504 (bc_1, YOUT2, output3, X, 503, 1, Z)," &
"505 (bc_1, YOUT2, input, X)," &
"506 (bc_1, *, control, 1)," &
"507 (bc_1, YOUT3, output3, X, 506, 1, Z)," &
"508 (bc_1, YOUT3, input, X)," &
"509 (bc_1, *, control, 1)," &
"510 (bc_1, YOUT4, output3, X, 509, 1, Z)," &
"511 (bc_1, YOUT4, input, X)," &
"512 (bc_1, *, control, 1)," &
"513 (bc_1, YOUT5, output3, X, 512, 1, Z)," &
"514 (bc_1, YOUT5, input, X)," &
"515 (bc_1, *, control, 1)," &
"516 (bc_1, YOUT6, output3, X, 515, 1, Z)," &
"517 (bc_1, YOUT6, input, X)," &
"518 (bc_1, *, control, 1)," &
"519 (bc_1, YOUT7, output3, X, 518, 1, Z)," &
"520 (bc_1, YOUT7, input, X)," &
"521 (bc_1, *, control, 1)," &
"522 (bc_1, USB_DRVVBUS, output3, X, 521, 1, Z)";
attribute DESIGN_WARNING of TMS320DM335: entity is
"According to simulation, BSD JTAG TAP may not work correctly unless " &
"device has completed Power on Reset sequence first. " ;
end TMS320DM335;