BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: ZL30122


-- **********************************************************************
--
--  FILE :  zl30122ggg.bsd
--  generated by Cz. P. as zl30122 on Mon May  1 15:26:42 EDT 2006
--  using p.jtag.bsd rev 3.3 July 18, 2003
--
--  BSDL description for top level entity zl30122
--  Device : ZL30122  Sonet SDH Low Jitter Line Card Sync
--  Package : 100-pin CABGA
-- 
--  Number of BSC cells: 85
-- 
-- **********************************************************************
--  Modification History:
--       Initial release:   Mon May  1 15:26:42 EDT 2006
--  ********************************************************************
--
--                        IMPORTANT NOTICE
--
--  This information is for modeling purposes only, and is not guaranteed.
--
--  This information is provided "as is" without warranty of any kind.
--  It may contain technical inaccuracies or typographical errors.
--
--  ZARLINK and ZL30122 are trademarks of ZARLINK Semiconductor. ZARLINK
--  products, marketed under trademarks, are protected under numerous US
--  and foreign patents and pending applications,  maskwork rights,  and
--  copyrights.
--
--  ZARLINK reserves the right to make changes to any products and 
--  services at any time without notice.  ZARLINK assumes no
--  responsibility or liability arising out of the application or use of
--  any information, product, or service described herein except as
--  expressly agreed to in writing by ZARLINK Corporation. ZARLINK 
--  customers are advised to obtain the latest version of device 
--  specifications before relying on any published information and before
--  placing orders for products or services.
--

--  ********************************************************************
--
--                             SPECIAL NOTES
--
--    1. All instruction opcodes other than those defined in this file
--       should be considered PRIVATE.
--
--  ********************************************************************



entity zl30122 is

  generic(PHYSICAL_PIN_MAP : string := "BGA_PACKAGE");

port (
      	AVCORE: linkage bit_vector (1 to 3);
      	CS_B: in bit;
      	DIFF_CLK_N: linkage bit;
      	DIFF_CLK_P: linkage bit;
      	DIFF_EN: in bit;
      	DPLL_HOLDOVER: out bit;
      	DPLL_LOCK: out bit;
      	DPLL_MOD_SEL: in bit;
     	FILTER_REF0: linkage bit;
      	FILTER_REF1: linkage bit;
     	IC_GND1: linkage bit;
      	IC_GND2: linkage bit;
      	IC_OPEN: linkage bit;
      	INT_B: out bit;
      	NC: linkage bit;
      	OSC_I: linkage bit;
      	OSC_O: linkage bit;
      	P_CLK: out bit;
      	P_FP: out bit;
      	REF: in bit_vector (0 to 2);
      	RST_B: in bit;
      	SCK: inout bit;
      	SDH_CLK: out bit;
      	SDH_FILTER: linkage bit;
      	SDH_FP: out bit;
      	SI: inout bit;
      	SO: out bit;
      	SYNC: in bit_vector (0 to 2);
      	TCK: in bit;
      	TDI: in bit;
      	TDO: out bit;
      	TMS: in bit;
      	TRST_B: in bit;
     	VCORE1: linkage bit;
      	VCORE2: linkage bit;
      	AVDD: linkage bit_vector (1 to 2);
      	AVSS: linkage bit_vector (1 to 4);
      	VDD: linkage bit_vector (1 to 7);
      	VSS: linkage bit_vector (1 to 10)
);

 

  use STD_1149_1_2001.all;

  attribute COMPONENT_CONFORMANCE of zl30122 : entity is
        "STD_1149_1_2001";

  attribute PIN_MAP of zl30122 : entity is PHYSICAL_PIN_MAP;
  constant BGA_PACKAGE : PIN_MAP_STRING :=
  "AVCORE           :(B6       , " & -- AVCORE[1]       
                     "C7       , " & -- AVCORE[2]       
                     "F1      ), " & -- AVCORE[3]       
  "CS_B             : C2       , " &  
  "DIFF_CLK_N       : B8       , " &  
  "DIFF_CLK_P       : A7       , " &  
  "DIFF_EN          : B3       , " &  
  "DPLL_HOLDOVER    : H1       , " &  
  "DPLL_LOCK        : E1       , " &  
  "DPLL_MOD_SEL     : B2       , " &  
  "FILTER_REF0      : B5       , " &  
  "FILTER_REF1      : C5       , " &  
  "IC_GND1          : H6       , " &  
  "IC_GND2          : H2       , " &  
  "IC_OPEN          : F5       , " &  
  "INT_B            : E2       , " &  
  "NC               : H7       , " &  
  "OSC_I            : H4       , " &  
  "OSC_O            : H5       , " &  
  "P_CLK            : G8       , " &  
  "P_FP             : G7       , " &  
  "REF              :(B1       , " & -- REF[0]          
                     "A3       , " & -- REF[1]          
                     "B4      ), " & -- REF[2]          
  "RST_B            : G5       , " &  
  "SCK              : C1       , " &  
  "SDH_CLK          : D8       , " &  
  "SDH_FILTER       : A5       , " &  
  "SDH_FP           : D7       , " &  
  "SI               : D2       , " &  
  "SO               : D1       , " &  
  "SYNC             :(A1       , " & -- SYNC[0]         
                     "A2       , " & -- SYNC[1]         
                     "A4      ), " & -- SYNC[2]         
  "TCK              : H3       , " &  
  "TDI              : G2       , " &  
  "TDO              : G4       , " &  
  "TMS              : F2       , " &  
  "TRST_B           : G3       , " &  
  "VCORE1           : E6       , " &  
  "VCORE2           : F3       , " &  
  "AVDD             :(B7,   C4)," &
  "AVSS             :(A6,   A8,   C6,   G1)," &
  "VDD              :(C3,   C8,   E8,   F6,   F8,   G6,   H8)," &
  "VSS              :(D3,   D4,   D5,   D6,   E3,   E4,   E5,   E7,   F4,   F7)";
   
  attribute TAP_SCAN_IN    of TDI     : signal is true;
  attribute TAP_SCAN_MODE  of TMS     : signal is true;
  attribute TAP_SCAN_OUT   of TDO     : signal is true;
  attribute TAP_SCAN_CLOCK of TCK     : signal is (10.0e6,BOTH);
  attribute TAP_SCAN_RESET of TRST_B   : signal is true;


--
-- NOTE:  All instruction opcodes other than those defined in this file
--        should be considered PRIVATE.
--

  attribute INSTRUCTION_LENGTH of zl30122 : entity is 16;
  attribute INSTRUCTION_OPCODE of zl30122 : entity is
    "bypass           (0000000000000000)," &
    "bypass           (1111111111111111)," &
    "clamp            (1111111111101111)," &
    "extest           (1111111111101000)," &
    "highz            (1111111111001111)," &
    "idcode           (1111111111111110)," &
    "preload          (1111111111111000)," &
    "sample           (1111111111111000)";

  attribute INSTRUCTION_CAPTURE of zl30122 : entity is "xxxxxxxxxxxxxx01";

  attribute IDCODE_REGISTER of zl30122 : entity is
        "0001" & 		-- version
        "0111010110101010" &    -- part number
        "00010100101" &		-- manufacturer id
        "1";


  attribute REGISTER_ACCESS of zl30122 : entity is
    "boundary (extest, sample, preload)," &
    "bypass (bypass, clamp, highz)," &
    "device_id (idcode)" ;
 
  attribute BOUNDARY_LENGTH of zl30122 : entity is 85;
 
  attribute BOUNDARY_REGISTER of zl30122 : entity is

--       num      cell  port                    function       safe ccel  disval  rslt

	" 0     ( BC_0, *,                      internal,      X)                        ," &
	" 1     ( BC_0, *,                      internal,      X)                        ," &
	" 2     ( BC_0, *,                      internal,      X)                        ," &
	" 3     ( BC_4, RST_B,                  input,         X)                        ," &
	" 4     ( BC_0, *,                      internal,      X)                        ," &
	" 5     ( BC_0, *,                      internal,      X)                        ," &
	" 6     ( BC_0, *,                      internal,      X)                        ," &
	" 7     ( BC_0, *,                      internal,      X)                        ," &
	" 8     ( BC_0, *,                      internal,      X)                        ," &
	" 9     ( BC_0, *,                      internal,      X)                        ," &
	" 10    ( BC_0, *,                      internal,      1)                        ," &
	" 11    ( BC_0, *,                      internal,      X)                        ," &
	" 12    ( BC_0, *,                      internal,      1)                        ," &
	" 13    ( BC_2, P_FP,                   output3,       X,   14,    1,      Z)    ," &
	" 14    ( BC_2, *,                      control,       1)                        ," &
	" 15    ( BC_2, P_CLK,                  output3,       X,   16,    1,      Z)    ," &
	" 16    ( BC_2, *,                      control,       1)                        ," &
	" 17    ( BC_0, *,                      internal,      X)                        ," &
	" 18    ( BC_0, *,                      internal,      1)                        ," &
	" 19    ( BC_0, *,                      internal,      X)                        ," &
	" 20    ( BC_0, *,                      internal,      1)                        ," &
	" 21    ( BC_0, *,                      internal,      X)                        ," &
	" 22    ( BC_0, *,                      internal,      1)                        ," &
	" 23    ( BC_0, *,                      internal,      X)                        ," &
	" 24    ( BC_0, *,                      internal,      1)                        ," &
	" 25    ( BC_0, *,                      internal,      X)                        ," &
	" 26    ( BC_0, *,                      internal,      1)                        ," &
	" 27    ( BC_2, SDH_FP,                 output3,       X,   28,    1,      Z)    ," &
	" 28    ( BC_2, *,                      control,       1)                        ," &
	" 29    ( BC_2, SDH_CLK,                output3,       X,   30,    1,      Z)    ," &
	" 30    ( BC_2, *,                      control,       1)                        ," &
	" 31    ( BC_0, *,                      internal,      X)                        ," &
	" 32    ( BC_0, *,                      internal,      X)                        ," &
	" 33    ( BC_0, *,                      internal,      X)                        ," &
	" 34    ( BC_0, *,                      internal,      X)                        ," &
	" 35    ( BC_0, *,                      internal,      X)                        ," &
	" 36    ( BC_0, *,                      internal,      X)                        ," &
	" 37    ( BC_0, *,                      internal,      X)                        ," &
	" 38    ( BC_0, *,                      internal,      X)                        ," &
	" 39    ( BC_0, *,                      internal,      X)                        ," &
	" 40    ( BC_0, *,                      internal,      X)                        ," &
	" 41    ( BC_0, *,                      internal,      X)                        ," &
	" 42    ( BC_0, *,                      internal,      X)                        ," &
	" 43    ( BC_4, REF(2),                 input,         X)                        ," &
	" 44    ( BC_4, SYNC(2),                input,         X)                        ," &
	" 45    ( BC_4, REF(1),                 input,         X)                        ," &
	" 46    ( BC_4, SYNC(1),                input,         X)                        ," &
	" 47    ( BC_4, SYNC(0),                input,         X)                        ," &
	" 48    ( BC_4, REF(0),                 input,         X)                        ," &
	" 49    ( BC_0, *,                      internal,      X)                        ," &
	" 50    ( BC_0, *,                      internal,      X)                        ," &
	" 51    ( BC_0, *,                      internal,      1)                        ," &
	" 52    ( BC_0, *,                      internal,      X)                        ," &
	" 53    ( BC_0, *,                      internal,      X)                        ," &
	" 54    ( BC_0, *,                      internal,      X)                        ," &
	" 55    ( BC_0, *,                      internal,      X)                        ," &
	" 56    ( BC_4, DPLL_MOD_SEL,           input,         X)                        ," &
	" 57    ( BC_4, DIFF_EN,                input,         X)                        ," &
	" 58    ( BC_0, *,                      internal,      X)                        ," &
	" 59    ( BC_0, *,                      internal,      X)                        ," &
	" 60    ( BC_0, *,                      internal,      X)                        ," &
	" 61    ( BC_0, *,                      internal,      X)                        ," &
	" 62    ( BC_7, SCK,                    bidir,         X,   63,    1,      Z)    ," &
	" 63    ( BC_2, *,                      control,       1)                        ," &
	" 64    ( BC_4, CS_B,                   input,         X)                        ," &
	" 65    ( BC_0, *,                      internal,      X)                        ," &
	" 66    ( BC_0, *,                      internal,      X)                        ," &
	" 67    ( BC_7, SI,                     bidir,         X,   68,    1,      Z)    ," &
	" 68    ( BC_2, *,                      control,       1)                        ," &
	" 69    ( BC_2, SO,                     output3,       X,   70,    1,      Z)    ," &
	" 70    ( BC_2, *,                      control,       1)                        ," &
	" 71    ( BC_2, INT_B,                  output3,       X,   72,    1,      Z)    ," &
	" 72    ( BC_2, *,                      control,       1)                        ," &
	" 73    ( BC_0, *,                      internal,      X)                        ," &
	" 74    ( BC_2, DPLL_LOCK,              output3,       X,   77,    1,      Z)    ," &
	" 75    ( BC_0, *,                      internal,      X)                        ," &
	" 76    ( BC_2, DPLL_HOLDOVER,          output3,       X,   77,    1,      Z)    ," &
	" 77    ( BC_0, *,                      control,       1)                        ," &
	" 78    ( BC_0, *,                      internal,      X)                        ," &
	" 79    ( BC_0, *,                      internal,      X)                        ," &
	" 80    ( BC_0, *,                      internal,      X)                        ," &
	" 81    ( BC_0, *,                      internal,      X)                        ," &
	" 82    ( BC_0, *,                      internal,      X)                        ," &
	" 83    ( BC_0, *,                      internal,      X)                        ," &
	" 84    ( BC_0, *,                      internal,      X)                        ";

end zl30122;

------------- end of BSDL description for the zl30122 ----------