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ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: C8051F000 Download View details  


-----------------------------------------------------------------------
--File:	C8051F000.bsd
--Author:	BD
--Created:	29 AUG 2006
--Version:	1.2
--Copyright 2006 Silicon Laboratories Inc. (All rights reserved)
--
--BSDL description for the C8051F000/005/010/015/018 TQFP-64 package
--
--Some port names differ from the pinout to conform to
--BSDL syntax.  These variations are marked in the comments.
--
--The following pins have been defined as "LINKAGE" in order to 
--conform to BSDL standard:  
--AIN0-7, XTAL2, VREF, CP0P, CP0N, CP1P, CP1N, DAC0, DAC1,
--VDD, AV+, AGND, DGND
-----------------------------------------------------------------------


entity C8051F000 is
generic(PHYSICAL_PIN_MAP: string := "TQFP_64");

port(
	AIN0 	: LINKAGE BIT;
	AIN1 	: LINKAGE BIT;
	AIN2 	: LINKAGE BIT;
	AIN3 	: LINKAGE BIT;
	AIN4 	: LINKAGE BIT;
	AIN5 	: LINKAGE BIT;
	AIN6 	: LINKAGE BIT;
	AIN7 	: LINKAGE BIT;
	
	P0_0	: INOUT BIT;
	P0_1	: INOUT BIT;
	P0_2	: INOUT BIT;	
	P0_3	: INOUT BIT;
	P0_4	: INOUT BIT;
	P0_5	: INOUT BIT;
	P0_6	: INOUT BIT;
	P0_7	: INOUT BIT;
	
	P1_0	: INOUT BIT;
	P1_1	: INOUT BIT;
	P1_2	: INOUT BIT;
	P1_3	: INOUT BIT;
	P1_4	: INOUT BIT;
	P1_5	: INOUT BIT;
	P1_6	: INOUT BIT;
	P1_7	: INOUT BIT;
	
	P2_0	: INOUT BIT;
	P2_1	: INOUT BIT;
	P2_2	: INOUT BIT;
	P2_3	: INOUT BIT;
	P2_4	: INOUT BIT;
	P2_5	: INOUT BIT;
	P2_6	: INOUT BIT;
	P2_7	: INOUT BIT;
	
	P3_0	: INOUT BIT;
	P3_1	: INOUT BIT;
	P3_2	: INOUT BIT;
	P3_3	: INOUT BIT;
	P3_4	: INOUT BIT;
	P3_5	: INOUT BIT;
	P3_6	: INOUT BIT;
	P3_7	: INOUT BIT;
	
	TCK	: IN BIT;
	TMS	: IN BIT;
	TDI	: IN BIT;
	TDO	: OUT BIT;
	
	XTAL1	: IN BIT;
	XTAL2	: LINKAGE BIT;
	RST	: INOUT BIT;			--/RST
	VREF	: LINKAGE BIT;
	CP0P	: LINKAGE BIT;			--CPO+
	CP0N	: LINKAGE BIT;			--CPO-
	CP1P	: LINKAGE BIT;			--CP1+
	CP1N	: LINKAGE BIT;			--CP1-
	DAC0	: LINKAGE BIT;
	DAC1	: LINKAGE BIT;
	
	VDD1	: LINKAGE BIT;			--VDD
	VDD2	: LINKAGE BIT;			--VDD
	VDD3	: LINKAGE BIT;			--VDD
	DGND1	: LINKAGE BIT;			--DGND
	DGND2	: LINKAGE BIT;			--DGND
	DGND3	: LINKAGE BIT;			--DGND
	AV1	: LINKAGE BIT;			--AV+
	AV2	: LINKAGE BIT;			--AV+
	AGND1	: LINKAGE BIT;			--AGND
	AGND2	: LINKAGE BIT			--AGND
);



use STD_1149_1_2001.all;

attribute COMPONENT_CONFORMANCE of C8051F000 : entity is "STD_1149_1_2001";

attribute PIN_MAP of C8051F000 : entity is PHYSICAL_PIN_MAP;

constant TQFP_64 : PIN_MAP_STRING :=
	"AIN0	: 7,"&
	"AIN1	: 8,"&
	"AIN2	: 9,"&
	"AIN3	: 10,"&
	"AIN4	: 11,"&
	"AIN5	: 12,"&
	"AIN6	: 13,"&
	"AIN7	: 14,"&
	
	"P0_0	: 39,"&	
	"P0_1	: 42,"&
	"P0_2	: 47,"&
	"P0_3	: 48,"&
	"P0_4	: 49,"&
	"P0_5	: 50,"&
	"P0_6	: 55,"&
	"P0_7	: 56,"&
	
	"P1_0	: 38,"&
	"P1_1	: 37,"&
	"P1_2	: 36,"&
	"P1_3	: 35,"&
	"P1_4	: 34,"&
	"P1_5	: 32,"&
	"P1_6	: 60,"&
	"P1_7	: 59,"&
	
	"P2_0	: 33,"&
	"P2_1	: 27,"&
	"P2_2	: 54,"&
	"P2_3	: 53,"&
	"P2_4	: 52,"&
	"P2_5	: 51,"&
	"P2_6	: 44,"&
	"P2_7	: 43,"&
	
	"P3_0	: 26,"&
	"P3_1	: 25,"&
	"P3_2	: 24,"&
	"P3_3	: 23,"&
	"P3_4	: 58,"&
	"P3_5	: 57,"&
	"P3_6	: 46,"&
	"P3_7	: 45,"&

	"TCK	: 22,"&
	"TMS	: 21,"&
	"TDI	: 28,"&
	"TDO	: 29,"&

	"XTAL1	: 18,"&
	"XTAL2	: 19,"&
	"RST	: 20,"&
	"VREF	: 6,"&
	"CP0P	: 4,"&		
	"CP0N	: 3,"&		
	"CP1P	: 2,"&
	"CP1N	: 1,"&
	"DAC0	: 64,"&
	"DAC1	: 63,"&

	"VDD1	: 31,"&
	"VDD2	: 40,"&
	"VDD3	: 62,"&
	"DGND1	: 30,"&
	"DGND2	: 41,"&
	"DGND3	: 61,"&
	"AV1	: 16,"&
	"AV2	: 17,"&
	"AGND1	: 5,"&
	"AGND2	: 15";


attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.00e6,BOTH);


attribute INSTRUCTION_LENGTH of C8051F000 : entity is 16;


attribute INSTRUCTION_OPCODE of C8051F000 : entity is 
"PRELOAD (0000000000000010)," &
"BYPASS (1111111111111111)," &
"IDCODE (0000000000000100)," &
"SAMPLE (0000000000000010)," &
"EXTEST (0000000000000000)";


attribute INSTRUCTION_CAPTURE of C8051F000 : entity is "0000000000000001";


attribute IDCODE_REGISTER of C8051F000 : entity is
	"XXXX"	&		--version
	"0000000000000010"  &	--part number
	"00100100001"	&	--manufacturer ID
	"1";			--mandatory LSB


attribute REGISTER_ACCESS of C8051F000 : entity is 
	"BOUNDARY (EXTEST,SAMPLE)," 	&
	"BYPASS (BYPASS),"		&
	"DEVICE_ID (IDCODE)";
	

attribute BOUNDARY_LENGTH of C8051F000 : entity is 87;


attribute BOUNDARY_REGISTER of C8051F000 : entity is 

	"0	(BC_2, *, control, 0),"&
	"1	(BC_7, RST, bidir, X, 0, 0, Z),"&
	"2	(BC_4, XTAL1, clock, X),"&
	"3	(BC_4, *, internal, X),"&
	"4	(BC_4, *, internal, 0),"&
	"5	(BC_4, *, internal, 0),"&
	"6	(BC_4, *, internal, 0),"&
	"7	(BC_4, *, internal, 0),"&
	"8	(BC_4, *, internal, 0),"&
	"9	(BC_4, *, internal, 0),"&
	"10	(BC_4, *, internal, 0),"&
	"11	(BC_4, *, internal, 0),"&
	"12	(BC_4, *, internal, 0),"&
	"13	(BC_4, *, internal, 0),"&
	"14	(BC_4, *, internal, 0),"&
	"15	(BC_4, *, internal, 0),"&
	"16	(BC_4, *, internal, 0),"&
	"17	(BC_4, *, internal, 0),"&
	"18	(BC_4, *, internal, 0),"&
	"19	(BC_4, *, internal, 0),"&
	"20	(BC_4, *, internal, 0),"&
	"21	(BC_4, *, internal, 0),"&
	"22	(BC_4, *, internal, 0),"&

	-- Pin 0.x output enables and I/O
	"23	(BC_2, *, control, 0),"&			--P0_0 OE
	"24	(BC_7, P0_0, bidir, X, 23, 0, Z),"&		--P0_0 I/0
	"25	(BC_2, *, control, 0),"&
	"26	(BC_7, P0_1, bidir, X, 25, 0, Z),"&
	"27	(BC_2, *, control, 0),"&
	"28	(BC_7, P0_2, bidir, X, 27, 0, Z),"&
	"29	(BC_2, *, control, 0),"&
	"30	(BC_7, P0_3, bidir, X, 29, 0, Z),"&
	"31	(BC_2, *, control, 0),"&
	"32	(BC_7, P0_4, bidir, X, 31, 0, Z),"&
	"33	(BC_2, *, control, 0),"&	
	"34	(BC_7, P0_5, bidir, X, 33, 0, Z),"&
	"35	(BC_2, *, control, 0),"&	
	"36	(BC_7, P0_6, bidir, X, 35, 0, Z),"&
	"37	(BC_2, *, control, 0),"&	
	"38	(BC_7, P0_7, bidir, X, 37, 0, Z),"&

	--Pin 1.x output enables and I/O		
	"39	(BC_2, *, control, 0),"&			--P1_0 OE
	"40	(BC_7, P1_0, bidir, X, 39, 0, Z),"&		--P1_0 I/0
	"41	(BC_2, *, control, 0),"&
	"42	(BC_7, P1_1, bidir, X, 41, 0, Z),"&
	"43	(BC_2, *, control, 0),"&
	"44	(BC_7, P1_2, bidir, X, 43, 0, Z),"&
	"45	(BC_2, *, control, 0),"&
	"46	(BC_7, P1_3, bidir, X, 45, 0, Z),"&
	"47	(BC_2, *, control, 0),"&
	"48	(BC_7, P1_4, bidir, X, 47, 0, Z),"&
	"49	(BC_2, *, control, 0),"&
	"50	(BC_7, P1_5, bidir, X, 49, 0, Z),"&
	"51	(BC_2, *, control, 0),"&
	"52	(BC_7, P1_6, bidir, X, 51, 0, Z),"&
	"53	(BC_2, *, control, 0),"&
	"54	(BC_7, P1_7, bidir, X, 53, 0, Z),"&


	--Pin 2.x output enables and I/O		
	"55	(BC_2, *, control, 0),"&			--P2_0 OE
	"56	(BC_7, P2_0, bidir, X, 55, 0, Z),"&		--P2_0 I/0
	"57	(BC_2, *, control, 0),"&
	"58	(BC_7, P2_1, bidir, X, 57, 0, Z),"&
	"59	(BC_2, *, control, 0),"&
	"60	(BC_7, P2_2, bidir, X, 59, 0, Z),"&
	"61	(BC_2, *, control, 0),"&
	"62	(BC_7, P2_3, bidir, X, 61, 0, Z),"&
	"63	(BC_2, *, control, 0),"&
	"64	(BC_7, P2_4, bidir, X, 63, 0, Z),"&
	"65	(BC_2, *, control, 0),"&
	"66	(BC_7, P2_5, bidir, X, 65, 0, Z),"&
	"67	(BC_2, *, control, 0),"&
	"68	(BC_7, P2_6, bidir, X, 67, 0, Z),"&
	"69	(BC_2, *, control, 0),"&
	"70	(BC_7, P2_7, bidir, X, 69, 0, Z),"&


	--Pin 3.x output enables and I/O		
	"71	(BC_2, *, control, 0),"&			--P3_0 OE
	"72	(BC_7, P3_0, bidir, X, 71, 0, Z),"&		--P3_0 I/0
	"73	(BC_2, *, control, 0),"&
	"74	(BC_7, P3_1, bidir, X, 73, 0, Z),"&
	"75	(BC_2, *, control, 0),"&
	"76	(BC_7, P3_2, bidir, X, 75, 0, Z),"&
	"77	(BC_2, *, control, 0),"&
	"78	(BC_7, P3_3, bidir, X, 77, 0, Z),"&
	"79	(BC_2, *, control, 0),"&	
	"80	(BC_7, P3_4, bidir, X, 79, 0, Z),"&
	"81	(BC_2, *, control, 0),"&
	"82	(BC_7, P3_5, bidir, X, 81, 0, Z),"&
	"83	(BC_2, *, control, 0),"&
	"84	(BC_7, P3_6, bidir, X, 83, 0, Z),"&
	"85	(BC_2, *, control, 0),"&
	"86	(BC_7, P3_7, bidir, X, 85, 0, Z)";

end C8051F000;

This library contains 7716 BSDL files (for 6087 distinct entities) from 66 vendors
Last BSDL model (chip) was added on Oct 17, 2017 16:06
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